TVP5146_12_技术文档

Contents

Section

Title

Page

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

2

3

4

5

6

1.1

1.2

1.3

1.4

1.5

1.6

1.7

Detailed Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

2.1

Analog Processing and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . .

9

2.1.1

2.1.2

2.1.3

2.1.4

Video Input Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Input Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog-to-Digital Converters (ADCs) . . . . . . . . . . . . . . . . . .

9

10

11

15

16

17

18

19

24

25

27

28

29

30

35

36

2.2

Digital Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2ꢀ Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Composite Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Component Video Processor . . . . . . . . . . . . . . . . . . . . . . . . .

Color Space Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

2.4

2.5

Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Real-Time Control (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1

2.5.2

2.5.3

Fast Switches for SCART . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Separate Syncs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Embedded Syncs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6

2.7

I²C Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1

2.6.2

2.6.3

2.6.4

Reset and I²C Bus Address Selection . . . . . . . . . . . . . . . . .

I²C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VBUS Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I²C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VBI Data Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1

2.7.2

Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Adjusting External Syncs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VBI FIFO and Ancillary Data in Video Stream . . . . . . . . . . .

VBI Raw Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8

2.9

2.10 Internal Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.1

2.11.2

2.11.3

Input Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AFE Gain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

Video Standard Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

2.11.4

2.11.5

2.11.6

2.11.7

2.11.8

2.11.9

Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Autoswitch Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

Color Killer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Luminance Processing Control 1 Register . . . . . . . . . . . . . .

Luminance Processing Control 2 Register . . . . . . . . . . . . . .

Luminance Processing Control 3 Register . . . . . . . . . . . . . .

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

2.11.10 Luminance Brightness Register . . . . . . . . . . . . . . . . . . . . . . .

2.11.11 Luminance Contrast Register . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.12 Chrominance Saturation Register . . . . . . . . . . . . . . . . . . . . .

2.11.13 Chroma Hue Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.14 Chrominance Processing Control 1 Register . . . . . . . . . . .

2.11.15 Chrominance Processing Control 2 Register . . . . . . . . . . .

2.11.16 Component Pr Saturation Register . . . . . . . . . . . . . . . . . . . .

2.11.17 Component Y Contrast Register . . . . . . . . . . . . . . . . . . . . . .

2.11.18 Component Pb Saturation Register . . . . . . . . . . . . . . . . . . .

2.11.19 Component Y Brightness Register . . . . . . . . . . . . . . . . . . . .

2.11.20 AVID Start Pixel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.21 AVID Stop Pixel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.22 HSYNC Start Pixel Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.23 HSYNC Stop Pixel Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.24 VSYNC Start Line Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.25 VSYNC Stop Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.26 VBLK Start Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.27 VBLK Stop Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.28 Fast-Switch Control Register . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.29 Fast-Switch SCART Delay Register . . . . . . . . . . . . . . . . . . .

2.11.30 SCART Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.31 CTI Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.32 CTI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.33 RTC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.34 Sync Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.35 Output Formatter 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.36 Output Formatter 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.37 Output Formatter 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.38 Output Formatter 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.39 Output Formatter 5 Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.40 Output Formatter 6 Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.41 Clear Lost Lock Detect Register . . . . . . . . . . . . . . . . . . . . . .

2.11.42 Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.43 Status 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.44 AGC Gain Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.45 Video Standard Status Register . . . . . . . . . . . . . . . . . . . . . .

2.11.46 GPIO Input 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.47 GPIO Input 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

2.11.48 Vertical Line Count Register . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.49 AFE Coarse Gain for CH 1 Register . . . . . . . . . . . . . . . . . . .

2.11.50 AFE Coarse Gain for CH 2 Register . . . . . . . . . . . . . . . . . . .

2.11.51 AFE Coarse Gain for CH 3 Register . . . . . . . . . . . . . . . . . . .

2.11.52 AFE Coarse Gain for CH 4 Register . . . . . . . . . . . . . . . . . . .

2.11.53 AFE Fine Gain for Pb_B Register . . . . . . . . . . . . . . . . . . . . .

2.11.54 AFE Fine Gain for Y_G_Chroma Register . . . . . . . . . . . . . .

2.11.55 AFE Fine Gain for R_Pr Register . . . . . . . . . . . . . . . . . . . . .

2.11.56 AFE Fine Gain for CVBS_Luma Register . . . . . . . . . . . . . .

2.11.57 ROM Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.58 AGC White Peak Processing Register . . . . . . . . . . . . . . . . .

2.11.59 AGC Increment Speed Register . . . . . . . . . . . . . . . . . . . . . .

2.11.60 AGC Increment Delay Register . . . . . . . . . . . . . . . . . . . . . . .

2.11.61 Chip ID MSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.62 Chip ID LSB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.63 VDP TTX Filter And Mask Registers . . . . . . . . . . . . . . . . . . .

2.11.64 VDP TTX Filter Control Register . . . . . . . . . . . . . . . . . . . . . .

2.11.65 VDP FIFO Word Count Register . . . . . . . . . . . . . . . . . . . . . .

2.11.66 VDP FIFO Interrupt Threshold Register . . . . . . . . . . . . . . . .

2.11.67 VDP FIFO Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.68 VDP FIFO Output Control Register . . . . . . . . . . . . . . . . . . . .

2.11.69 VDP Line Number Interrupt Register . . . . . . . . . . . . . . . . . .

2.11.70 VDP Pixel Alignment Register . . . . . . . . . . . . . . . . . . . . . . . .

2.11.71 VDP Line Start Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.72 VDP Line Stop Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.73 VDP Global Line Mode Register . . . . . . . . . . . . . . . . . . . . . .

2.11.74 VDP Full Field Enable Register . . . . . . . . . . . . . . . . . . . . . . .

2.11.75 VDP Full Field Mode Register . . . . . . . . . . . . . . . . . . . . . . . .

56

57

58

59

60

61

62

63

64

65

66

67

68

69

2.11.76 VBUS Data Access With No VBUS Address Increment

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69

2.11.77 VBUS Data Access With VBUS Address Increment

Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69

70

71

72

73

74

75

76

77

78

79

2.11.78 FIFO Read Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.79 VBUS Address Access Register . . . . . . . . . . . . . . . . . . . . . .

2.11.80 Interrupt Raw Status 0 Register . . . . . . . . . . . . . . . . . . . . . . .

2.11.81 Interrupt Raw Status 1 Register . . . . . . . . . . . . . . . . . . . . . . .

2.11.82 Interrupt Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.83 Interrupt Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.84 Interrupt Mask 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.85 Interrupt Mask 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.86 Interrupt Clear 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.87 Interrupt Clear 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 VBUS Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.1

VDP Closed Caption Data Register . . . . . . . . . . . . . . . . . . .

v

2.12.2

2.12.3

2.12.4

2.12.5

2.12.6

2.12.7

2.12.8

2.12.9

VDP WSS Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VDP VITC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VDP V-Chip TV Rating Block 1 Register . . . . . . . . . . . . . . .

VDP V-Chip TV Rating Block 2 Register . . . . . . . . . . . . . . .

VDP V-Chip TV Rating Block 3 Register . . . . . . . . . . . . . . .

VDP V-Chip MPAA Rating Data Register . . . . . . . . . . . . . . .

VDP General Line Mode and Line Address Register . . . . .

VDP VPS/Gemstar Data Register . . . . . . . . . . . . . . . . . . . . .

79

80

81

82

83

84

85

86

87

89

90

91

93

94

2.12.10 VDP FIFO Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.11 Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . .

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

4

3.1

3.2

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1

Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1

3.3.2

3.3.3

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Processing and A/D Converters . . . . . . . . . . . . . . . .

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Example Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1

4.2

4.3

Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1

4.1.2

Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1

4.2.2

Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1

4.3.2

Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1

5.2

Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Designing With PowerPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Illustrations

Figure

1−1

1−2

2−1

2−2

2−3

2−4

2−5

Title

Page

4

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Processors and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital Video Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Composite and S-Video Processor Block Diagram . . . . . . . . . . . . . . . . . .

Color Low-Pass Filter Frequency Response . . . . . . . . . . . . . . . . . . . . . . . .

5

9

11

12

13

Color Low-Pass Filter With Filter Frequency Response, NTSC Square

Pixel Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

14

2−6

2−7

2−8

2−9

Color Low-Pass Filter With Filter Characteristics,

NTSC/PAL ITU-R BT.601 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Color Low-Pass Filter With Filter Characteristics, PAL Square Pixel

Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chroma Trap Filter Frequency Response, NTSC Square Pixel

Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601

Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 Chroma Trap Filter Frequency Response, PAL ITU-R BT.601

Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 Chroma Trap Filter Frequency Response, PAL Square Pixel

Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

15

16

17

18

20

21

22

23

24

26

29

66

87

2−12 Luminance Edge-Enhancer Peaking Block Diagram . . . . . . . . . . . . . . . . .

2−13 Peaking Filter Response, NTSC Square Pixel Sampling . . . . . . . . . . . . .

2−14 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling . . . . . . . .

2−15 Peaking Filter Response, PAL Square Pixel Sampling . . . . . . . . . . . . . . .

2−16 Y Component Gain, Offset, Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−17 CbCr Component Gain, Offset, Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−18 Reference Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−19 RTC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−20 Vertical Synchronization Signals for 525-Line System . . . . . . . . . . . . . . . .

2−21 Vertical Synchronization Signals for 625-Line System . . . . . . . . . . . . . . . .

2−22 Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode . . . . . . . . . . . .

2−23 Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode . . . . . . . . . . . .

2−24 VSYNC Position With Respect to HSYNC . . . . . . . . . . . . . . . . . . . . . . . . . .

2−25 VBUS Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−26 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−27 Teletext Filter Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1

Clocks, Video Data, and Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

3−2

5−1

I²C Host Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

88

93

List of Tables

Table

Title

Page

1−1

2−1

2−2

2−3

2−4

2−5

2−6

2−7

2−8

2−9

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Summary of Line Frequencies, Data Rates, and Pixel/Line Counts . . . .

EAV and SAV Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I²C Host Interface Terminal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I²C Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supported VBI Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ancillary Data Format and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VBI Raw Data Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

18

19

24

25

27

28

29

31

34

35

2−10 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 VBUS Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 Analog Channel and Video Mode Selection . . . . . . . . . . . . . . . . . . . . . . . .

viii

1

Introduction

The TVP5146 device is a high quality, single-chip digital video decoder that digitizes and

decodes all popular baseband analog video formats into digital component video. The TVP5146

decoder supports the analog-to-digital (A/D) conversion of component RGB and YPbPr signals,

as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-video

into component YCbCr. This decoder includes four 10-bit 30-MSPS A/D converters (ADCs).

Preceding each ADC in the device, the corresponding analog channel contains an analog circuit

that clamps the input to a reference voltage and applies a programmable gain and offset. A total

of 10 video input terminals can be configured to a combination of RGB, YPbPr, CVBS, or

S-video video inputs.

Component, composite, or S-video signals are sampled at 2× the square-pixel or ITU-R BT.601

clock frequency, line-locked, and are then decimated to the 1× pixel rate. CVBS decoding

utilizes five-line adaptive comb filtering for both the luma and chroma data paths to reduce both

cross-luma and cross-chroma artifacts. A chroma trap filter is also available. On CVBS and

S-video inputs, the user can control video characteristics such as contrast, brightness,

saturation, and hue via an I²C host port interface. Furthermore, luma peaking (sharpness) with

programmable gain is included, as well as a patented chroma transient improvement (CTI)

circuit.

A built-in color space converter is applied to decoded component RGB data.

The following output formats can be selected: 20-bit 4:2:2 YCbCr or 10-bit 4:2:2 YCbCr.

The TVP5146 decoder generates synchronization, blanking, field, active video window,

horizontal and vertical syncs, clock, genlock (for downstream video encoder synchronization),

host CPU interrupt and programmable logic I/O signals, in addition to digital video outputs.

The TVP5146 decoder includes methods for advanced vertical blanking interval (VBI) data

retrieval. The VBI data processor (VDP) slices, parses, and performs error checking on teletext,

closed caption (CC), and other VBI data. A built-in FIFO stores up to 11 lines of teletext data,

and with proper host port synchronization, full-screen teletext retrieval is possible. The TVP5146

decoder can pass through the output formatter 2× the sampled raw luma data for host-based

VBI processing.

The decoder provides the option for concurrent processing of pixel-locked CVBS and

RGB/YPbPr input formats.

The main blocks of the TVP5146 decoder include:

•

Robust sync detection for weak and noisy signals as well as VCR trick modes

Y/C separation by 2-D, 5-line, adaptive comb or chroma trap filter

Fast-switch input for pixel-by-pixel switching between CVBS and YPbPr/RGB component video inputs

(SCART support)

•

Four 10-bit, 30-MSPS A/D converters with analog preprocessors [clamp and automatic gain control

(AGC)]

•

Luminance processor

Chrominance processor

Macrovision is a trademark of Macrovision Corporation.

Gemstar is a trademark of Gemstar-TV Guide International.

PowerPAD is a trademark of Texas Instruments.

Other trademarks are the property of their respective owners.

1

SLES084C − August 2007

TVP5146

•

Component processor

Clock/timing processor and power-down control

Software-controlled power-saving standby mode

Output formatter

2

•

I C host port interface

VBI data processor

Macrovision copy protection detection circuit (Type 1, 2, 3, and separate color stripe detection)

3.3-V tolerant digital I/O ports

1.1 Detailed Functionality

•

Four 30-MSPS, 10-bit A/D channels with programmable gain control

Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60), SECAM (B, D, G, K, K1, L), CVBS, and

S-video

•

Supports analog component SD YPbPr/RGB video formats with embedded sync

10 analog video input terminals for multisource connection

User-programmable video output formats

−

10-bit ITU-R BT.656 4:2:2 YCbCr with embedded syncs

10-bit 4:2:2 YCbCr with separate syncs

20-bit 4:2:2 YCbCr with separate syncs

2× sampled raw VBI data in active video during a vertical blanking period

Sliced VBI data during a vertical blanking period or active video period (full field mode)

•

HSYNC/VSYNC outputs with programmable position, polarity, and width, and FID (field ID) output

Component video processing

−

Gain (contrast) and offset (brightness) adjustments

Automatic component video detection (525/625)

Color space conversion from RGB to YCbCr

•

Composite and S-video processing

−

Adaptive 2-D, 5-line, adaptive comb filter for composite video inputs; chroma trap available

Automatic video standard detection (NTSC/PAL/SECAM) and switching

Luma-peaking with programmable gain

Patented CTI circuit

Patented architecture for locking to weak, noisy, or unstable signals

Single 14.31818-MHz reference crystal for all standards (ITU-R.BT601 and square pixel)

Line-locked internal pixel sampling clock generation with horizontal- and vertical-lock signal outputs

Genlock output [real-time control (RTC] format) for downstream video encoder synchronization

•

Certified Macrovision copy protection detection

2

TVP5146

SLES084C − August 2007

•

VBI data processor

−

Teletext (NABTS, WST)

CC and extended data service (EDS)

Wide screen signaling (WSS)

Copy generation management system (CGMS)

Video program system (VPS/PDC)

Vertical interval time code (VITC)

Gemstar 1×/2× electronic program guide compatible mode

Register readback of CC, WSS (CGMS), VPS/PDC, VITC, and Gemstar 1×/2× sliced data

2

•

I C host port interface

Reduced power consumption: 1.8-V digital core, 3.3-V for digital I/O, and 1.8-V analog core with

power-save and power-down modes

•

80-terminal TQFP PowerPAD package

1.2 Applications

•

Digital TV

LCD TV/monitors

DVD-R

PVR

PC video cards

Video capture/video editing

Video conferencing

1.3 Related Products

•

TVP5150A/TVP5150AM1 Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync

Detector, (SLES098)

1.4 Ordering Information

PACKAGED DEVICES

80-TERMINAL PLASTIC FLAT-PACK PowerPAD

TVP5146PFP

T

A

TM

0°C to 70°C

3

SLES084C − August 2007

TVP5146

1.5 Functional Block Diagram

VBI

Data

Slicer

Copy

Protection

Detector

CVBS/Y/G

Analog Front End

VI_1_A

CVBS/

Pb/B/C

Composite and S-Video Processor

Y/C

VI_1_B

VI_1_C

ADC1

ADC2

ADC3

ADC4

Luma

CVBS/Y

C

Y

Separation

Processing

YCbCr

5-line

Adaptive

Comb

VI_2_A

Y[9:0]

C[9:0]

FSS

C

Chroma

Processing

CVBS/

Y/G

VI_2_B

VI_2_C

Output

Formatter

M

U

X

VI_3_A

VI_3_B

VI_3_C

Component

Processor

CVBS/

Pr/R/C

Y/G

Pb/B

Pr/R

YCbCr

Color

Gain/Offset

Space

Conversion

CVBS/Y

VI_4_A

GPIO

Sampling

Clock

Timing Processor

With Sync Detector

Host

Interface

Figure 1−1. Functional Block Diagram

4

TVP5146

SLES084C − August 2007

1.6 Terminal Assignments

PFP PACKAGE

(TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60

VI_1_B

VI_1_C

C_6/GPIO

C_7/GPIO

C_8/GPIO

C_9/GPIO

DGND

DVDD

Y_0

Y_1

Y_2

Y_3

Y_4

IOGND

IOVDD

Y_5

Y_6

Y_7

Y_8

Y_9

DGND

DVDD

1

2

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

CH1_A33GND

CH1_A33VDD

CH2_A33VDD

CH2_A33GND

VI_2_A

3

4

5

6

7

VI_2_B

VI_2_C

8

9

CH2_A18GND

CH2_A18VDD

A18VDD_REF

A18GND_REF

CH3_A18VDD

CH3_A18GND

VI_3_A

VI_3_B

VI_3_C

CH3_A33GND

CH3_A33VDD

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Figure 1−2. Terminal Assignments Diagram

5

SLES084C − August 2007

TVP5146

1.7 Terminal Functions

Table 1−1. Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

Analog Video

VI_1_A

NUMBER

80

1

VI_1_x: Analog video input for CVBS/Pb/B/C

VI_1_B

VI_2_x: Analog video input for CVBS/Y/G

VI_3_x: Analog video input for CVBS/Pr/R/C

VI_4_A: Analog video input for CVBS/Y

VI_1_C

2

VI_2_A

7

VI_2_B

8

I

Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof)

can be supported.

VI_2_C

9

VI_3_A

16

17

18

23

The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF.

VI_3_B

2

The possible input configurations are listed in the input select register at I C subaddress 00h (see Section

2.11.1).

VI_3_C

VI_4_A

Clock Signals

DATACLK

40

74

75

O

I

Line-locked data output clock

External clock reference input. It can be connected to an external oscillator with a 1.8-V compatible clock

signal or to a 14.31818-MHz crystal oscillator.

XTAL1

XTAL2

O

External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.

Digital Video

57, 58,

59, 60,

63, 64,

65, 66,

69, 70

Digital video output of CbCr, C_9 is MSB and C_0 is LSB. Unused outputs can be left unconnected. Also,

these terminals can be programmable general-purpose I/O.

C_[9:0]/

GPIO

O

For the 8-bit mode, the two LSBs are ignored.

C1 needs a pulldown resistor (see Figure 5−1).

43, 44,

45, 46,

47, 50,

51, 52,

53, 54

Digital video output of Y/YCbCr, Y_9 is MSB and Y_0 is LSB.

Y_[9:0]

For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.

Miscellaneous Signals

Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB)

and the composite video input.

FSS/GPIO

35

I/O

Programmable general-purpose I/O

Genlock control output (GLCO)

GLCO/I2CA

INTREQ

37

30

I/O

O

2

During reset, this terminal is an input used to program the I C address LSB.

Interrupt request

Power-down input:

1 = Power down

0 = Normal mode

PWDN

33

34

I

RESETB

Reset input, active low

6

TVP5146

SLES084C − August 2007

Table 1−1. Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NUMBER

Host Interface

SCL

2

28

29

I

I C clock input

2

SDA

I/O I C data bus

Power Supplies

AGND

26

13

12

I

Analog ground. Connect to analog ground.

A18GND_REF

A18VDD_REF

Analog 1.8-V return

Analog power for reference 1.8 V

CH1_A18GND

CH2_A18GND

CH3_A18GND

CH4_A18GND

79

10

15

24

I

Analog 1.8-V return

CH1_A18VDD

CH2_A18VDD

CH3_A18VDD

CH4_A18VDD

78

11

14

25

Analog power. Connect to 1.8 V.

Analog 3.3-V return

CH1_A33GND

CH2_A33GND

CH3_A33GND

CH4_A33GND

3

6

19

22

CH1_A33VDD

CH2_A33VDD

CH3_A33VDD

CH4_A33VDD

4

5

20

21

Analog power. Connect to 3.3 V.

27, 32, 42,

56, 68

DGND

DVDD

I

Digital return

31, 41, 55,

67

Digital power. Connect to 1.8 V.

IOGND

39, 49, 62

38, 48, 61

77

I

Digital power return

IOVDD

Digital power. Connect to 3.3 V or less for reduced noise.

Analog power return

PLL_A18GND

PLL_A18VDD

Sync Signals

76

Analog power. Connect to 1.8 V.

Horizontal sync output or digital composite sync output

Programmable general-purpose I/O

HS/CS/GPIO

VS/VBLK/GPIO

FID/GPIO

72

73

71

36

I/O

Vertical sync output (for modes with dedicated VSYNC) or VBLK output

Programmable general-purpose I/O

Odd/even field indicator output. This terminal needs a pulldown resistor (see Figure 5−1).

Programmable general-purpose I/O

Active video indicator output

Programmable general-purpose I/O

AVID/GPIO

7

SLES084C − August 2007

TVP5146

8

TVP5146

SLES084C − August 2007

2

Functional Description

2.1 Analog Processing and A/D Converters

Figure 2−1 shows a functional diagram of the analog processors and ADCs. This block provides

the analog interface to all video inputs. It accepts up to 10 inputs and performs source selection,

video clamping, video amplification, A/D conversion, and gain and offset adjustments to center

the digitized video signal.

TVP5146 Analog Front End

VI_1_A

CH1 A/D

M

U

X

10-Bit

ADC

Clamp

PGA

VI_1_B

VI_1_C

VI_2_A

VI_2_B

VI_2_C

CH2 A/D

M

U

X

10-Bit

ADC

Line-Locked

Sampling Clock

VI_3_A

VI_3_B

CH3 A/D

M

U

X

10-Bit

ADC

VI_3_C

CH4 A/D

10-Bit

ADC

VI_4_A

Figure 2−1. Analog Processors and A/D Converters

2.1.1 Video Input Switch Control

The TVP5146 decoder has 4 analog channels that accept up to 10 video inputs. The user can

configure the internal analog video switches via the I²C interface. The 10 analog video inputs

can be used for different input configurations, some of which are:

•

Up to 10 selectable individual composite video inputs

Up to four selectable S-video inputs

Up to three selectable analog YPbPr/RGB video inputs and one CVBS input

Up to two selectable analog YPbPr/RGB video inputs, two S-video inputs, and two CVBS inputs

The input selection is performed by the input select register at I²C subaddress 00h (see Section

2.11.1).

9

SLES084C − August 2007

TVP5146

2.1.2 Analog Input Clamping

An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The

clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference

voltage. The selection between bottom and mid clamp is performed automatically by the

TVP5146 decoder.

2.1.3 Automatic Gain Control

The TVP5146 decoder uses four programmable gain amplifiers (PGAs), one per channel. The

PGA can scale a signal with a voltage-input compliance of 0.5-V_PPto 2-V_PPto a full-scale 10-bit

A/D output code range. A 4-bit code sets the coarse gain with individual adjustment per channel.

Minimum gain corresponds to a code 0x0 (2-V_PPfull-scale input, –6-dB gain) while maximum

gain corresponds to code 0xF (0.5 V_PPfull scale, +6-dB gain). The TVP5146 decoder also has

12-bit fine gain controls for each channel and applies independently to coarse gain controls. For

composite video, the input video signal amplitude can vary significantly from the nominal level of

1 V_PP. The TVP5146 decoder can adjust its PGA setting automatically: an AGC can be enabled

and can adjust the signal amplitude such that the maximum range of the ADC is reached without

clipping. Some nonstandard video signals contain peak white levels that saturate the ADC. In

these cases, the AGC automatically cuts back gain to avoid clipping. If the AGC is on, then the

TVP5146 decoder can read the gain currently being used.

The TVP5146 AGC comprises the front-end AGC before Y/C separation and the back-end AGC

after Y/C separation. The back-end AGC restores the optimum system gain whenever an

amplitude reference such as the composite peak (which is only relevant before Y/C separation)

forces the front-end AGC to set the gain too low. The front-end and back-end AGC algorithms

can use up to four amplitude references: sync height, color burst amplitude, composite peak,

and luma peak.

The specific amplitude references being used by the front-end and back-end AGC algorithms

can be independently controlled using the AGC white peak processing register located at

subaddress 74h. The TVP5146 gain increment speed and gain increment delay can be

controlled using the AGC increment speed register located at subaddress 78h and the AGC

increment delay register located at subaddress 79h, respectively.

2.1.4 Analog-to-Digital Converters (ADCs)

All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A/D channels receive

an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and

30 MHz. All ADC reference voltages are generated internally.

2.2 Digital Video Processing

Figure 2−2 is a block diagram of the TVP5146 digital video decoder processor. This processor

receives digitized video signals from the ADCs and performs composite processing for CVBS

and S-video inputs, YCbCr signal enhancements for CVBS and S-video inputs, and YPbPr/RGB

processing for component video inputs. It also generates horizontal and vertical syncs and other

output control signals such as genlock for CVBS and S-video inputs. Additionally, it can provide

field identification, horizontal and vertical lock, vertical blanking, and active video window

indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with

external syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync

pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material.

Information present in the VBI interval can be retrieved and either inserted in the ITU-R BT.656

output as ancillary data or stored in internal FIFO and/or registers for retrieval via the host port

interface.

10

TVP5146

SLES084C − August 2007

Copy

Protection

Detector

VBI Data

Processor

Slice VBI Data

Y[9:0]

C[9:0]

Output

Formatter

2ꢀ

CH1 A/D

Decimation

CVBS/Y/G

FSS

CVBS/Y

C

Composite

Processor

YCbCr

2ꢀ

CH2 A/D

CH3 A/D

CH4 A/D

Decimation

2ꢀ

Y/G

Decimation

Component

Processor

Pb/B

Pr/R

2ꢀ

Decimation

XTAL1

FID

XTAL2

RESETB

PWDN

VS/VBLK

HS/CS

GLCO

AVID

SCL

SDA

Timing

Processor

Host

Interface

DATACLK

Figure 2−2. Digital Video Processor Block Diagram

2.2.1 2y Decimation Filter

All input signals are oversampled by a factor of 2 (27 MHz). The A/D outputs first pass through

decimation filters that reduce the data rate to 1× the pixel rate. The decimation filter is a

half-band filter. Oversampling and decimation filtering can effectively increase the overall

signal-to-noise ratio by 3 dB.

2.2.2 Composite Processor

Figure 2−3 is a block diagram of the TVP5146 digital composite video processing circuit. This

circuit receives a digitized composite or S-video signal from the ADCs and performs Y/C

separation (bypassed for S-video input), chroma demodulation for PAL/NTSC and SECAM, and

YUV signal enhancements.

The 10-bit composite video is multiplied by the subcarrier signals in the quadrature demodulator

to generate color difference signals U and V. The U and V signals are then sent to low-pass

filters to achieve the desired bandwidth. An adaptive 5-line comb filter separates UV from Y

based on the unique property of color phase shifts from line to line. The chroma is remodulated

through a quadrature modulator and subtracted from line-delayed composite video to generate

luma. This form of Y/C separation is completely complementary, thus there is no loss of

information. However, in some applications, it is desirable to limit the U/V bandwidth to avoid

crosstalk. In that case, notch filters can be turned on. To accommodate some viewing

preferences, a peaking filter is also available in the luma path. Contrast, brightness, sharpness,

hue, and saturation controls are programmable through the host port.

11

SLES084C − August 2007

TVP5146

Y

Peaking

Delay

CVBS/Y

Line

Delay

–

Y

NTSC/PAL

Remodulation

SECAM Luma

Contrast

Brightness

Saturation

Adjust

Cb

Cr

Notch

Filter

SECAM

Color

Demodulation

CVBS

Notch

Filter

Color LPF

U

↓ 2

Burst

Accumulator

(U)

5-Line

Adaptive

Comb

Filter

Burst

Accumulator

(V)

Notch

U

Delay

Filter

Notch

Filter

V

Color LPF

↓ 2

V

NTSC/PAL

Demodulation

CVBS/C

Figure 2−3. Composite and S-Video Processor Block Diagram

12

TVP5146

SLES084C − August 2007

2.2.2.1 Color Low-Pass Filter

High filter bandwidth preserves sharp color transitions and produces crisp color boundaries.

However, for video sources that have asymmetrical U and V side bands, it is desirable to limit

the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable

to enable one of the three notch filters. Figure 2−4 through Figure 2−7 represent the frequency

responses of the wideband color low-pass filters.

10

0

10

0

Filter 2

–3 dB @ 767 kHz

PAL SQP –3 dB

@ 1.55 MHz

Filter 0

–3 dB @ 1.29 MHz

−10

−20

−30

−40

−50

−60

−70

−10

−20

−30

−40

−50

−60

−70

Filter 3

–3 dB @ 504 kHz

Filter 1

–3 dB

@ 936 kHz

ITU-R BT.601 –3 dB

@ 1.42 MHz

NTSC SQP –3 dB

@ 1.29 MHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

f – Frequency – MHz

Figure 2−5. Color Low-Pass Filter With Filter

Frequency Response, NTSC Square Pixel

Sampling

Figure 2−4. Color Low-Pass Filter Frequency

Response

10

Filter 2

–3 dB @ 844 kHz

–3 dB @ 922 kHz

0

Filter 0

–3 dB @ 1.55 MHz

Filter 0

–3 dB @ 1.41 MHz

−10

Filter 3

–3 dB

@ 605 kHz

Filter 3

–3 dB @ 554 kHz

−20

−30

−40

−50

−60

−70

−20

Filter 1

–3 dB

@ 1.03 MHz

Filter 1

–3 dB

−30

@ 1.13 MHz

−40

−50

−60

−70

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

f – Frequency – MHz

Figure 2−7. Color Low-Pass Filter With Filter

Characteristics, PAL Square Pixel Sampling

Figure 2−6. Color Low-Pass Filter With Filter

Characteristics, NTSC/PAL ITU-R BT.601

Sampling

13

SLES084C − August 2007

TVP5146

2.2.2.2 Y/C Separation

Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter.

The comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is

bypassed in the luma path, then chroma trap filters are used which are shown in Figure 2−8

through Figure 2−11. TI’s patented adaptive comb filter algorithm reduces artifacts such as

hanging dots at color boundaries. It detects and properly handles false colors in high frequency

luminance images, such as a multiburst pattern or circle pattern. Adaptive comb filtering is the

recommended mode of operation.

10

5

10

5

Notch 3 Filter

Notch 2 Filter

0

−5

−10

−15

−20

−25

−30

−35

−40

−10

−15

−20

−25

−30

−35

−40

Notch 1 Filter

Notch 2 Filter

Notch 3 Filter

Notch 1 Filter

No Notch Filter

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f – Frequency – MHz

Figure 2−8. Chroma Trap Filter Frequency

Response, NTSC Square Pixel Sampling

Figure 2−9. Chroma Trap Filter Frequency

Response, NTSC ITU-R BT.601 Sampling

10

5

10

Notch 3 Filter

5

0

−5

−10

−15

−20

−25

−30

−35

−40

−10

−15

−20

−25

−30

−35

−40

Notch 1 Filter

Notch 2 Filter

Notch 1 Filter

Notch 2 Filter

No Notch Filter

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f – Frequency – MHz

Figure 2−10. Chroma Trap Filter Frequency

Response, PAL ITU-R BT.601 Sampling

Figure 2−11. Chroma Trap Filter Frequency

Response, PAL Square Pixel Sampling

14

TVP5146

SLES084C − August 2007

2.2.3 Luminance Processing

The digitized composite video signal passes through either a luminance comb filter or a chroma

trap filter, either of which removes chrominance information from the composite signal to

generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit.

Figure 2−12 illustrates the basic functions of the luminance data path. In the case of S-video, the

luminance signal bypasses the comb filter or chroma trap filter and is fed directly to the circuit.

High-frequency components of the luminance signal are enhanced by a peaking filter

(sharpness). Figure 2−13, Figure 2−14, and Figure 2−15 show the characteristics of the peaking

filter at four different gain settings that are programmable via the host port.

Gain

Peak

Detector

Bandpass

Filter

Peaking

Filter

x

IN

Delay

+

OUT

Figure 2−12. Luminance Edge-Enhancer Peaking Block Diagram

7

6

7

Peak at

f = 2.64 MHz

f = 2.40 MHz

6

Gain = 2

5

4

Gain = 1

4

3

Gain = 0.5

2

1

0

Gain = 0

−1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f – Frequency – MHz

Figure 2−13. Peaking Filter Response, NTSC

Square Pixel Sampling

Figure 2−14. Peaking Filter Response,

NTSC/PAL ITU-R BT.601 Sampling

15

SLES084C − August 2007

TVP5146

7

6

Peak at

f = 2.89 MHz

Gain = 2

5

Gain = 1

4

3

Gain = 0.5

2

1

0

Gain = 0

−1

0

1

2

3

4

5

6

7

f – Frequency – MHz

Figure 2−15. Peaking Filter Response, PAL Square Pixel Sampling

2.2.3.1 Color Transient Improvement

Color transient improvement (CTI) enhances horizontal color transients by delay modulation for

both color difference signals. The operation must be performed only on YCbCr-formatted data.

The color difference signal transition points are maintained, but the edges are enhanced for

signals which have bandwidth-limited color components (for example, CVBS and S-video).

2.2.4 Component Video Processor

The component video processing block supports a user-selectable contrast, brightness, and

saturation adjustment in YCbCr output formats. For YCbCr output formats, gain and offset

values are applied to the luma data path in order to map the pixel values to the correct output

range (for 10-bit Y_min= 64 and Y_max= 940), and to provide a means of adjusting contrast and

brightness. For Y, digital contrast (gain) and brightness (offset) factors can vary from 0 to 255.

The contrast control adjusts the amplitude range of the Y output centered at the midpoint of the

output code range. The limit block limits the output to the ITU-R BT.601 range (Y_minto Y_max) or

an extended range, depending on a user setting.

Offset

x

+

Limit

Y

Gain

Figure 2−16. Y Component Gain, Offset, Limit

16

TVP5146

SLES084C − August 2007

For CbCr components, a saturation (gain) factor is applied to the CbCr inputs in order to map

them to the CbCr output code range and provide saturation control. Similarly, the limit block can

limit CbCr outputs to a valid range:

Cb,Cr

= 64 / Cb,Cr

= 960

min

max

x

Limit

CbCr

Gain

Figure 2−17. CbCr Component Gain, Offset, Limit

2.2.5 Color Space Conversion

The formulas for RGB to YCbCr conversion are given as:

Y = 0.299 × R + 0.587 × G + 0.114 × B

Cb = –0.172 × R – 0.339 × G + 0.511 × B + 512

Cr = 0.511 × R – 0.428 × G – 0.083 × B + 512

2.3 Clock Circuits

An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is

required to drive the PLL. This can be input to the TVP5146 decoder at the 1.8-V level on

terminal 74 (XTAL1), or a crystal of 14.31818-MHz fundamental resonant frequency can be

connected across terminals 74 and 75 (XTAL2). If a parallel resonant circuit is used as shown in

Figure 2−18, then the external capacitors must have the following relationship:

C

L1

= C = 2C – C

,

L2

L

STRAY

where C_STRAYis the terminal capacitance with respect to ground. Figure 2−18 shows the

reference clock configurations. The TVP5146 decoder generates the DATACLK signal used for

clocking data.

TVP5146

14.31818-MHz

Crystal

C

L1

L2

74

75

74

75

14.31818-MHz

Clock

XTAL1

XTAL2

Figure 2−18. Reference Clock Configurations

2.4 Real-Time Control (RTC)

Although the TVP5146 decoder is a line-locked system, the color burst information is used to

determine accurately the color subcarrier frequency and phase. This ensures proper operation

with nonstandard video signals that do not follow exactly the required frequency multiple

between color subcarrier frequency and video line frequency. The frequency control word of the

internal color subcarrier PLL and the subcarrier reset bit are transmitted via terminal 37 (GLCO)

for optional use in an end system (for example, by a video encoder). The frequency control word

is a 23-bit binary number.

17

SLES084C − August 2007

TVP5146

The instantaneous frequency of the color subcarrier can be calculated from the following

equation:

F_ctrl

2²³

F_PLL

+

F_sclk

where F_PLLis the frequency of the subcarrier PLL, F_ctrlis the 23-bit PLL frequency control word,

and F_sclkis two times the pixel frequency. Figure 2−19 shows the detailed timing diagram.

Valid

Invalid

Sample

Reserved

M

S

B

L

S

B

RTC

S

R

22

0

128 CLK

18 CLK

1 CLK

45 CLK

23-Bit Fsc PLL Increment

3 CLK

Start

Bit

NOTE: RTC Reset bit (R) is active low, Sequence bit (S) PAL:1 = (R-Y) line normal, 0 = (R-Y) line inverted, NTSC: 1 = no change

Figure 2−19. RTC Timing

2.5 Output Formatter

The output formatter sets how the data is formatted for output on the TVP5146 output buses.

Table 2−1 shows the available output modes.

Table 2−1. Output Format

TERMINAL

NAME

TERMINAL

NUMBER

20-Bit 4:2:2

YCbCr

10-Bit 4:2:2 YCbCr

Y_9

Y_8

Y_7

Y_6

Y_5

Y_4

Y_3

Y_2

Y_1

Y_0

C_9

C_8

C_7

C_6

C_5

C_4

C_3

C_2

C_1

C_0

43

44

45

46

47

50

51

52

53

54

57

58

59

60

63

64

65

66

69

70

Cb9, Y9, Cr9

Cb8, Y8, Cr8

Cb7, Y7, Cr7

Cb6, Y6, Cr6

Cb5, Y5, Cr5

Cb4, Y4, Cr4

Cb3, Y3, Cr3

Cb2, Y2, Cr2

Cb1, Y1, Cr1

Cb0, Y0, Cr0

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb6, Cr6

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

18

TVP5146

SLES084C − August 2007

Table 2−2. Summary of Line Frequencies, Data Rates, and Pixel/Line Counts

PIXEL

FREQUENCY

(MHz)

COLOR

SUBCARRIER

FREQUENCY (MHz)

PIXELS PER

LINE

ACTIVE PIXELS

PER LINE

LINES PER

FRAME

HORIZONTAL

LINE RATE (kHz)

STANDARDS

601 sampling

NTSC-J, M

NTSC-4.43

PAL-M

858

864

720

525

625

13.5

3.579545

4.43361875

3.57561149

4.43361875

3.58205625

15.73426

15.625

PAL-60

PAL-B, D, G, H, I

PAL-N

15.625

PAL-Nc

15.625

Dr = 4.406250

Db = 4.250000

SECAM

864

720

625

13.5

15.625

Square sampling

NTSC-J, M

NTSC-4.43

PAL-M

780

944

640

768

525

625

12.2727

14.75

3.579545

4.43361875

3.57561149

4.43361875

3.58205625

15.73426

15.625

PAL-60

PAL-B, D, G, H, I

PAL-N

14.75

15.625

PAL-Nc

14.75

15.625

Dr = 4.406250

Db = 4.250000

SECAM

944

768

625

14.75

15.625

2.5.1 Fast Switches for SCART

The TVP5146 decoder supports the SCART interface used in European audio/video end

equipment to carry composite video, S-video, and RGB video on the same cable. In the event

that composite video and RGB video are present simultaneously on the video terminals

assigned to a SCART interface, the TVP5146 decoder assumes they are pixel synchronous to

each other. The timing for both composite video and RGB video is obtained from the composite

source, and its derived clock is used to sample RGB video as well. The fast-switch input terminal

allows switching between these two input video sources on a pixel-by-pixel basis. The fast

switch is a hard switch; there is no alpha blending between both sources.

2.5.2 Separate Syncs

VS, HS, and VBLK are independently software programmable to a 1× pixel count. This allows

any possible alignment to the internal pixel count and line count. The default settings for 525-line

and 625-line video outputs are given as examples below. FID changes at the same transient

time when the trailing edge of vertical sync occurs. The polarity of FID is programmable by an

I²C interface.

19

SLES084C − August 2007

TVP5146

525-Line

525

1

2

3

4

5

6

7

8

9

10

11

21

22

First Field Video

HS

VS

VS Start

VS Stop

CS

FID

VBLK

VBLK Start

VBLK Stop

262 263 264 265 266 267 268 269 270 271 272 273

284 285

Second Field Video

HS

VS

VS Start

VS Stop

CS

FID

VBLK

VBLK Start

NOTE: Line numbering conforms to ITU-R BT.470

VBLK Stop

Figure 2−20. Vertical Synchronization Signals for 525-Line System

20

TVP5146

SLES084C − August 2007

625-Line

622 623 624 625

1

2

3

4

5

6

7

8

23

24

25

First Field Video

HS

VS

VS Start

VS Stop

CS

FID

VBLK

VBLK Start

VBLK Stop

310 311 312 313 314 315 316 317 318 319 320 321

336 337 338

Second Field Video

HS

VS

VS Start

VS Stop

CS

FID

VBLK

VBLK Start

NOTE: Line numbering conforms to ITU-R BT.470

VBLK Stop

Figure 2−21. Vertical Synchronization Signals for 625-Line System

21

SLES084C − August 2007

TVP5146

0

DATACLK

Y[9:0]

EAV EAV EAV EAV

SAV SAV SAV SAV

Cb

Y

Cr

Y

Horizontal Blanking

HS Start HS Stop

Cb0 Y0 Cr0 Y1

1

2

3

4

1

2

3

4

HS

A

C

B

D

AVID

AVID Stop

AVID Start

DATACLK = 2 Pixel Clock

Mode

NTSC 601

PAL 601

A

B

C

D

106 128

112 128

42

48

44

80

276

288

280

352

NTSC Sqp 108 128

PAL Sqp 144 128

NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference

Figure 2−22. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode

22

TVP5146

SLES084C − August 2007

0

DATACLK

Y[9:0]

Y

Horizontal Blanking

Y0 Y1 Y2 Y3

CbCr[9:0]

Cb Cr Cb Cr

Horizontal Blanking

HS Start HS Stop

Cb0 Cr0 Cb1 Cr1

HS

A

C

B

D

2

AVID

AVID Stop

NOTE: AVID rising edge occurs 2 clock cycles early.

AVID Start

DATACLK = 1 Pixel Clock

Mode

A

B

C

D

NTSC 601

PAL 601

53

56

54

72

64

19

22

20

38

136

142

138

174

NTSC Sqp

PAL Sqp

NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference

Figure 2−23. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode

23

SLES084C − August 2007

TVP5146

HS

VS

First Field

B/2

HS

VS

H/2 + B/2

Second Field

10-Bit (PCLK = 2 Pixel Clock)

20-Bit (PCLK = 1 Pixel Clock)

Mode

B/2

64

H/2

858

864

780

944

B/2

32

H/2

429

432

390

472

NTSC 601

PAL 601

NTSC Sqp

PAL Sqp

Figure 2−24. VSYNC Position With Respect to HSYNC

2.5.3 Embedded Syncs

Standards with embedded syncs insert the SAV and EAV codes into the data stream on the

rising and falling edges of AVID. These codes contain the V and F bits which also define vertical

timing. Table 2−3 gives the format of the SAV and EAV codes.

H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to

the line and field counter varies depending on the standard.

The P bits are protection bits:

P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H

Table 2−3. EAV and SAV Sequence

D9 (MSB)

D8

1

D7

1

D6

1

D5

1

D4

1

D3

1

D2

1

D1

1

D0

1

Preamble

Status word

1

0

1

0

F

V

H

P3

P2

P1

P0

0

2.6 I²C Host Interface

Communication with the TVP5146 decoder is via an I²C host interface. The I²C standard

consists of two signals, the serial input/output data (SDA) line and the serial input clock line

(SCL), which carry information between the devices connected to the bus. A third signal (I²CA)

is used for slave address selection. Although an I²C system can be multimastered, the TVP5146

decoder functions as a slave device only.

24

TVP5146

SLES084C − August 2007

Because SDA and SCL are kept open-drain at a logic-high output level or when the bus is not

driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on

the board. The slave-address select signal, terminal 37 (I²CA), enables the use of two TVP5146

decoders tied to the same I²C bus by controlling the least significant bit of the I²C device

address.

2

Table 2−4. I C Host Interface Terminal Description

SIGNAL

TYPE

DESCRIPTION

Slave address selection

Input clock line

2

I CA

SCL

SDA

I

I/O

Input/output data line

2.6.1 Reset and I²C Bus Address Selection

The TVP5146 decoder can respond to two possible chip addresses. The address selection is

made at reset by an externally supplied level on the I²CA terminal. The TVP5146 decoder

samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures

the I²C bus address bit A0. The I²CA terminal has an internal pulldown resistor to pull the

terminal low to set a zero.

2

Table 2−5. I C Address Selection

2

A6

1

A5

0

A4

1

A3

1

A2

1

A1

0

A0 (I CA)

R/W

1/0

HEX

B9/B8

BB/BA

0 (default)

†

1

0

1

0

1

1/0

†

2

If terminal 37 is strapped to DVDD via a 2.2-kΩ resistor, I C device address A0 is set to 1.

2.6.2 I²C Operation

S

1011 1000

ACK

Subaddress

ACK

Send data

ACK

P

Data transfers occur using the following illustrated formats.

Read from I²C control registers

S

1011 1000

ACK

Subaddress

ACK

S

1011 1001

ACK

Receive data

NAK

P

2

S = I C bus start condition

2

P = I C bus stop condition

ACK = Acknowledge generated by the slave

NAK = Acknowledge generated by the master, for multiple-byte read master with ACK for each byte except

last byte

Subaddrress = Subaddress byte

Data = Data byte, if more than one byte of data is transmitted (read and write), the subaddress pointer is

automatically incremented.

2

I C bus address = Example showing that I CA is in default mode. Write (B8h), read (B9h)

2.6.3 VBUS Access

The TVP5146 decoder has additional internal registers accessible through an indirect access to

an internal 24-bit address wide VBUS. Figure 2−25 shows the VBUS registers access.

25

SLES084C − August 2007

TVP5146

2

I C Registers

VBUS Registers

00h

00 0000h

HOST

Processor

2

80 051Ch

80 0520h

80 052Ch

80 0600h

I C

CC

WSS

VITC

E0h

VBUS

Data

Line

Mode

E1h

E8h

VBUS[23:0]

80 0700h

90 1904h

VPS

VBUS

Address

FIFO

EAh

FFh

FF FFFFh

VBUS Write

Single Byte

S

B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK

P

S

B8 ACK E0 ACK Send Data ACK

P

Multiple Bytes

S

B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK

S

B8 ACK E1 ACK Send Data ACK • • • Send Data ACK

P

VBUS Read

Single Byte

S

B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK

P

S

B8 ACK E0 ACK

S

B9 ACK Read Data NAK P

Multiple Bytes

S

B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK

P

S

B8 ACK E1 ACK

S

B9 ACK Read Data ACK • • • Read Data NAK

P

2

NOTE: Examples use default I C address.

ACK = Acknowledge generated by the slave

NAK = No Acknowledge generated by the master

Figure 2−25. VBUS Access

26

TVP5146

SLES084C − August 2007

2.6.4 I²C Timing Requirements

The TVP5146 decoder requires delays in the I²C accesses to accommodate the internal

processor timing. In accordance with I²C specifications, the TVP5146 decoder holds the I²C

clock line (SCL) low to indicate the wait period to the I²C master. If the I²C master is not

designed to check for the I²C clock line held-low condition, then the maximum delays must

always be inserted where required. These delays are of variable length; maximum delays are

indicated in the following diagram:

Normal register

S

1011 1000

ACK

Subaddress

ACK

Send data

ACK

Wait 64 µs

P

2.7 VBI Data Processor

The TVP5146 VBI data processor (VDP) slices various data services like teletext (WST,

NABTS), closed caption (CC), wide screen signaling (WSS), program delivery control (PDC),

vertical interval time code (VITC), video program system (VPS), copy generation management

system (CGMS) data, and electronic program guide (Gemstar) 1x/2x. Table 2−6 shows the

supported VBI system.

These services are acquired by programming the VDP to enable the reception of one or more

VBI data standard(s) in the VBI. The VDP can be programmed on a line-per-line basis to enable

simultaneous reception of different VBI formats, one per line. The results are stored in a FIFO

and/or registers. Because of its high data bandwidth, the teletext results are stored in FIFO only.

The TVP5146 decoder provides fully decoded V-CHIP data to the dedicated registers at

subaddresses 800540h–800543h (see Sections 2.12.4 through 2.12.7).

Table 2−6. Supported VBI Systems

VBI SYSTEM

Teletext WST A

STANDARD

SECAM

PAL

LINE NUMBER

6–23 (Fields 1 and 2)

6–22 (Fields 1 and 2)

10–21 (Fields 1 and 2)

22 (Fields 1 and 2)

21 (Fields 1 and 2)

23 (Fields 1 and 2)

20 (Fields 1 and 2)

6–22

NUMBER OF BYTES

38

Teletext WST B

Teletext NABTS C

Teletext NABTS D

Closed caption

WSS

43

NTSC

NTSC-J

PAL

34

35

2

NTSC

PAL

2

14 bits

WSS-CGMS

VITC

NTSC

PAL

20 bits

9

VITC

NTSC

PAL

10–20

9

VPS (PDC)

V-CHIP (decoded)

Gemstar 1×

Gemstar 2×

User

16

13

NTSC

Any

21 (Field 2)

2

5 with frame byte

Programmable

27

SLES084C − August 2007

TVP5146

2.7.1 VBI FIFO and Ancillary Data in Video Stream

Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI

data is output on the Y[9:2] terminals during the horizontal blanking period. Table 2−7 shows the

header format and sequence of the ancillary data inserted into the video stream. This format is

also used to store any VBI data into the FIFO. The size of the FIFO is 512 bytes. Therefore, the

FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard.

Table 2−7. Ancillary Data Format and Sequence

BYTE

NO.

D7

(MSB)

D6

D5

D4

D3

D2

D1

D0

(LSB)

DESCRIPTION

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Ancillary data preamble

1

NEP

EP

0

1

0

DID2

F2

N2

DID1

F1

N1

DID0

F0

N0

Data ID (DID)

F5

N5

F4

N4

F3

N3

Secondary data ID (SDID)

Number of 32-bit data (NN)

Internal data ID0 (IDID0)

Video line # [7:0]

0

Data

error

Match

#1

Match

#2

Video line # [9:8] Internal data ID1 (IDID1)

st

8

9

1. Data

Data byte

:

1

word

2. Data

3. Data

4. Data

:

10

11

:

th

m. Data

CS[7:0]

Data byte

Check sum

N

4N+7

0

Fill byte

EP:

Even parity for D0–D5

NEP: Negated even parity

DID:

91h: Sliced data of VBI lines of first field

53h: Sliced data of line 24 to end of first field

55h: Sliced data of VBI lines of second field

97h: Sliced data of line 24 to end of second field

SDID:

This field holds the data format taken from the line mode register bits [2:0] of the

corresponding line.

NN:

Number of Dwords beginning with byte 8 through 4N+7. Note this value is the number

of Dwords where

each Dword is 4 bytes.

IDID0:

IDID1:

Transaction video line number [7:0]

Bit 0/1 = Transaction video line number [9:8]

Bit 2 = Match 2 flag

Bit 3 = Match 1 flag

Bit 4 = 1 if an error was detected in the EDC block. 0 if no error was detected.

CS:

Sum of D0–D7 of first data through last data byte.

Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes,

byte 8 is the sync pattern

byte. Byte 9 is the first data byte.

28

TVP5146

SLES084C − August 2007

2.7.2 VBI Raw Data Output

The TVP5146 decoder can output raw A/D video data at twice the sampling rate for external VBI

slicing. This is transmitted as an ancillary data block, although somewhat differently from the

way the sliced VBI data is transmitted in the FIFO format as described in Section 2.7.1. The

samples are transmitted during the active portion of the line. VBI raw data uses ITU-R BT.656

format having only luma data. The chroma samples are replaced by luma samples. The

TVP5146 decoder inserts a four-byte preamble 000h 3FFh 3FFh 180h before data start. There

are no checksum bytes and fill bytes in this mode.

Table 2−8. VBI Raw Data Output Format

BYTE

NO.

D9

(MSB)

D8

D7

D6

D5

D4

D3

D2

D1

D0

(LSB)

DESCRIPTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VBI raw data preamble

2

3

4

1. Data

2. Data

:

5

2× pixel rate luma data

:

(i.e., NTSC 601: n = 1707)

n–1

n

n–5. Data

n–4. Data

2.8 Reset and Initialization

Reset is initiated at power up or any time terminal 34 (RESETB) is brought low. Table 2−9

describes the status of the TVP5146 terminals during and immediately after reset.

Table 2−9. Reset Sequence

SIGNAL NAME

DURING RESET

Input

RESET COMPLETED

Y[9:0], C[9:0], DATACLK

High-impedance

RESETB, PWDN, SDA, SCL, FSS,

AVID, GLCO, HS, VS, FID

Input

INTREQ

Input

Output

DATACLK

Output

High-impedance

TI recommends the following power-up sequence.

Power (1.8 V)

100 ms

Power (3.3 V)

3 ms (min)

Normal Operation

RESETB

(Terminal 34)

Reset

1 ms (min)

SDA

(Terminal 29)

2

Invalid I C Cycle

Valid

NOTE: All times shown are minimum values. Maximum time between 1.8 V and 3.3 V should be no longer than 1 second.

Figure 2−26. Reset Timing

29

SLES084C − August 2007

TVP5146

The TVP5146 requires that terminal 69 (C_1/GPIO) be held LOW. If using the 20-/16-bit mode

or using this terminal as GPIO, then this terminal must be pulled low through a 2.2-kΩ pulldown

resistor (see Figure 5−1). If unused, this terminal can be shorted to ground. (Note: If using the

20-/16-bit mode and only using the 16 MSBs, it is possible to short terminal 69 to GND, but the

current for IOVDD will increase by 2 or 3 mA.)

After reset, the user must write the following I²C commands to the TVP5146:

2

STEP

I C SUBADDRESS

I C DATA

1

2

0xE8

0xE9

0xEA

0xE0

0xE8

0xE9

0xEA

0xE0

0x03

0x02

0x00

0x80

0x01

0x60

0x00

0xB0

0x01

0x00

0x01

0x00

3

4

5

6

7

8

9

10

11

Afterward, the user programs the device as usual.

2.9 Adjusting External Syncs

The proper sequence to program the following external syncs is:

•

To set NTSC, PAL-M, NTSC 443, PAL60 (525-line modes):

−

Set the video standard to NTSC (register 02h)

Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h)

To set PAL, PAL-N, SECAM (625-line modes):

−

Set the video standard to PAL (register 02h)

Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h)

For autoswitch, set the video standard to autoswitch (register 02h)

2.10 Internal Control Registers

The TVP5146 decoder is initialized and controlled by a set of internal registers that define the

operating parameters of the entire decoder. Communication between the external controller and

the TVP5146 decoder is through a standard I²C host port interface, as described earlier.

Table 2−10 shows the summary of these registers. Detailed programming information for each

register is described in the following sections. Additional registers are accessible through an

indirect procedure involving access to an internal 24-bit address wide VBUS. Table 2−11 shows

the summary of the VBUS registers.

NOTE: Do not write to reserved registers. Reserved bits in any defined register must be written

with 0s, unless otherwise noted.

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TVP5146

SLES084C − August 2007

Table 2−10. Register Summary

2

REGISTER NAME

I C SUBADDRESS

00h

DEFAULT

00h

R/W

Input select

AFE gain control

01h

0Fh

00h

Video standard

02h

Operation mode

03h

00h

Autoswitch mask

04h

23h

Color killer

05h

10h

Luminance processing control 1

Luminance processing control 2

Luminance processing control 3

Luminance brightness

Luminance contrast

Chrominance saturation

Chroma hue

06h

00h

07h

00h

08h

02h

09h

80h

0Ah

80h

0Bh

80h

0Ch

00h

Chrominance processing control 1

Chrominance processing control 2

Reserved

0Dh

00h

0Eh

0Fh

Component Pr saturation

Component Y contrast

Component Pb saturation

Reserved

10h

80h

R/W

11h

12h

13h

Component Y brightness

Reserved

14h

80h

R/W

15h

AVID start pixel

16h–17h

18h–19h

1Ah–1Bh

1Ch–1Dh

1Eh–1Fh

20h–21h

22h–23h

24h–25h

055h

325h

000h

040h

004h

007h

001h

015h

R/W

AVID stop pixel

HSYNC start pixel

HSYNC stop pixel

VSYNC start line

VSYNC stop line

VBLK start line

VBLK stop line

NOTE: R = Read only

W = Write only

R/W = Read and write

Reserved register addresses must not be written to.

31

SLES084C − August 2007

TVP5146

Table 2−10. Registers Summary (Continued)

2

REGISTER NAME

I C SUBADDRESS

26h–27h

28h

DEFAULT

R/W

Reserved

Fast-switch control

Reserved

CCh

00h

29h

Fast-switch SCART delay

Reserved

2Ah

2Bh

SCART delay

2Ch

00h

R/W

CTI delay

2Dh

CTI control

2Eh

Reserved

2Fh–30h

31h

RTC

05h

00h

40h

00h

FFh

00h

R/W

R

Sync control

32h

Output formatter 1

Output formatter 2

Output formatter 3

Output formatter 4

Output formatter 5

Output formatter 6

Clear lost lock detect

Status 1

33h

34h

35h

36h

37h

38h

39h

3Ah

Status 2

3Bh

R

AGC gain status

Reserved

3Ch–3Dh

3Eh

R

Video standard status

GPIO input 1

3Fh

R

40h

R

GPIO input 2

41h

R

Vertical line count

Reserved

42h–43h

44h–45h

46h

R

AFE coarse gain for CH1

AFE coarse gain for CH2

AFE coarse gain for CH3

AFE coarse gain for CH4

AFE fine gain for Pb_B

AFE fine gain for Y_G_Chroma

AFE fine gain for Pr_R

AFE fine gain for CVBS_Luma

Reserved

20h

R/W

47h

48h

20h

49h

20h

4Ah–4Bh

4Ch–4Dh

4Eh–4Fh

50h–51h

52h–6Fh

70h

900h

ROM version

R

Reserved

71h–73h

74h

AGC white peak processing

Reserved

00h

R/W

75h–77h

NOTE: R = Read only

W = Write only

R/W = Read and write

Reserved register addresses must not be written to.

32

TVP5146

SLES084C − August 2007

Table 2−10. Registers Summary (Continued)

2

REGISTER NAME

I C SUBADDRESS

78h

DEFAULT

R/W

AGC increment speed

AGC increment delay

Reserved

05h

1Eh

79h

7Ah–7Fh

80h

Chip ID MSB

R

Chip ID LSB

81h

Reserved

82h–B0h

B1h

VDP TTX filter 1 mask 1

VDP TTX filter 1 mask 2

VDP TTX filter 1 mask 3

VDP TTX filter 1 mask 4

VDP TTX filter 1 mask 5

VDP TTX filter 2 mask 1

VDP TTX filter 2 mask 2

VDP TTX filter 2 mask 3

VDP TTX filter 2 mask 4

VDP TTX filter 2 mask 5

VDP TTX filter control

VDP FIFO word count

VDP FIFO interrupt threshold

Reserved

00h

R/W

R

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

BCh

BDh

80h

R/W

BEh

VDP FIFO reset

BFh

00h

R/W

VDP FIFO output control

VDP line number interrupt

VDP pixel alignment

Reserved

C0h

C1h

00h

C2h–C3h

C4h–D5h

D6h

01Eh

VDP line start

06h

1Bh

FFh

00h

FFh

R/W

VDP line stop

D7h

VDP global line mode

VDP full field enable

VDP full field mode

Reserved

D8h

D9h

DAh

DBh–DFh

E0h

VBUS data access with no VBUS address

increment

00h

R/W

VBUS data access with VBUS address increment

FIFO read data

E1h

E2h

R/W

R

Reserved

E3h–E7h

E8h–E9h

EBh–EFh

F0h

VBUS address access

Reserved

00 0000h

R/W

Interrupt raw status 0

Interrupt raw status 1

F1h

NOTE: R = Read only

W = Write only

R/W = Read and write

Reserved register addresses must not be written to.

33

SLES084C − August 2007

TVP5146

Table 2−10. Registers Summary (Continued)

2

REGISTER NAME

I C SUBADDRESS

DEFAULT

R/W

Interrupt status 0

Interrupt status 1

Interrupt mask 0

Interrupt mask 1

Interrupt clear 0

Interrupt clear 1

Reserved

F2h

F3h

F4h

00h

F5h

F6h

F7h

F8h–FFh

NOTE: R = Read only

W = Write only

R/W = Read and write

Reserved register addresses must not be written to.

Table 2−11. VBUS Register Summary

2

REGISTER NAME

I C SUBADDRESS

00 0000h–80 051Bh

80 051Ch–80 051Fh

80 0520h–80 0526h

80 0527h–80 052Bh

80 052Ch–80 0534h

80 0535h–80 053Fh

80 0540h–80 0543h

80 0544h–80 05FFh

80 0600h–80 0611h

80 0612h–80 06FFh

80 0700h–80 070Ch

80 070Dh–90 1903h

90 1904h

DEFAULT

R/W

Reserved

VDP closed caption data

VDP WSS data

Reserved

R

VDP VITC data

Reserved

R

VDP V-Chip data

Reserved

VDP general line mode and line address

Reserved

00h, FFh

R/W

R

VDP VPS/Gemstar data

Reserved

VDP FIFO read

Reserved

R

90 1905h–B0 005Fh

B0 0060h

Interrupt configuration

Reserved

00h

R/W

B0 0061h–FF FFFFh

NOTE: Writing any value to a reserved register may cause erroneous operation of the TVP5146 decoder.

It is recommended not to access any data to/from reserved registers.

34

TVP5146

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2.11 Register Definitions

2.11.1 Input Select Register

Subaddress

00h

Default

00h

7

6

5

4

3

2

1

0

Input select [7:0]

Table 2−12. Analog Channel and Video Mode Selection

INPUT SELECT [7:0]

MODE

INPUT(S) SELECTED

7

0

1

6

0

1

0

1

5

0

4

0

1

0

1

0

1

0

1

3

0

1

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

HEX

00

CVBS

VI_1_A (default)

VI_1_B

01

VI_1_C

02

VI_2_A

04

VI_2_B

05

VI_2_C

06

VI_3_A

08

VI_3_B

09

VI_3_C

0A

0C

44

VI_4_A

S-video VI_2_A(Y), VI_1_A(C)

VI_2_B(Y), VI_1_B(C)

VI_2_C(Y), VI_1_C(C)

VI_2_A(Y), VI_3_A(C)

VI_2_B(Y), VI_3_B(C)

VI_2_C(Y), VI_3_C(C)

VI_4_A(Y), VI_1_A(C)

VI_4_A(Y), VI_1_B(C)

VI_4_A(Y), VI_1_C(C)

VI_4_A(Y), VI_3_A(C)

VI_4_A(Y), VI_3_B(C)

VI_4_A(Y), VI_3_C(C)

45

46

54

55

56

4C

4D

4E

5C

5D

5E

84

RGB

VI_1_A(B), VI_2_A(G), VI_3_A(R)

VI_1_B(B), VI_2_B(G), VI_3_B(R)

VI_1_C(B), VI_2_C(G), VI_3_C(R)

VI_1_A(Pb), VI_2_A(Y), VI_3_A(Pr)

VI_1_B(Pb), VI_2_B(Y), VI_3_B(Pr)

VI_1_C(Pb), VI_2_C(Y), VI_3_C(Pr)

85

86

YPbPr

94

95

96

SCART VI_1_A(B), VI_2_A(G), VI_3_A(R), VI_4_A(CVBS)

VI_1_B(B), VI_2_B(G), VI_3_B(R), VI_4_A(CVBS)

VI_1_C(B), VI_2_C(G), VI_3_C(R), VI_4_A(CVBS)

VI_1_A(Pb), VI_2_A(Y), VI_3_A(Pr), VI_4_A(CVBS)

VI_1_B(Pb), VI_2_B(Y), VI_3_B(Pr), VI_4_A(CVBS)

VI_1_C(Pb), VI_2_C(Y), VI_3_C(Pr), VI_4_A(CVBS)

CC

CD

CE

DC

DD

DE

Ten input terminals can be configured to support composite, S-video, and component

YPbPr/RGB or SCART as listed in Table 2−12. Users must follow this table properly for S-video

and component applications because only the terminal configurations listed in Table 2−12 are

supported.

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SLES084C − August 2007

TVP5146

2.11.2 AFE Gain Control Register

Subaddress

01h

Default

0Fh

7

6

5

4

3

2

1

0

Reserved

1

AGC chroma

AGC luma

Bit 3: 1 must be written to this bit.

Bit 2: 1 must be written to this bit.

AGC chroma: Controls automatic gain in the chroma/B/R/PbPr channel:

0 = Manual (if AGC luma is set to manual, AGC chroma is forced to be in manual)

1 = Enabled auto gain, applies a gain value acquired from the sync channel for S-video and component

mode. When AGC luma is set, this state is valid. (default)

AGC luma: Controls automatic gain in the embedded sync channel of CVBS, S-video,

component video:

0 = Manual gain, AFE coarse and fine gain frozen to the previous gain value set by a AGC when this bit is

set

to 0.

1 = Enabled auto gain applies only to the embedded sync channel (default)

These settings only affect the analog front-end (AFE). The brightness and contrast of

component, CVBS are not affected by these settings.

2.11.3 Video Standard Register

Subaddress

02h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Video standard [2:0]

Video standard [2:0]:

CVBS and S-Video

Component Video

000 = Autoswitch mode (default) Autoswitch mode (default)

001 = (M, J) NTSC

010 = (B, D, G, H, I, N) PAL

011 = (M) PAL

Component 525

Component 625

Reserved

100 = (Combination-N) PAL

101 = NTSC 4.43

110 = SECAM

Reserved

111 = PAL 60

Reserved

NOTE: PAL60 is not included in autoswitch mode.

With the autoswitch code running, the user can force the decoder to operate in a particular video

standard mode by writing the appropriate value into this register. Changing these bits causes the

register settings to be reinitialized.

NOTE: Sampling rate (either square pixel or ITU-R BT.601) can be set by bit 7 (sampling rate) in the output

2

formatter 1 register at I C subaddress 33h (see Section 2.11.35).

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TVP5146

SLES084C − August 2007

2.11.4 Operation Mode Register

Subaddress

03h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Power save

Power save:

0 = Normal operation (default)

1 = Power-save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I C

interface is active and all current operating settings are preserved.

2

2.11.5 Autoswitch Mask Register

Subaddress

04h

Default

23h

7

6

5

4

3

2

1

0

Reserved

SECAM

NTSC 4.43

(Nc) PAL

(M) PAL

PAL

(M, J) NTSC

Autoswitch mode mask: Limits the video formats between which autoswitch is possible.

SECAM:

0 = Autoswitch does not include SECAM

1 = Autoswitch includes SECAM (default)

NTSC 4.43:

0 = Autoswitch does not include NTSC 4.43 (default)

1 = Autoswitch includes NTSC 4.43

(Nc) PAL:

0 = Autoswitch does not include (Nc) PAL (default)

1 = Autoswitch includes (Nc) PAL

(M) PAL:

0 = Autoswitch does not include (M) PAL (default)

1 = Autoswitch includes (M) PAL

PAL:

0 = Reserved

1 = Autoswitch includes (B, D, G, H, I, N) PAL (default)

(M, J ) NTSC:

0 = Reserved

1 = Autoswitch includes (M, J) NTSC (default)

NOTE: Bits 1 and 0 must always be 1.

37

SLES084C − August 2007

TVP5146

2.11.6 Color Killer Register

Subaddress

05h

Default

10h

7

6

5

4

3

2

1

0

Reserved

Automatic color killer

Color killer threshold [4:0]

Automatic color killer:

00 = Automatic mode (default)

01 = Reserved

10 = Color killer enabled, the C terminals are forced to a zero color state.

11 = Color killer disabled

Color killer threshold [4:0]:

1 1111 = 31 (maximum)

1 0000 = 16 (default)

0 0000 = 0 (minimum)

2.11.7 Luminance Processing Control 1 Register

Subaddress

06h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Pedestal not present

Reserved

VBI raw

Luminance signal delay [3:0]

Pedestal not present:

0 = 7.5 IRE pedestal is present on the analog video input signal (default)

1 = Pedestal is not present on the analog video input signal

VBI raw:

0 = Disabled (default)

1 = Enabled

During the duration of the vertical blanking as defined by the VBLK start and stop line registers

at subaddresses 22h through 25h (see Sections 2.11.26 and 2.11.27), the chroma samples are

replaced by luma samples. This feature can be used to support VBI processing performed by an

external device during the VBI. In order to use this bit, the output format must be 10-bit ITU-R

BT.656 mode.

Luminance signal delay [3:0]: Luminance signal delays with respect to the chroma signal in 1×

pixel clock increments.

0111 = Reserved

0110 = 6-pixel delay

0001 = 1-pixel delay

0000 = 0 delay (default)

1111 = –1-pixel delay

1000 = –8-pixel delay

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TVP5146

SLES084C − August 2007

2.11.8 Luminance Processing Control 2 Register

Subaddress

07h

Default

00h

7

6

5

4

3

2

1

0

Luma filter select [1:0]

Reserved

Peaking gain (sharpness) [1:0]

Reserved

Luma filter selected [1:0]:

00 = Luminance adaptive comb enabled (default on CVBS)

01 = Luminance adaptive comb disabled (trap filter selected)

10 = Luma comb/trap filter bypassed (default on S-video, component mode, and SECAM)

11 = Reserved

Peaking gain (sharpness) [1:0]:

00 = 0 (default)

01 = 0.5

10 = 1

11 = 2

2.11.9 Luminance Processing Control 3 Register

Subaddress

08h

Default

02h

7

6

5

4

3

2

1

0

Reserved

Trap filter select [1:0]

Trap filter select [1:0] selects one of the four trap filters to produce the luminance signal by

removing the chrominance signal from the composite video signal. The stopband of the chroma

trap filter is centered at the chroma subcarrier frequency with the stopband bandwidth controlled

by the two control bits.

Trap filter stopband bandwidth (MHz):

Filter select [1:0] NTSC ITU-R BT.601

pixel

NTSC Square pixel PAL ITU-R BT.601 PAL

Square

1.3252

0.9507

0.8066

0.5474

00 =

1.2129

0.8701

0.7183

0.5010

1.1026

0.7910

0.6712

0.4554

1.2129

0.8701

0.7383

0.5010

01 =

10 = (default)

11 =

2.11.10 Luminance Brightness Register

Subaddress

09h

Default

80h

7

6

5

4

3

2

1

0

Brightness [7:0]

Brightness [7:0]: This register works for CVBS and S-video luminance.

1111 1111 = 255 (bright)

1000 0000 = 128 (default)

0000 0000 = 0 (dark)

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SLES084C − August 2007

TVP5146

2.11.11 Luminance Contrast Register

Subaddress

0Ah

Default

80h

7

6

5

4

3

2

1

0

Contrast [7:0]

Contrast [7:0]: This register works for CVBS and S-video luminance.

1111 1111 = 255 (maximum contrast)

1000 0000 = 128 (default)

0000 0000 = 0 (minimum contrast)

2.11.12 Chrominance Saturation Register

Subaddress

0Bh

Default

80h

7

6

5

4

3

2

1

0

Saturation [7:0]

Saturation [7:0]: This register works for CVBS and S-video chrominance.

1111 1111 = 255 (maximum)

1000 0000 = 128 (default)

0000 0000 = 0 (no color)

2.11.13 Chroma Hue Register

Subaddress

0Ch

Default

00h

7

6

5

4

3

2

1

0

Hue [7:0]

Hue [7:0] (does not apply to a component video): This register works for CVBS and S-video

chrominance.

0111 1111 = +180 degrees

0000 0000 = 0 degrees (default)

1000 0000 = –180 degrees

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TVP5146

SLES084C − August 2007

2.11.14 Chrominance Processing Control 1 Register

Subaddress

0Dh

Default

00h

7

6

5

4

3

2

1

0

Chrominance adaptive

comb enable

Reserved

Color PLL reset

Reserved

Automatic color gain control [1:0]

Color PLL reset:

0 = Color subcarrier PLL not reset (default)

1 = Color subcarrier PLL reset

Chrominance adaptive comb enable: This bit is effective on composite video only.

0 = Enabled (default)

1 = Disabled

Automatic color gain control (ACGC) [1:0]:

00 = ACGC enabled (default)

01 = Reserved

10 = ACGC disabled, ACGC set to the nominal value

11 = ACGC frozen to the previous set value

2.11.15 Chrominance Processing Control 2 Register

Subaddress

0Eh

Default

0Eh

7

6

5

4

3

2

1

0

Reserved

PAL compensation

WCF

Chrominance filter select [1:0]

PAL compensation:

0 = Disabled

1 = Enabled (default)

WCF: Wideband chroma LPF filter

0 = Disabled

1 = Enabled (default)

Chrominance filter select [1:0]:

00 = Disabled

01 = Notch 1

10 = Notch 2 (default)

11 = Notch 3

See Figure 2−8 through Figure 2−11 for characteristics.

2.11.16 Component Pr Saturation Register

Subaddress

10h

Default

80h

7

6

5

4

3

2

1

0

Pr saturation [7:0]

Pr saturation [7:0]: This register works only with YPbPr component video. For RGB video, user

must use the AFE gain registers.

1111 1111 = 255 (maximum)

1000 0000 = 128 (default)

0000 0000 = 0 (minimum)

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TVP5146

2.11.17 Component Y Contrast Register

Subaddress

11h

Default

80h

7

6

5

4

3

2

1

0

Y contrast [7:0]

Y contrast [7:0]: This register works only with YPbPr component video. For RGB video, user

must use the AFE gain registers.

1111 1111 = 255 (maximum)

1000 0000 = 128 (default)

0000 0000 = 0 (minimum)

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2.11.18 Component Pb Saturation Register

Subaddress

12h

Default

80h

7

6

5

4

3

2

1

0

Pb saturation [7:0]

Pb saturation [7:0]: This register works only with YPbPr component video. For RGB video, user

must use the AFE gain registers.

1111 1111 = 255 (maximum)

1000 0000 =128 (default)

0000 0000 = 0 (minimum)

2.11.19 Component Y Brightness Register

Subaddress

14h

Default

80h

7

6

5

4

3

2

1

0

Y brightness [7:0]

Y brightness [7:0]: This register works only with YPbPr component video.

1111 1111 = 255 (maximum)

1000 0000 = 128 (default)

0000 0000 = 0 (minimum)

2.11.20 AVID Start Pixel Register

Subaddress

16h–17h

Default

055h

Subaddress

16h

7

6

5

4

3

2

1

0

AVID start [7:0]

AVID active

17h

Reserved

AVID start [9:8]

AVID active:

0 = AVID out active in VBLK (default)

1 = AVID out inactive in VBLK

AVID start [9:0]: AVID start pixel number, this is a absolute pixel location from HSYNC start pixel

0.

NTSC 601

85 (55h)

NTSC Sqp

86 (56h)

PAL 601

88 (58h)

PAL Sqp

103 (67h)

default

The TVP5146 decoder updates the AVID start only when the AVID start MSB byte is written to. If

the user changes these registers, then the TVP5146 decoder retains values in different modes

until this decoder resets. The AVID start pixel register also controls the position of the SAV code.

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TVP5146

2.11.21 AVID Stop Pixel Register

Subaddress

18h–19h

Default

325h

Subaddress

18h

7

6

5

4

3

2

1

0

AVID stop [7:0]

19h

Reserved

AVID stop [9:8]

AVID stop [9:0]: AVID stop pixel number. The number of pixels of active video must be an even

number. This is an absolute pixel location from HSYNC start pixel 0.

NTSC 601

805 (325h)

NTSC Sqp

726 (2D6h)

PAL 601

808 (328h)

PAL Sqp

696 (2B8h)

default

The TVP5146 decoder updates the AVID stop only when the AVID stop MSB byte is written to. If

the user changes these registers, then the TVP5146 decoder retains values in different modes

until this decoder resets. The AVID start pixel register also controls the position of the EAV code.

2.11.22 HSYNC Start Pixel Register

Subaddress

1Ah–1Bh

Default

000h

Default (000h)

Subaddress

7

6

5

4

3

2

1

0

1Ah

1Bh

HSYNC start [7:0]

Reserved

HSYNC start [9:8]

HSYNC start pixel [9:0]: This is an absolute pixel location from HSYNC start pixel 0.

The TVP5146 decoder updates the HSYNC start only when the HSYNC start MSB byte is

written to. If the user changes these registers, then the TVP5146 decoder retains values in

different modes until this decoder resets.

2.11.23 HSYNC Stop Pixel Register

Subaddress

1Ch–1Dh

Default

040h

Subaddress

1Ch

7

6

5

4

3

2

1

0

HSYNC stop [7:0]

1Dh

Reserved

HSYNC stop [9:8]

HSYNC stop [9:0]: This is an absolute pixel location from HSYNC start pixel 0.

The TVP5146 decoder updates the HSYNC stop only when the HSYNC Stop MSB byte is

written to. If the user changes these registers, then the TVP5146 decoder retains values in

different modes until this decoder resets.

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2.11.24 VSYNC Start Line Register

Subaddress

1Eh–1Fh

Default

004h

Subaddress

1Eh

7

6

5

4

3

2

1

0

VSYNC start [7:0]

1Fh

Reserved

VSYNC start [9:8]

VSYNC start [9:0]: This is an absolute line number. The TVP5146 decoder updates the VSYNC

start only when the VSYNC start MSB byte is written to. If the user changes these registers, then

the TVP5146 decoder retains values in different modes until this decoder resets.

NTSC: default 004h,

PAL: default 001h

2.11.25 VSYNC Stop Line Register

Subaddress

20h–21h

Default

007h

Subaddress

20h

7

6

5

4

3

2

1

0

VSYNC stop [7:0]

21h

Reserved

VSYNC stop [9:8]

VSYNC stop [9:0]: This is an absolute line number. The TVP5146 decoder updates the VSYNC

stop only when the VSYNC stop MSB byte is written to. If the user changes these registers, the

TVP5146 decoder retains values in different modes until this decoder resets.

NTSC: default 007h,

PAL: default 004h

2.11.26 VBLK Start Line Register

Subaddress

22h–23h

Default

001h

Subaddress

22h

7

6

5

4

3

2

1

0

VBLK start [7:0]

23h

Reserved

VBLK start [9:8]

VBLK start [9:0]: This is an absolute line number. The TVP5146 decoder updates the VBLK start

line only when the VBLK start MSB byte is written to. If the user changes these registers, the

TVP5146 decoder retains values in different modes until this decoder resets.

NTSC: default 001h,

PAL: default 623 (26Fh)

2.11.27 VBLK Stop Line Register

Subaddress

24h–25h

Default

015h

Subaddress

24h

7

6

5

4

3

2

1

0

VBLK stop [7:0]

25h

Reserved

VBLK stop [9:8]

VBLK stop [9:0]: This is an absolute line number. The TVP5146 decoder updates the VBLK stop

only when the VBLK stop MSB byte is written to. If the user changes these registers, then the

TVP5146 decoder retains values in different modes until this decoder resets.

NTSC: default 21 (15h), PAL: default 23 (17h)

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TVP5146

2.11.28 Fast-Switch Control Register

Subaddress

28h

Default

CCh

7

6

5

4

3

2

1

0

Mode [2:0]

Reserved

FSS edge

Reserved

Polarity FSS

Mode [2:0]: Select fast-switch modes

000 = CVBS $ SCART

001 = Reserved

010 = Reserved

011 = Reserved

100 = Reserved

101 = Reserved

110 = Composite only (default)

111 = Component only

FSS edge: FSS is sampled at the rising or falling edge of the sampling clock

0 = Rising edge

1 = Falling edge (default)

Polarity FSS:

0 = 0: YCbCr/RGB

1 = 0: CVBS (4A)

1: CVBS (4A) (default)

1: YCbCr/RGB

2.11.29 Fast-Switch SCART Delay Register

Subaddress

2Ah

Default

00h

7

6

5

4

3

2

1

0

Reserved

FSS delay [4:0]

FSS delay [4:0]: Adjusts the delay between the FSS and component RGB/YPbPr

0 1111 = 15 pixel delay

0 0001 = 1 pixel delay

0 0000 = 0 delay (default)

1 1111 = –1 pixel delay

1 0000 = –16 pixel delay

2.11.30 SCART Delay Register

Subaddress

2Ch

Default

00h

7

6

5

4

3

2

1

0

Reserved

SCART delay [4:0]

SCART delay [4:0]: Adjusts delay between the CVBS and component (RGB) video

0 1111 = 15 pixel delay

0 0001 = 1 pixel delay

0 0000 = 0 delay (default)

1 1111 = –1 pixel delay

1 0000 = –16 pixel delay

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2.11.31 CTI Delay Register

Subaddress

2Dh

Default

00h

7

6

5

4

3

2

1

0

Reserved

CTI delay [2:0]

CTI delay [2:0]: Sets the delay of the Y channel with respect to Cb/Cr in the CTI block

011 = 3 pixel delay

001 = 1 pixel delay

000 = 0 delay (default)

111 = –1 pixel delay

100 = –4 pixel delay

2.11.32 CTI Control Register

Subaddress

2Eh

Default

00h

7

6

5

4

3

2

1

0

CTI coring [3:0]

CTI gain [3:0]

CTI coring [3:0]: 4-bit CTI coring limit control value, unsigned linear control range from 0 to 60,

step size = 4

1111 = 60

0001 = 4

0000 = 0 (default)

CTI gain [3:0]: 4-bit CTI gain control values, unsigned linear control range from 0 to 15/16, step

size = 1/16

1111 = 15/16

0001 = 1/16

0000 = 0 disabled (default)

2.11.33 RTC Register

Subaddress

31h

Default

05h

7

6

5

4

3

2

1

0

Reserved

Genlock [2:0]

Genlock [2:0]:

000 = Reserved

001 = Reserved

010 = Reserved

011 = Reserved

100 = Reserved

101 = RTC mode

110 = Reserved

111 = Reserved

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TVP5146

2.11.34 Sync Control Register

Subaddress

32h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Polarity FID

Polarity VS

Polarity HS

VS/VBLK

HS/CS

Polarity FID: determines polarity of FID terminal

0 = First field high, second field low (default)

1 = First field low, second field high

Polarity VS: determines polarity of VS terminal

0 = Active low (default)

1 = Active high

Polarity HS: determines polarity of HS terminal

0 = Active low (default)

1 = Active high

VS/VBLK:

0 = VS terminal outputs vertical sync (default)

1 = VS terminal outputs vertical blank

HS/CS:

0 = HS terminal outputs horizontal sync (default)

1 = HS terminal outputs composite sync

2.11.35 Output Formatter 1 Register

Subaddress

33h

Default

40h

7

6

5

4

3

2

1

0

Sampling rate

YCbCr code range

CbCr code

Reserved

Output format [2:0]

Sampling rate (changing this bit causes the register settings to be reinitialized):

0 = ITU-R BT.601 sampling rate (default)

1 = Square pixel sampling rate

YCbCr code range:

0 = ITU-R BT.601 coding range (Y ranges from 64 to 940. Cb and Cr range from 64 to 960.)

1 = Extended coding range (Y, Cb, and Cr range from 4 to 1016) (default)

CbCr code:

0 = Offset binary code (2s complement + 512) (default)

1 = Straight binary code (2s complement)

Output format [2:0]:

000 = 10-bit 4:2:2 (2× pixel rate) with embedded syncs (ITU-R BT.656) (default)

001 = 20-bit 4:2:2 (pixel rate) with separate syncs

010 = Reserved

011 = 10-bit 4:2:2 with separate syncs

100–111= Reserved

NOTE: 10-bit mode is also used for the raw VBI output mode when bit 4 (VBI raw) in the

luminance processing control 1 register at subaddress 06h is set (see Section 2.11.7).

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2.11.36 Output Formatter 2 Register

Subaddress

34h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Y[9:0] enable

Reserved

CLK polarity

Clock enable

Y[9:0] enable: Y[9:0] and C[9:0] output enable

0 = Y[9:0] and C[9:0] high impedance (default)

1 = Y [9:0] and C[9:0] active

CLK polarity:

0 = Data clocked out on the falling edge of DATACLK (default)

1 = Data clocked out on the rising edge of DATACLK

Clock enable:

0 = DATACLK outputs are high-impedance (default).

1 = DATACLK outputs are enabled.

2.11.37 Output Formatter 3 Register

Subaddress

35h

Default

FFh

7

6

5

4

3

2

1

0

FSS [1:0]

AVID [1:0]

GLCO [1:0]

FID [1:0]

FSS [1:0]: FSS terminal function select

00 = FSS is logic 0 output.

01 = FSS is logic 1 output.

10 = FSS is fast-switch input for SCART support.

11 = FSS is logic input (default).

AVID [1:0]: AVID terminal function select

00 = AVID is logic 0 output.

01 = AVID is logic 1 output.

10 = AVID is active video indicator output.

11 = AVID is logic input (default).

GLCO [1:0]: GLCO terminal function select

00 = GLCO is logic 0 output.

01 = GLCO is logic 1 output.

10 = GCLO is genlock output.

11 = GCLO is logic input (default).

FID [1:0]: FID terminal function select

00 = FID is logic 0 output.

01 = FID is logic 1 output.

10 = FID is FID output.

11 = FID is logic input (default).

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TVP5146

2.11.38 Output Formatter 4 Register

Subaddress

36h

Default

FFh

7

6

5

4

3

2

1

0

VS/VBLK [1:0]

HS/CS [1:0]

C_1 [1:0]

C_0 [1:0]

VS/VBLK [1:0]: VS terminal function select

00 = VS is logic 0 output.

01 = VS is logic 1 output.

10 = VS/VBLK is vertical sync or vertical blank output corresponding to bit 1 (VS/VBLK) in the sync control

register at subaddress 32h (see Section 2.11.34).

11 = VS is logic input (default).

HS/CS [1:0]: HS terminal function select

00 = HS is logic 0 output.

01 = HS is logic 1 output.

10 = HS/CS is horizontal sync or composite sync output corresponding to bit 0 (HS/CS) in the sync control

register at subaddress 32h (see Section 2.11.34).

11 = HS is logic input (default).

C_1 [1:0]: C_1 terminal function select

00 = C_1 is logic 0 output.

01 = C_1 is logic 1 output.

10 = Reserved

11 = C_1 is logic input (default).

C_0 [1:0]: C_0 terminal function select

00 = C_0 is logic 0 output.

01 = C_0 is logic 1 output.

10 = Reserved

11 = C_0 is logic input (default).

C_x functions are only available in the 10-bit output mode.

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2.11.39 Output Formatter 5 Register

Subaddress

37h

Default

FFh

7

6

5

4

3

2

1

0

C_5 [1:0]

C_4 [1:0]

C_3 [1:0]

C_2 [1:0]

C_5 [1:0]: C_5 terminal function select

00 = C_5 is logic 0 output.

01 = C_5 is logic 1 output.

10 = Reserved

11 = C_5 is logic input (default).

C_4 [1:0]: C_4 terminal function select

00 = C_4 is logic 0 output.

01 = C_4 is logic 1 output.

10 = Reserved

11 = C_4 is logic input (default).

C_3 [1:0]: C_3 terminal function select

00 = C_3 is logic 0 output.

01 = C_3 is logic 1 output.

10 = Reserved

11 = C_3 is logic input (default)

C_2 [1:0]: C_2 terminal function select

00 = C_2 is logic 0 output.

01 = C_2 is logic 1 output.

10 = Reserved

11 = C_2 is logic input (default).

C_x functions are only available in the 10-bit output mode.

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TVP5146

2.11.40 Output Formatter 6 Register

Subaddress

38h

Default

FFh

7

6

5

4

3

2

1

0

C_9 [1:0]

C_8 [1:0]

C_7 [1:0]

C_6 [1:0]

C_9 [1:0]: C_9 terminal function select

00 = C_9 is logic 0 output.

01 = C_9 is logic 1 output.

10 = Reserved

11 = C_9 is logic input (default).

C_8 [1:0]: C_8 terminal function select

00 = C_8 is logic 0 output.

01 = C_8 is logic 1 output.

10 = Reserved

11 = C_8 is logic input (default).

C_7 [1:0]: C_7 terminal function select

00 = C_7 is logic 0 output.

01 = C_7 is logic 1 output.

10 = Reserved

11 = C_7 is logic input (default).

C_6 [1:0]: C_6 terminal function select

00 = C_6 is logic 0 output.

01 = C_6 is logic 1 output.

10 = Reserved

11 = C_6 is logic input (default).

C_x functions are only available in the 10-bit output mode.

2.11.41 Clear Lost Lock Detect Register

Subaddress

39h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Clear lost lock detect

Clear lost lock detect: Clear bit 4 (lost lock detect) in the status 1 register at subaddress 3Ah

(see Section 2.11.42).

0 = No effect (default)

1 = Clears bit 4 in the status 1 register

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2.11.42 Status 1 Register

Subaddress

3Ah

Read only

7

6

5

4

3

2

1

0

Peak white

detect status

Line-alternating

status

Field rate

status

Lost lock

detect

Color subcarrier

lock status

Vertical sync

lock status

Horizontal sync

lock status

TV/VCR

status

Peak white detect status:

0 = Peak white is not detected.

1 = Peak white is detected.

Line-alternating status:

0 = Nonline-alternating

1 = Line-alternating

Field rate status:

0 = 60 Hz

1 = 50 Hz

Lost lock detect:

0 = No lost lock since this bit was cleared

1 = Lost lock since this bit was cleared.

Color subcarrier lock status:

0 = Color subcarrier is not locked.

1 = Color subcarrier is locked.

Vertical sync lock status:

0 = Vertical sync is not locked.

1 = Vertical sync is locked.

Horizontal sync lock status:

0 = Horizontal sync is not locked.

1 = Horizontal sync is locked.

TV/VCR status:

0 = TV

1 = VCR

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TVP5146

2.11.43 Status 2 Register

Subaddress

3Bh

Read only

7

6

5

4

3

2

1

0

Reserved

Weak signal detection

PAL switch polarity

Field sequence status

Reserved

Macrovision detection [2:0]

Weak signal detection:

0 = No weak signal

1 = Weak signal mode

PAL switch polarity of first line of odd field:

0 = PAL switch is zero.

1 = PAL switch is one.

Field sequence status:

0 = Even field

1 = Odd field

Macrovision detection [2:0]:

000 = No copy protection

001 = AGC pulses/pseudo syncs present (type 1)

010 = 2-line colorstripe only present

011 = AGC pulses/pseudo syncs and 2-line colorstripe present (type 2)

100 = Reserved

101 = Reserved

110 = 4-line colorstripe only present

111 = AGC pulses/pseudo syncs and 4-line colorstripe present (type 3)

2.11.44 AGC Gain Status Register

Subaddress

3Ch–3Dh

Read only

Subaddress

3Ch

7

6

5

4

3

2

1

0

Fine gain [7:0]

3Dh

Coarse gain [3:0]

Fine gain [11:8]

Fine gain [11:0]: This register provides the fine gain value of sync channel. See FGAIN 1 [11:0]

in the AFE fine gain for Pb_B register at subaddress 4Ah–4Bh (see Section 2.11.53).

1111 1111 1111 = 1.9995

1000 0000 0000 = 1

0010 0000 0000 = 0.5

Coarse gain [3:0]: This register provides the coarse gain value of sync channel. See CGAIN 1

[3:0] in the AFE coarse gain for CH1 register at subaddress 46h (see Section 2.11.49).

1111 = 2

0101 = 1

0000 = 0.5

These AGC gain status registers are updated automatically by the TVP5146 decoder with AGC

on. In manual gain control mode these register values are not updated by the TVP5146 decoder.

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2.11.45 Video Standard Status Register

Subaddress

3Fh

Read only

7

6

5

4

3

2

1

0

Autoswitch

Reserved

Video standard [2:0]

Autoswitch mode:

0 = Stand-alone (forced video standard) mode

1 = Autoswitch mode

Video standard [2:0]:

CVBS and S-video

000 = Reserved

001 = (M, J) NTSC

Component video

Reserved

Component 525

010 = (B, D, G, H, I, N) PAL Component 625

011 = (M) PAL Reserved

100 = (Combination-N) PAL Reserved

101 = NTSC 4.43

110 = SECAM

111 = PAL 60

Reserved

This register contains information about the detected video standard that the decoder is

currently operating. When autoswitch code is running, this register must be tested to determine

which video standard has been detected.

2.11.46 GPIO Input 1 Register

Subaddress

40h

Read only

7

6

5

4

3

2

1

0

C_7

C_6

C_5

C_4

C_3

C_2

C_1

C_0

C_x input status:

0 = Input is a low.

1 = Input is a high.

These status bits are only valid when terminals are used as inputs and their states updated at

every line.

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TVP5146

2.11.47 GPIO Input 2 Register

Subaddress

41h

Read only

7

6

5

4

3

2

1

0

FSS

AVID

GLCO

VS

HS

FID

C_9

C_8

FSS input terminal status:

0 = Input is a low.

1 = Input is a high.

AVID input terminal status:

0 = Input is a low.

1 = Input is a high.

GLCO input terminal status:

0 = Input is a low

1 = Input is a high.

VS input terminal status:

0 = Input is a low.

1 = Input is a high.

HS input status:

0 = Input is a low.

1 = Input is a high.

FID input status:

0 = Input is a low.

1 = Input is a high.

C_x input status:

0 = Input is a low.

1 = Input is a high.

These status bits are only valid when terminals are used as inputs and their states updated at

every line.

2.11.48 Vertical Line Count Register

Subaddress

42h–43h

Read only

Subaddress

42h

7

6

5

4

3

2

1

0

V_CNT[7:0]

43h

Reserved

V_CNT[9:8]

V_CNT[9:0] represents the detected total number of lines from the previous frame.

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2.11.49 AFE Coarse Gain for CH 1 Register

Subaddress

46h

Default

20h

7

6

5

4

3

2

1

0

CGAIN 1 [3:0]

Reserved

CGAIN 1 [3:0]: Coarse_Gain = 0.5 + (CGAIN 1)/10, where 0 ꢀ CGAIN 1 ꢀ 15

This register works only in manual gain control mode. When AGC is active, writing to any value

is ignored.

1111 = 2

1110 = 1.9

1101 = 1.8

1100 = 1.7

1011 = 1.6

1010 = 1.5

1001 = 1.4

1000 = 1.3

0111 = 1.2

0110 = 1.1

0101 = 1

0100 = 0.9

0011 = 0.8

0010 = 0.7 (default)

0001 = 0.6

0000 = 0.5

2.11.50 AFE Coarse Gain for CH 2 Register

Subaddress

47h

Default

20h

7

6

5

4

3

2

1

0

CGAIN 2 [3:0]

Reserved

CGAIN 2 [3:0]: Coarse_Gain = 0.5 + (CGAIN 2)/10, where 0 ꢀ CGAIN 2 ꢀ 15

This register works only in manual gain control mode. When AGC is active, writing to any value

is ignored.

1111 = 2

1110 = 1.9

1101 = 1.8

1100 = 1.7

1011 = 1.6

1010 = 1.5

1001 = 1.4

1000 = 1.3

0111 = 1.2

0110 = 1.1

0101 = 1

0100 = 0.9

0011 = 0.8

0010 = 0.7 (default)

0001 = 0.6

0000 = 0.5

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TVP5146

2.11.51 AFE Coarse Gain for CH 3 Register

Subaddress

48h

Default

20h

7

6

5

4

3

2

1

0

CGAIN 3 [3:0]

Reserved

CGAIN 3 [3:0]: Coarse_Gain = 0.5 + (CGAIN 3)/10, where 0 ꢀ CGAIN 3 ꢀ 15

This register works only in the manual gain control mode. When AGC is active, writing to any

value is ignored.

1111 = 2

1110 = 1.9

1101 = 1.8

1100 = 1.7

1011 = 1.6

1010 = 1.5

1001 = 1.4

1000 = 1.3

0111 = 1.2

0110 = 1.1

0101 = 1

0100 = 0.9

0011 = 0.8

0010 = 0.7 (default)

0001 = 0.6

0000 = 0.5

2.11.52 AFE Coarse Gain for CH 4 Register

Subaddress

49h

Default

20h

7

6

5

4

3

2

1

0

CGAIN 4 [3:0]

Reserved

CGAIN 4 [3:0]: Coarse_Gain = 0.5 + (CGAIN 4)/10, where 0 ꢀ CGAIN 4 ꢀ 15

This register works only in the manual gain control mode. When AGC is active, writing to any

value is ignored.

1111 = 2

1110 = 1.9

1101 = 1.8

1100 = 1.7

1011 = 1.6

1010 = 1.5

1001 = 1.4

1000 = 1.3

0111 = 1.2

0110 = 1.1

0101 = 1

0100 = 0.9

0011 = 0.8

0010 = 0.7 (default)

0001 = 0.6

0000 = 0.5

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2.11.53 AFE Fine Gain for Pb_B Register

Subaddress

4Ah–4Bh

Default

900h

Subaddress

4Ah

7

6

5

4

3

2

1

0

FGAIN 1 [7:0]

4Bh

Reserved

FGAIN 1 [11:8]

FGAIN 1 [11:0]: This fine gain applies to component Pb/B.

Fine_Gain = (1/2048) * FGAIN 1, where 0 ꢀ FGAIN 1 ꢀ 4095

This register works only in manual gain control mode. When AGC is active, writing to any value

is ignored.

1111 1111 1111 = 1.9995

1100 0000 0000 = 1.5

1001 0000 0000 = 1.125 (default)

1000 0000 0000 = 1

0100 0000 0000 = 0.5

0011 1111 1111 to 0000 0000 0000 = Reserved

2.11.54 AFE Fine Gain for Y_G_Chroma Register

Subaddress

4Ch–4Dh

Default

900h

Subaddress

4Ch

7

6

5

4

3

2

1

0

FGAIN 2 [7:0]

4Dh

Reserved

FGAIN 2 [11:8]

FGAIN 2 [11:0]: This gain applies to component Y/G channel or S-video chroma.

Fine_Gain = (1/2048) * FGAIN 2, where 0 ꢀ FGAIN 2 ꢀ 4095

This register works only in manual gain control mode. When AGC is active, writing to any value

is ignored.

1111 1111 1111 = 1.9995

1100 0000 0000 = 1.5

1001 0000 0000 = 1.125 (default)

1000 0000 0000 = 1

0100 0000 0000 = 0.5

0011 1111 1111 to 0000 0000 0000 = Reserved

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2.11.55 AFE Fine Gain for R_Pr Register

Subaddress

4Eh–4Fh

Default

900h

Subaddress

4Eh

7

6

5

4

3

2

1

0

FGAIN 3 [7:0]

4Fh

Reserved

FGAIN 3 [11:8]

FGAIN 3 [11:0]: This fine gain applies to component Pb/B.

Fine_Gain = (1/2048) * FGAIN 3, where 0 ꢀ FGAIN 3 ꢀ 4095

This register works only in manual gain control mode. When AGC is active, writing to any value

is ignored.

1111 1111 1111 = 1.9995

1100 0000 0000 = 1.5

1001 0000 0000 = 1.125 (default)

1000 0000 0000 = 1

0100 0000 0000 = 0.5

0011 1111 1111 to 0000 0000 0000 = Reserved

2.11.56 AFE Fine Gain for CVBS_Luma Register

Subaddress

50h–51h

Default

900h

Subaddress

50h

7

6

5

4

3

2

1

0

FGAIN 4 [7:0]

51h

Reserved

FGAIN 4 [11:8]

FGAIN 4 [11:0]: This fine gain applies to CVBS or S-video luma.

Fine_Gain = (1/2048) * FGAIN 4, where 0 ꢀ FGAIN 4 ꢀ 4095

This register works only in manual gain control mode. When AGC is active, writing to any value

is ignored.

1111 1111 1111 = 1.9995

1100 0000 0000 = 1.5

1001 0000 0000 = 1.125 (default)

1000 0000 0000 = 1

0100 0000 0000 = 0.5

0011 1111 1111 to 0000 0000 0000 = Reserved

2.11.57 ROM Version Register

Subaddress

70h

Read only

7

6

5

4

3

2

1

0

ROM version [7:0]

ROM Version [7:0]: ROM revision number

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2.11.58 AGC White Peak Processing Register

Subaddress

74h

Default

00h

7

6

5

4

3

2

1

0

Luma peak A

Reserved

Color burst A

Sync height A

Luma peak B

Composite peak

Color burst B Sync height B

Luma peak A: Use of the luma peak as a video amplitude reference for the back-end

feed-forward type AGC algorithm.

0 = Enabled (default)

1 = Disabled

Color burst A: Use of the color burst amplitude as a video amplitude reference for the back-end.

NOTE: Not available for SECAM, component, and B/W video sources.

0 = Enabled (default)

1 = Disabled

Sync height A: Use of the sync height as a video amplitude reference for the back-end

feed-forward type AGC algorithm.

0 = Enabled (default)

1 = Disabled

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Luma peak B: Use of the luma peak as a video amplitude reference for the front-end feedback

type AGC algorithm.

0 = Enabled (default)

1 = Disabled

Composite peak: Use of the composite peak as a video amplitude reference for the front-end

feedback type AGC algorithm.

NOTE: Required for CVBS and SCART (with color burst) video sources.

0 = Enabled (default)

1 = Disabled

Color burst B: Use of the color burst amplitude as a video amplitude reference for the front-end

feedback type AGC algorithm.

NOTE: Not available for SECAM, component, and B/W video sources.

0 = Enabled (default)

1 = Disabled

Sync height B: Use of the sync height as a video amplitude reference for the front-end feedback

type AGC algorithm.

0 = Enabled (default)

1 = Disabled

NOTE: If all 4 bits of the lower nibble are set to logic 1 (that is, no amplitude reference selected),

then the front-end analog and digital gains are automatically set to nominal values of 2 and

2304, respectively.

If all 4 bits of the upper nibble are set to logic 1 (that is, no amplitude reference selected), then

the back-end gain is set automatically to unity.

If the input sync height is greater than 100% and the AGC-adjusted output video amplitude

becomes less than 100%, then the back-end scale factor attempts to increase the contrast in the

back end to restore the video amplitude to 100%.

2.11.59 AGC Increment Speed Register

Subaddress

78h

Default

06h

7

6

5

4

3

2

1

0

Reserved

AGC increment speed [3:0]

AGC increment speed: Adjusts gain increment speed.

111 = 7 (slowest)

110 = 6 (default)

L

000 = 0 (fastest)

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2.11.60 AGC Increment Delay Register

Subaddress

79h

Default

1Eh

7

6

5

4

3

2

1

0

AGC increment delay [7:0]

AGC increment delay: Number of frames to delay gain increments

1111 1111 = 255

L

0001 1110 = 30 (default)

L

0000 0000 = 0

2.11.61 Chip ID MSB Register

Subaddress

80h

Read only

7

6

5

4

3

2

1

0

Chip ID MSB [7:0]

Chip ID MSB [7:0]: This register identifies the MSB of the device ID. Value = 51h

2.11.62 Chip ID LSB Register

Subaddress

81h

Read only

7

6

5

4

3

2

1

0

Chip ID LSB [7:0]

Chip ID LSB [7:0]: This register identifies the LSB of the device ID. Value = 46h

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2.11.63 VDP TTX Filter And Mask Registers

Subaddress

B1h

B2h

B3h

B4h

B5h

B6h

B7h

00h

B8h

00h

B9h

00h

BAh

00h

Default

00h

Subaddress

B1h

7

6

5

4

3

2

1

0

Filter 1 mask 1

Filter 1 mask 2

Filter 1 mask 3

Filter 1 mask 4

Filter 1 mask 5

Filter 2 mask 1

Filter 2 mask 2

Filter 2 mask 3

Filter 2 mask 4

Filter 2 mask 5

Filter 1 pattern 1

Filter 1 pattern 2

Filter 1 pattern 3

Filter 1 pattern 4

Filter 1 pattern 5

Filter 2 pattern 1

Filter 2 pattern 2

Filter 2 pattern 3

Filter 2 pattern 4

Filter 2 pattern 5

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

BAh

For an NABTS system, the packet prefix consists of five bytes. Each byte contains 4 data bits

(D[3:0]) interlaced with 4 Hamming protection bits (H[3:0]):

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

D3

H3

D2

H2

D1

H1

D0

H0

Only data portion D[3:0] from each byte is applied to a teletext filter function with corresponding

pattern bits P[3:0] and mask bits M[3:0] (see Figure 2−27). The filter ignores the Hamming

protection bits.

For WST system (PAL or NTSC), the packet prefix consists of two bytes. The two bytes contain

three bits of magazine number (M[2:0]) and five bits of row address (R[4:0]), interlaced with eight

Hamming protection bits H[7:0]:

Bit 7

R0

Bit 6

H3

Bit 5

M2

Bit 4

H2

Bit 3

M1

Bit 2

H1

Bit 1

M0

Bit 0

H0

R4

H7

R3

H6

R2

H5

R1

H4

The mask bits enable filtering using the corresponding bit in the pattern register. For example, a

1 in the LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the

pattern register to the first data bit on the transaction. If these match, then a true result is

returned. A 0 in a mask bit means that the filter module must ignore that data bit of the

transaction. If all 0s are programmed in the mask bits, then the filter matches all patterns

returning a true result (default 00h).

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2.11.64 VDP TTX Filter Control Register

Subaddress

BBh

Default

00h

7

6

5

4

3

2

1

0

Reserved

Filter logic [1:0]

Mode

TTX filter 2 enable

TTX filter 1 enable

Filter logic [1:0]: Allows different logic to be applied when combining the decision of filter 1 and

filter 2 as follows:

00 = NOR (default)

01 = NAND

10 = OR

11 = AND

Mode: Indicates which teletext mode is in use.

0 = Teletext filter applies to 2 header bytes (default)

1 = Teletext filter applies to 5 header bytes

TTX filter 2 enable: Provides for enabling the teletext filter function within the VDP.

0 = Disabled (default)

1 = Enabled

TTX filter 1 enable: Provides for enabling the teletext filter function within the VDP.

0 = Disabled (default)

1 = Enabled

If the filter matches or if the filter mask is all 0s, then a true result is returned.

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1P1[3]

D1[3]

1M1[3]

1P1[2]

D1[2]

1M1[2]

1M1[1]

1P1[1]

D1[1]

1P1[0]

D1[0]

1M1[0]

NIBBLE 1

D2[3:0]

1P2[3:0]

1M2[3:0]

NIBBLE 2

NIBBLE 3

NIBBLE 4

NIBBLE 5

PASS 1

D3[3:0]

1P3[3:0]

1M3[3:0]

Filter 1

Enable

00

01

D4[3:0]

1P4[3:0]

1M4[3:0]

PASS

10

11

D5[3:0]

1P5[3:0]

1M5[3:0]

2

FILTER 1

FILTER 2

Filter Logic

D1..D5

2P1..2P5

2M1..2M5

PASS 2

Filter 2

Enable

Figure 2−27. Teletext Filter Function

2.11.65 VDP FIFO Word Count Register

Subaddress

BCh

Read only

7

6

5

4

3

2

1

0

FIFO word count [7:0]

FIFO word count [7:0]: This register provides the number of words in the FIFO.

NOTE: 1 word equals 2 bytes.

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2.11.66 VDP FIFO Interrupt Threshold Register

Subaddress

BDh

Default

80h

7

6

5

4

3

2

1

0

Threshold [7:0]

Threshold [7:0]: This register is programmed to trigger an interrupt when the number of words in

the FIFO exceeds this value.

NOTE: 1 word equals 2 bytes.

2.11.67 VDP FIFO Reset Register

Subaddress

BFh

Default

00h

7

6

5

4

3

2

1

0

Reserved

FIFO reset

FIFO reset: Writing any data to this register clears the FIFO and VDP data registers (CC, WSS,

VITC and VPS). After clearing them, this register is automatically cleared.

2.11.68 VDP FIFO Output Control Register

Subaddress

C0h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Host access enable

Host access enable: This register is programmed to allow the host port access to the FIFO or to

allow all VDP data to go out the video output.

0 = Output FIFO data to the video output Y[9:2] (default)

1 = Allow host port access to the FIFO data

2.11.69 VDP Line Number Interrupt Register

Subaddress

C1h

Default

00h

7

6

5

4

3

2

1

0

Field 1 enable

Field 2 enable

Line number [5:0]

Field 1 enable:

0 = Interrupt disabled (default)

1 = Interrupt enabled

Field 2 enable:

0 = Interrupt disabled (default)

1 = Interrupt enabled

Line number [5:0]: Interrupt line number (default 00h)

This register is programmed to trigger an interrupt when the video line number exceeds this

value in bits [5:0]. This interrupt must be enabled at address F4h.

NOTE: The line number value of 0 or 1 is invalid and does not generate an interrupt.

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2.11.70 VDP Pixel Alignment Register

Subaddress

C2h–C3h

Default

01Eh

Subaddress

C2h

7

6

5

4

3

2

1

0

Pixel alignment [7:0]

C3h

Reserved

Pixel alignment [9:8]

Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge

of horizontal sync, where the VDP controller initiates the program from one line standard to the

next line standard. For example, the previous line of teletext to the next line of closed caption.

This value must be set so that the switch occurs after the previous transaction has cleared the

delay in the VDP, but early enough to allow the new values to be programmed before the current

settings are required.

The default value is 0x1E and has been tested with every standard supported here. A new value

is needed only if a custom standard is in use.

2.11.71 VDP Line Start Register

Subaddress

D6h

Default

06h

7

6

5

4

3

2

1

0

VDP line start [7:0]

VDP line start [7:0]: Sets the VDP line starting address

This register must be set properly before enabling the line mode registers. VDP processor works

only in the VBI region set by this register and the VDP line stop register at subaddress D7h (see

Section 2.11.72).

2.11.72 VDP Line Stop Register

Subaddress

D7h

Default

1Bh

7

6

5

4

3

2

1

0

VDP line stop [7:0]

VDP line stop [7:0]: Sets the VDP stop line address

2.11.73 VDP Global Line Mode Register

Subaddress

D8h

Default

FFh

7

6

5

4

3

2

1

0

Global line mode [7:0]

Global line mode [7:0]: VDP processing for multiple lines set by the VDP start line register at

subaddress D6h and the VDP stop line register at subaddress D7h.

Global line mode register has the same bit definition as the general line mode registers.

General line mode has priority over the global line mode.

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2.11.74 VDP Full Field Enable Register

Subaddress

D9h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Full field enable

Full field enable:

0 = Disabled full field mode (default)

1 = Enabled full field mode

This register enables the full field mode. In this mode, all lines outside the vertical blank area

and all lines in the line mode register programmed with FFh are sliced with the definition of the

VDP full field mode register at subaddress DAh. Values other than FFh in the line mode

registers allow a different slice mode for that particular line.

2.11.75 VDP Full Field Mode Register

Subaddress

DAh

Default

FFh

7

6

5

4

3

2

1

0

Full field mode [7:0]

Full field mode [7:0]:

This register programs the specific VBI standard for full field mode. It can be any VBI standard.

Individual line settings take priority over the full field register. This allows each VBI line to be

programmed independently but have the remaining lines in full field mode. The full field mode

register has the same bit definition as line mode registers (default FFh).

Global line mode has priority over the full field mode.

2.11.76 VBUS Data Access With No VBUS Address Increment Register

Subaddress

E0h

Default

00h

7

6

5

4

3

2

1

0

VBUS data [7:0]

VBUS data [7:0]: VBUS data register for VBUS single byte read/write transaction.

2.11.77 VBUS Data Access With VBUS Address Increment Register

Subaddress

E1h

Default

00h

7

6

5

4

3

2

1

0

VBUS data [7:0]

VBUS data [7:0]: VBUS data register for VBUS multibyte read/write transaction. VBUS address

is autoincremented after each data byte read/write.

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TVP5146

2.11.78 FIFO Read Data Register

Subaddress

E2h

Read only

7

6

5

4

3

2

1

0

FIFO read data [7:0]

FIFO read data [7:0]: This register is provided to access VBI FIFO data through the host port. All

forms of teletext data come directly from the FIFO, while all other forms of VBI data can be

programmed to come from registers or from the FIFO. If the host port is to be used to read data

from the FIFO, then bit 0 (host access enable) in the VDP FIFO output control register at

subaddress C0h must be set to 1 (see Section 2.11.68).

2.11.79 VBUS Address Access Register

Subaddress

E8h

E9h

EAh

Default

00h

Subaddress

E8h

7

6

5

4

3

2

1

0

VBUS address [7:0]

VBUS address [15:8]

VBUS address [23:16]

E9h

EAh

VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user must program in these

registers the 24-bit address of the internal register to be accessed via host port indirect access

mode.

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2.11.80 Interrupt Raw Status 0 Register

Subaddress

F0h

Read only

7

6

5

4

3

2

1

0

FIFO THRS

TTX

WSS

VPS

VITC

CC F2

CC F1

Line

FIFO THRS: FIFO threshold passed, unmasked

0 = Not passed

1 = Passed

TTX: Teletext data available unmasked

0 = Not available

1 = Available

WSS: WSS data available unmasked

0 = Not available

1 = Available

VPS: VPS data available unmasked

0 = Not available

1 = Available

VITC: VITC data available unmasked

0 = Not available

1 = Available

CC F2: CC field 2 data available unmasked

0 = Not available

1 = Available

CC F1: CC field 1 data available unmasked

0 = Not available

1 = Available

Line: Line number interrupt unmasked

0 = Not available

1 = Available

See also the interrupt raw status 1 register at subaddress F1h (see Section 2.11.81).

The host interrupt raw status 0 and 1 registers represent the interrupt status without applying

mask bits.

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2.11.81 Interrupt Raw Status 1 Register

Subaddress

F1h

Read only

7

6

5

4

3

2

1

0

Reserved

Macrovision status changed

Standard changed

FIFO full

Macrovision status changed: unmasked

0 = Macrovision status unchanged

1 = Macrovision status changed

Standard changed: unmasked

0 = Video standard unchanged

1 = Video standard changed

FIFO full: unmasked

0 = FIFO not full

1 = FIFO was full during write to FIFO

The FIFO full error flag is set when the current line of VBI data cannot enter the FIFO. For

example, if the FIFO has only 10 bytes left and teletext is the current VBI line, then the FIFO full

error flag is set, but no data is written because the entire teletext line does not fit. However, if the

next VBI line is closed caption requiring only 2 bytes of data plus the header, then this goes into

the FIFO even if the full error flag is set.

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2.11.82 Interrupt Status 0 Register

Subaddress

F2h

Read only

7

6

5

4

3

2

1

0

FIFO THRS

TTX

WSS

VPS

VITC

CC F2

CC F1

Line

FIFO THRS: FIFO threshold passed, masked

0 = Not passed

1 = Passed

TTX: Teletext data available masked

0 = Not available

1 = Available

WSS: WSS data available masked

0 = Not available

1 = Available

VPS: VPS data available masked

0 = Not available

1 = Available

VITC: VITC data available masked

0 = Not available

1 = Available

CC F2: CC field 2 data available masked

0 = Not available

1 = Available

CC F1: CC field 1 data available masked

0 = Not available

1 = Available

Line: Line number interrupt masked

0 = Not available

1 = Available

See also the interrupt status 1 register at subaddress F3h (see Section 2.11.83).

The interrupt status 0 and 1 registers represent the interrupt status after applying mask bits.

Therefore, the status bits are the result of a logical AND between the raw status and mask bits.

The external interrupt terminal is derived from this register as an OR function of all nonmasked

interrupts in this register.

Reading data from the corresponding register does not clear the status flags automatically.

These flags are reset using the corresponding bits in interrupt clear 0 and 1 registers.

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2.11.83 Interrupt Status 1 Register

Subaddress

F3h

Read only

7

6

5

4

3

2

1

0

Reserved

Macrovsion status changed

Standard changed

FIFO full

Macrovision status changed: Macrovision status changed masked

0 = Macrovision status not changed

1 = Macrovision status changed

Standard changed: Standard changed masked

0 = Video standard not changed

1 = Video standard changed

FIFO full: Full status of FIFO masked

0 = FIFO not full

1 = FIFO was full during write to FIFO, see the interrupt mask 1 register at subaddress F5h for details (see

Section 2.11.85)

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2.11.84 Interrupt Mask 0 Register

Subaddress

F4h

Default

00h

7

6

5

4

3

2

1

0

FIFO THRS

TTX

WSS

VPS

VITC

CC F2

CC F1

Line

FIFO THRS: FIFO threshold passed mask

0 = Disabled (default)

1 = Enabled FIFO_THRES interrupt

TTX: Teletext data available mask

0 = Disabled (default)

1 = Enabled TTX available interrupt

WSS: WSS data available mask

0 = Disabled (default)

1 = Enabled WSS available interrupt

VPS: VPS data available mask

0 = Disabled (default)

1 = Enabled VPS available interrupt

VITC: VITC data available mask

0 = Disabled (default)

1 = Enabled VITC available interrupt

CC F2: CC field 2 data available mask

0 = Disabled (default)

1 = Enabled CC_field 2 available interrupt

CC F1: CC field 1 data available mask

0 = Disabled (default)

1 = Enabled CC_field 1 available interrupt

Line: Line number interrupt mask

0 = Disabled (default)

1 = Enabled Line_INT interrupt

See also the interrupt mask 1 register at subaddress F5h (see Section 2.11.85).

The host interrupt mask 0 and 1 registers can be used by the external processor to mask

unnecessary interrupt sources for the interrupt status 0 and 1 register bits, and for the external

interrupt terminal. The external interrupt is generated from all nonmasked interrupt flags.

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2.11.85 Interrupt Mask 1 Register

Subaddress

F5h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Macrovision status changed

Standard changed

FIFO full

Macrovision status changed: Macrovision status changed mask

0 = Macrovision status unchanged

1 = Macrovision status changed

Standard changed: Standard changed mask

0 = Disabled (default)

1 = Enabled video standard changed

FIFO full: FIFO full mask

0 = Disabled (default)

1 = Enabled FIFO full interrupt

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2.11.86 Interrupt Clear 0 Register

Subaddress

F6h

Default

00h

7

6

5

4

3

2

1

0

FIFO THRS

TTX

WSS

VPS

VITC

CC F2

CC F1

Line

FIFO THRS: FIFO threshold passed clear

0 = No effect (default)

1 = Clear bit 7 (FIFO_THRS) in the interrupt status 0 register at subaddress F2h

TTX: Teletext data available clear

0 = No effect (default)

1 = Clear bit 6 (TTX available) in the interrupt status 0 register at subaddress F2h

WSS: WSS data available clear

0 = No effect (default)

1 = Clear bit 5 (WSS available) in the interrupt status 0 register at subaddress F2h

VPS: VPS data available clear

0 = No effect (default)

1 = Clear bit 4 (VPS available) in the interrupt status 0 register at subaddress F2h

VITC: VITC data available clear

0 = Disabled (default)

1 = Clear bit 3 (VITC available) in the interrupt status 0 register at subaddress F2h

CC F2: CC field 2 data available clear

0 = Disabled (default)

1 = Clear bit 2 (CC field 2 available) in the interrupt status 0 register at subaddress F2h

CC F1: CC field 1 data available clear

0 = Disabled (default)

1 = Clear bit 1 (CC field 1 available) in the interrupt status 0 register at subaddress F2h

Line: Line number interrupt clear

0 = Disabled (default)

1 = Clear bit 0 (line interrupt available) in the interrupt status 0 register at subaddress F2h

See also the interrupt clear 1 register at subaddress F7h (see Section 2.11.87).

The host interrupt clear 0 and 1 registers are used by the external processor to clear the

interrupt status bits in the host interrupt status 0 and 1 registers. When no nonmasked interrupts

remain set in the registers, the external interrupt terminal also becomes inactive.

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TVP5146

2.11.87 Interrupt Clear 1 Register

Subaddress

F7h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Macrovision status changed

Standard changed

FIFO full

Macrovision status changed: Clear Macrovision status changed flag

0 = No effect (default)

1 = Clear bit 2 (Macrovision status changed) in the interrupt status 1 register at subaddress F3h and the

interrupt raw status 1 register at subaddress F1h

Standard changed: Clear standard changed flag

0 = No effect (default)

1 = Clear bit 1 (video standard changed) in the interrupt status 1 register at subaddress F3h and the

interrupt raw status 1 register at subaddress F1h

FIFO full: Clear FIFO full flag

0 = No effect (default)

1 = Clear bit 0 (FIFO full flag) in the interrupt status 1 register at subaddress F3h and the interrupt raw

status 1 register at subaddress F1h

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2.12 VBUS Register Definitions

2.12.1 VDP Closed Caption Data Register

Subaddress

80 051Ch–80 051Fh

Read only

Subaddress

80 051Ch

80 051Dh

80 051Eh

80 051Fh

7

6

5

4

3

2

1

0

Closed caption field 1 byte 1

Closed caption field 1 byte 2

Closed caption field 2 byte 1

Closed caption field 2 byte 2

These registers contain the closed caption data arranged in bytes per field.

2.12.2 VDP WSS Data Register

Subaddress

80 0520h–80 0526h

WSS NTSC (CGMS):

Read only

Subaddress

80 0520h

80 0521h

80 0522h

80 0523h

80 0524h

80 0525h

80 0526h

7

6

5

4

3

2

1

0

Byte

b5

b4

b3

b2

b1

b0

WSS field 1 byte 1

WSS field 1 byte 2

WSS field 1 byte 3

b13

b12

b11

b19

b10

b18

b9

b8

b7

b6

b17

b16

b15

b14

Reserved

b5

b4

b3

b9

b2

b8

b1

b7

b0

b6

WSS field 2 byte 1

WSS field 2 byte 2

WSS field 2 byte 3

b13

b12

b11

b19

b10

b18

b17

b16

b15

b14

These registers contain the wide screen signaling data for NTSC.

Bits 0–1 represent word 0, aspect ratio.

Bits 2–5 represent word 1, header code for word 2.

Bits 6–13 represent word 2, copy control.

Bits 14–19 represent word 3, CRC.

PAL/SECAM:

Read only

Subaddress

80 0520h

80 0521h

80 0522h

80 0523h

80 0524h

80 0525h

80 0526h

7

6

5

4

3

2

1

0

Byte

b7

b6

b5

b4

b3

b2

b1

b9

b0

b8

WSS field 1 byte 1

WSS field 1 byte 2

b13

b12

b11

b10

Reserved

b7

b6

b5

b4

b12

b3

b2

b1

b9

b0

b8

WSS field 2 byte 1

WSS field 2 byte 2

b13

b11

b10

Reserved

PAL/SECAM:

Bits 0–3 represent group 1, aspect ratio.

Bits 4–7 represent group 2, enhanced services.

Bits 8–10 represent group 3, subtitles.

Bits 11–13 represent group 4, others.

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TVP5146

2.12.3 VDP VITC Data Register

Subaddress

80 052Ch–80 0534h

Read only

Subaddress

80 052Ch

80 052Dh

80 052Eh

80 052Fh

80 0530h

80 0531h

80 0532h

80 0533h

80 0534h

7

6

5

4

3

2

1

0

VITC frame byte 1

VITC frame byte 2

VITC seconds byte 1

VITC seconds byte 2

VITC minutes byte 1

VITC minutes byte 2

VITC hours byte 1

VITC hours byte 2

VITC CRC byte

These registers contain the VITC data.

2.12.4 VDP V-Chip TV Rating Block 1 Register

Subaddress

80 0540h

Read only

7

6

5

4

3

2

1

0

Reserved

14-D

PG-D

Reserved

MA-L

14-L

PG-L

Reserved

TV parental guidelines rating block 1:

14-D: When incoming video program is TV-14-D rated, then this bit is set high

PG-D: When incoming video program is TV-PG-D rated, then this bit is set high

MA-L: When incoming video program is TV-MA-L rated, then this bit is set high

14-L: When incoming video program is TV-14-L rated, then this bit is set high

PG-L: When incoming video program is TV-PG-L rated, then this bit is set high

2.12.5 VDP V-Chip TV Rating Block 2 Register

Subaddress

80 0541h

Read only

7

6

5

4

3

2

1

0

MA-S

14-S

PG-S

Reserved

MA-V

14-V

PG-V

Y7-FV

TV parental guidelines rating block 2:

MA-S: When incoming video program is TV-MA-S rated, then this bit is set high

14-S: When incoming video program is TV-14-S rated, then this bit is set high

PG-S: When incoming video program is TV-PG-S rated, then this bit is set high

MA-V: When incoming video program is TV-MA-V rated, then this bit is set high

14-V: When incoming video program is TV-14-V rated, then this bit is set high

PG-V: When incoming video program is TV-PG-S rated, then this bit is set high

Y7-FV: When incoming video program is TV-Y7-FV rated, then this bit is set high

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2.12.6 VDP V-Chip TV Rating Block 3 Register

Subaddress

80 0542h

Read only

7

6

5

4

3

2

1

0

None

TV-MA

TV-14

TV-PG

TV-G

TV-Y7

TV-Y

None

TV parental guidelines rating block 3:

None: No block intended

TV-MA: When incoming video program is TV-MA rated in TV Parental Guidelines Rating, then this bit is set

high

TV-14: When incoming video program is TV-14 rated in TV Parental Guidelines Rating, then this bit is set

high

TV-PG: When incoming video program is TV-PG rated in TV Parental Guidelines Rating, then this bit is set

high

TV-G: When incoming video program is TV-G rated in TV Parental Guidelines Rating, then this bit is set

high

TV-Y7: When incoming video program is TV-Y7 rated in TV Parental Guidelines Rating, then this bit is set

high

TV-Y: When incoming video program is TV-G rated in TV Parental Guidelines Rating, then this bit is set

high

None: No block intended

2.12.7 VDP V-Chip MPAA Rating Data Register

Subaddress

80 0543h

Read only

7

6

5

4

3

2

1

0

Not Rated

X

NC-17

R

PG-13

PG

G

N/A

MPAA rating block (E5h):

Not Rated: When incoming video program is Not Rated rated in MPAA Rating, then this bit is set high

X: When incoming video program is X rated in MPAA Rating, then this bit is set high

NC-17: When incoming video program is NC-17 rated in MPAA Rating, then this bit is set high

R: When incoming video program is R rated in MPAA Rating, then this bit is set high

PG-13: When incoming video program is PG-13 rated in MPAA Rating, then this bit is set high

PG: When incoming video program is PG rated in MPAA Rating, then this bit is set high

G: When incoming video program is G rated in MPAA Rating, then this bit is set high

N/A: When incoming video program is N/A rated in MPAA Rating, then this bit is set high

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TVP5146

2.12.8 VDP General Line Mode and Line Address Register

Subaddress

80 0600h–80 0611h

(default line mode = FFh, address = 00h)

Subaddress

80 0600h

80 0601h

80 0602h

80 0603h

80 0604h

80 0605h

80 0606h

80 0607h

80 0608h

80 0609h

80 060Ah

80 060Bh

80 060Ch

80 060Dh

80 060Eh

80 060Fh

80 0610h

80 0611h

7

6

5

4

3

2

1

0

Line address 1

Line mode 1

Line address 2

Line mode 2

Line address 3

Line mode 3

Line address 4

Line mode 4

Line address 5

Line mode 5

Line address 6

Line mode 6

Line address 7

Line mode 7

Line address 8

Line mode 8

Line address 9

Line mode 9

Line address x [7:0]: Line number to be processed by a VDP set by a line mode register (default

00h)

Line mode x [7:0]:

Bit 7:

0 = Disabled filters

1 = Enabled filters for teletext and CC (Null byte filter) (default)

Bit 6:

0 = Send sliced VBI data to registers only (default)

1 = Send sliced VBI data to FIFO and registers, teletext data only goes to FIFO

(default)

Bit 5:

0 = Allow VBI data with errors in the FIFO

1 = Do not allow VBI data with errors in the FIFO (default)

Bit 4:

Bit 3:

0 = Disabled error detection and correction

1 = Enabled error detection and correction (teletext only) (default)

0 = Field 1

1 = Field 2 (default)

Bits [2:0]: 000 = Teletext (WST625, Chinese teletext, NABTS 525)

001 = CC (US, Europe, Japan, China)

010 = WSS (525, 625)

011 = VITC

100 = VPS (PAL only), EPG (NTSC only)

101 = USER 1

110 = USER 2

111 = Reserved (active video) (default)

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2.12.9 VDP VPS/Gemstar Data Register

Subaddress

80 0700h–80 070Ch

VPS: Read only

Subaddress

80 0700h

80 0701h

80 0702h

80 0703h

80 0704h

80 0705h

80 0706h

80 0707h

80 0708h

80 0709h

80 070Ah

80 070Bh

80 070Ch

7

6

5

4

3

2

1

0

VPS byte 1

VPS byte 2

VPS byte 3

VPS byte 4

VPS byte 5

VPS byte 6

VPS byte 7

VPS byte 8

VPS byte 9

VPS byte 10

VPS byte 11

VPS byte 12

VPS byte 13

These registers contain the entire VPS data line except the clock run-in code or the start code.

Gemstar: Read only

Subaddress

80 0700h

80 0701h

80 0702h

80 0703h

80 0704h

80 0705h

80 0706h

80 0707h

80 0708h

80 0709h

80 070Ah

80 070Bh

80 070Ch

7

6

5

4

3

2

1

0

Gemstar frame code

Gemstar byte 1

Gemstar byte 2

Gemstar byte 3

Gemstar byte 4

Reserved

2.12.10 VDP FIFO Read Register

Subaddress

90 1904h

Read only

7

6

5

4

3

2

1

0

FIFO data [7:0]

FIFO data [7:0]: This register is provided to access VBI FIFO data through the host port. All

forms of teletext data come directly from the FIFO, while all other forms of VBI data can be

programmed to come from registers or from the FIFO. If the host port is to be used to read data

from the FIFO, then bit 0 (host access enable) in the FIFO output control register at subaddress

C0h must be set to 1.

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2.12.11 Interrupt Configuration Register

Subaddress

B0 0060h

Default

00h

7

6

5

4

3

2

1

0

Reserved

Polarity

Reserved

Polarity: Interrupt terminal polarity

0 = Active high (default)

1 = Active low

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3

Electrical Specifications

3.1 Absolute Maximum Ratings^†

Supply voltage range: IOV to I/O GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V

DD

DV to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 2 V

DD

A33VDD (see Note 1) to A18GND (see Note 2) . . . . . . . . . . . . . . . . −0.3 V to 3.6 V

A18VDD (see Note 3) to A33GND (see Note 4) . . . . . . . . . . . . . . . . . . −0.2 V to 2 V

Digital input voltage, V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V

I

Digital output voltage, V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V

O

Analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 2 V

Operating free-air temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

Storage temperature, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. CH1_A33VDD, CH2_A33VDD, CH3_A33VDD, CH4_A33VDD

2. CH1_A33GND, CH2_A33GND, CH3_A33GND, CH4_A33GND

3. CH1_A18VDD, CH2_A18VDD, CH3_A18VDD, CH4_A18VDD, A18VDD_REF, PLL_A18VDD

4. CH1_A18GND, CH2_A18GND, CH3_A18GND, CH4_A18GND

3.2 Recommended Operating Conditions

MIN NOM

MAX

UNIT

IOV

Digital supply voltage

3

1.65

3

3.3

1.8

3.3

1.8

1

3.6

1.95

3.6

V

DD

DV

Digital supply voltage

DD

AV

Analog supply voltage

V

DD33

DD18

Analog supply voltage

1.65

0.5

1.95

2

V

Analog input voltage (ac-coupling necessary)

Digital input voltage high (Note 1)

Digital input voltage low (Note 2)

V

I(P-P)

0.7 IOV

V

IH

IL

DD

0.3 IOV

V

DD

I

Output current, V = 2.4 V

−4

6

−8

8

mA

°C

OH

OL

out

Output current, V = 0.4 V

out

T

Operating free-air temperature

0

70

A

NOTES: 1. Exception: 0.7 AV

2. Exception: 0.3 AV

for XTAL1 terminal

DD18

3.2.1 Crystal Specifications

CRYSTAL SPECIFICATIONS

MIN

NOM

14.31818

MAX

UNIT

MHz

ppm

Frequency

Frequency tolerance

50

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SLES084C − August 2007

TVP5146

3.3 Electrical Characteristics

For minimum/maximum values: IOV_DD= 3.0 V to 3.6 V, DV_DD= 1.65 V to 1.95 V, AV_DD33= 3.0

V to 3.6 V, AV_DD18= 1.65 V to 1.95 V, T_A= 0°C to 70°C

For typical values: IOV_DD= 3.3 V, DV_DD= 1.8 V, AV_DD33= 3.3 V, AV_DD18= 1.8 V, T_A= 25°C

3.3.1 DC Electrical Characteristics

PARAMETER

TEST CONDITIONS

CVBS

MIN

TYP

6

MAX

UNIT

I

3.3-V IO digital supply current

mA

DDIO(D)

RGB and CVBS

CVBS

6

66.2

67

1.8-V digital supply current

mA

mW

DD(D)

RGB and CVBS

CVBS

16

3.3-V analog supply current

DD33(A)

DD18(A)

RGB and CVBS

CVBS

47.8

79.3

240

334.5

730

100

11

1.8-V analog supply current

RGB and CVBS

CVBS

P

TOT

Total power dissipation (normal operation)

RGB and CVBS

P

I

Total power dissipation (power save)

Total power dissipation (power down)

Input leakage current

mW

µA

pF

V

SAVE

DOWN

10

8

lkg

C

Input capacitance

By design

i

V

OH

V

OL

Output voltage high

0.8 IOV

DD

Output voltage low

0.2 IOV

V

DD

NOTE 1: Measured with a load of 10 kΩ in parallel to 15 pF.

3.3.2 Analog Processing and A/D Converters

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kΩ

Z

Input impedance, analog video inputs

Input capacitance, analog video inputs

Input voltage range

By design

200

i

C

10

2

pF

i

V

C

= 47 nF

coupling

0.50

−6

1

V

i(pp)

∆G

Gain control range

6

dB

DNL

INL

Fr

Differential nonlinearity

Integral nonlinearity

AFE only

0.75

1

1.0

2.5

LSB

dB

Frequency response

Crosstalk

Multiburst (60 IRE)

1 MHz

−0.9

XTALK

SNR

GM

NS

−50

dB

Signal-to-noise ratio, all channels

Gain match (Note 1)

Noise spectrum

1 MHz, 1.0 V

54

dB

P-P

Full scale, 1 MHz

1.1% 1.5%

Luma ramp (100 kHz to full, tilt-null)

Modulated ramp

−58

0.5

dB

DP

Differential phase

°

DG

Differential gain

Modulated ramp

1.5%

NOTE 1: Component inputs only

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3.3.3 Timing

3.3.3.1 Clocks, Video Data, Sync Timing

TEST CONDITIONS

(see Note 1)

PARAMETER

MIN

TYP

MAX

UNIT

Duty cycle DATACLK

45%

50%

18.5

55%

t

1

t

2

t

3

t

4

t

5

High time, DATACLK

Low time, DATACLK

Fall time, DATACLK

Rise time, DATACLK

Output delay time

ns

90% to 10%

10% to 90%

4

10

NOTE 1: C = 15 pF

L

t

2

t

1

V

OH

DATACLK

V

OL

t

4

3

V

OH

Y, C, AVID, VS, HS, FID

Valid Data

OL

t

5

Figure 3−1. Clocks, Video Data, and Sync Timing

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3.3.3.2 I²C Host Port Timing

PARAMETER

TEST CONDITIONS

MIN

1.3

0

TYP

MAX

UNIT

µs

t

Bus free time between STOP and START

1

2

3

4

5

6

7

8

Data hold time

0.9

µs

Data setup time

100

0.6

ns

Setup time for a (repeated) START condition

Setup time for a STOP condition

Hold time (repeated) START condition

Rise time VC1(SDA) and VC0(SCL) signal

Fall time VC1(SDA) and VC0(SCL) signal

Capacitive load for each bus line

µs

ns

µs

250

400

ns

C

pF

kHz

b

2

f

I C clock frequency

I2C

Stop Start

Stop

VC1 (SDA)

VC0 (SCL)

Data

t

1

t

6

t

3

t

6

t

5

2

t

4

t

7

t

8

Change

Data

2

Figure 3−2. I C Host Port Timing

88

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4

Example Register Settings

The following example register settings are provided only as a reference. These settings, given

the assumed input connector, video format, and output format, set up the TVP5146 decoder and

provide video output. Example register settings for other features and the VBI data processor

are not provided here.

4.1 Example 1

4.1.1 Assumptions

Input connector:

Video format:

Composite (VI_1_A) (default)

NTSC (J, M), PAL (B, G, H, I, N) or SECAM (default)

NOTE: NTSC-443, PAL-Nc, and PAL-M are masked from the autoswitch process by default.

See the autoswitch mask register at address 04h.

Output format:

10-bit ITU-R BT.656 with embedded syncs (default)

4.1.2 Recommended Settings

Recommended I²C writes: For the given assumptions, only one write is required. All other

registers are set up by default.

2

I C register address 08h = Luminance processing control 3 register

2

I C data 00h = Optimizes the trap filter selection for NTSC and PAL

2

I C register address 0Eh = Chrominance processing control 3 register

2

I C data 04h = Optimizes the chrominance filter selection for NTSC and PAL

2

I C register address 34h = Output formatter 2 register

2

I C data 11h = Enables YCbCr output and the clock output

NOTE: HS/CS, VS/VBLK, AVID, FID, and GLCO are logic inputs by default. See output

formatter 3 and 4 registers at addresses 35h and 36h, respectively.

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4.2 Example 2

4.2.1 Assumptions

Input connector:

Video format:

S-video [VI_2_C (luma), VI_1_C (chroma)]

NTSC (J, M, 443), PAL (B, G, H, I, M, N, Nc) and SECAM

10-bit 4:2:2 YCbCr with discrete sync outputs

Output format:

4.2.2 Recommended Settings

Recommended I²C writes: This setup requires additional writes to output the discrete sync 10-bit

4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above.

2

I C register address 00h = Input select register

2

I C data 46h = Sets luma to VI_2_C and chroma to VI_1_C

2

I C register address 04h = Autoswitch mask register

2

I C data 3Fh = Includes NTSC 443 and PAL (M, Nc) in the autoswitch

2

I C register address 08h = Luminance processing control 3 register

2

I C data 00h = Optimizes the trap filter selection for NTSC and PAL

2

I C register address 0Eh = Chrominance processing control 2 register

2

I C data 04h = Optimizes the chrominance filter selection for NTSC and PAL

2

I C register address 33h = Output formatter 1 register

2

I C data 43h = Selects the 10-bit 4:2:2 output format

2

I C register address 34h = Output formatter 2 register

2

I C data 11h = Enables YCbCr output and the clock output

2

I C register address 36h = Output formatter 4 register

2

I C data AFh = Enables HS and VS sync outputs

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4.3 Example 3

4.3.1 Assumptions

Input connector:

Video format:

Component [VI_1_B (Pb), VI_2_B (Y), VI_3_B (Pr)]

NTSC (J, M, 443), PAL (B, G, H, I, M, N, Nc) and SECAM

20-bit 4:2:2 YCbCr with discrete sync outputs

Output format:

4.3.2 Recommended Settings

Recommended I²C writes: This setup requires additional writes to output the discrete sync 20-bit

4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above.

2

I C register address 00h = Input select register

2

I C data 95h = Sets Pb to VI_1_B, Y to VI_2_B, and Pr to VI_3_B

2

I C register address 04h = Autoswitch mask register

2

I C data 3Fh = Includes NTSC 443 and PAL (M, Nc) in the autoswitch

2

I C register address 08h = Luminance processing control 3 register

2

I C data 00h = Optimizes the trap filter selection for NTSC and PAL

2

I C register address 0Eh = Chrominance processing control 2 register

2

I C data 04h = Optimizes the chrominance filter selection for NTSC and PAL

2

I C register address 33h = Output formatter 1 register

2

I C data 41h = Selects the 20-bit 4:2:2 output format

2

I C register address 34h = Output formatter 2 register

2

I C data 11h = Enables YCbCr output and the clock output

2

I C register address 36h = Output formatter 4 register

2

I C data AFh = Enables HS and VS sync outputs

91

SLES084C − August 2007

TVP5146

92

TVP5146

SLES084C − August 2007

5

Application Information

5.1 Application Example

XTAL1

C_0

FID

XTAL2

C_1

C_2

VS/VBLK

HS/CS

2.2 kΩ

14.31818 MHz

A3.3VDD

IOVDD3.3V

DVDD1.8V

C_3

C_4

C_5

XTAL1

XTAL2

CL2

CL1

A1.8VDD

0.1 µF (2)

0.1 µF (3)

VI_1A

VI_1B

VI_1C

1

60

59

58

57

56

55

C_6

VI_1_B

VI_1_C

C_6/RED

2

C_7/GREEN

C_8/BLUE

C_9/FSO

DGND

C_7

C_8

C_9

3

4

5

6

7

8

9

CH1_A33GND

CH1_A33VDD

CH2_A33VDD

CH2_A33GND

VI_2_A

VI_2_B

VI_2_C

CH2_A18GND

75 Ω (3)

0.1 µF (2)

0.1 µF (3)

DVDD

Y_0

Y_1

Y_2

Y_3

54

53

52

51

50

49

48

47

46

45

44

43

42

41

VI_2A

0.1 µF

Y_0

Y_1

Y_2

Y_3

Y_4

VI_2B

VI_2C

10

11

12

13

14

15

16

17

18

19

20

75 Ω (3)

TVP5146PFP

CH2_A18VDD

A18VDD_REF

A18GND_REF

CH3_A18VDD

CH3_A18GND

VI_3_A

Y_4

IOGND

IOVDD

0.1 µF (3)

0.1 µF

Y_5

Y_6

Y_7

Y_8

Y_5

Y_6

Y_7

Y_8

Y_9

VI_3A

VI_3B

VI_3C

VI_3_B

VI_3_C

Y_9

CH3_A33GND

CH3_A33VDD

DGND

DVDD

0.1 µF (3)

0.1 µF

75 Ω (3)

0.1 µF

VI_4A

2.2 kΩ (2)

75 Ω

IOVDD

0.1 µF

DATACLK

GLCO/I2CA

0.1 µF

GND

0.1 µF

AVID

FSS

RESETB

PWDN

10 kΩ

I2C Address selection

1−2 Base Addr. 0xBA

2−3 Base Addr. 0xB8

GLCO/I2CA

1

3

2

INTREQ

SDA

10 kΩ

SCL

NOTE: If XTAL1 is connected to clock source, input voltage high must be 1.8 V.

Terminals 69 and 71 must be connected to ground through pulldown resistors.

Figure 5−1. Application Example

93

SLES084C − August 2007

TVP5146

5.2 Designing With PowerPADt Devices

The TVP5146 device is housed in a high-performance, thermally enhanced, 80-terminal

PowerPAD package (TI package designator: 80PFP). Use of the PowerPAD package does not

require any special considerations except to note that the thermal pad, which is an exposed die

pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not

implementing the PowerPAD PCB features, the use of solder masks (or other assembly

techniques) may be required to prevent any inadvertent shorting by the exposed thermal pad of

connection etches or vias under the package. The recommended option, however, is not to run

any etches or signal vias under the device, but to have only a grounded thermal land as

explained in the following paragraphs. Although the actual size of the exposed die pad may vary,

the minimum size required for the keep-out area for the 80-terminal PFP PowerPAD package is

8 mm × 8 mm.

It is recommended that there be a thermal land, which is an area of solder-tinned copper,

underneath the PowerPAD package. The thermal land varies in size, depending on the

PowerPAD package being used, the PCB construction, and the amount of heat that needs to be

removed. In addition, the thermal land may or may not contain numerous thermal vias

depending on PCB construction.

Other requirements for using thermal lands and thermal vias are detailed in the PowerPADt

Thermally Enhanced Package technical brief, TI literature number SLMA002, available via the TI

Web pages at URL http://www.ti.com.

For the TVP5146 device, this thermal land must be grounded to the low-impedance ground

plane of the device. This improves not only thermal performance but also the electrical

grounding of the device. It is also recommended that the device ground terminal landing pads be

connected directly to the grounded thermal land. The land size must be as large as possible

without shorting device signal terminals. The thermal land may be soldered to the exposed

thermal pad using standard reflow soldering techniques.

While the thermal land may be electrically floated and configured to remove heat to an external

heat sink, it is recommended that the thermal land be connected to the low impedance ground

plane for the device. More information can be obtained from the TI Recommendations for PHY

Layout applicaton report, TI literature number SLLA020.

PowerPAD is a trademark of Texas Instruments.

94

TVP5146

SLES084C − August 2007

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TVP5146PFPR

HTQFP

PFP

80

1000

330.0

24.4

15.0

1.5

20.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTQFP PFP 80

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 45.0

TVP5146PFPR

1000

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Audio

Applications

www.ti.com/audio

amplifier.ti.com

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www.dlp.com

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DLP® Products

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www.ti.com/clocks

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www.ti.com/security

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power.ti.com

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TVP5146_12
厂家：	TEXAS INSTRUMENTS
描述：	NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovisionï£ª Detection, YPbPr/RGB Inputs, 5-Line Comb Filter, and SCART Support NTSC / PAL / SECAM 4×10位数字视频解码器， Macrovisionï英镑ª检测，频YPbPr / RGB输入， 5线梳状滤波器和SCART支持解码器
文件：	总109页 (文件大小：1805K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TVP5146_12 [TI]

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