TVP9900PFPR [TI]
VSB/QAM Receiver; VSB / QAM接收器
| 型号： | TVP9900PFPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | VSB/QAM Receiver |
| 文件： | 总65页 (文件大小：907K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVP9900
VSB/QAM Receiver
Data Manual
Literature Number: SLEA064
March 2007
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TVP9900
VSB/QAM Receiver
www.ti.com
SLEA064–MARCH 2007
Contents
1
Introduction......................................................................................................................... 7
1.1
Features....................................................................................................................... 7
1.2
Ordering Information ........................................................................................................ 7
2
3
Block Diagram ..................................................................................................................... 8
Terminal Assignments.......................................................................................................... 9
3.1
Pinout.......................................................................................................................... 9
3.2
Terminal Functions......................................................................................................... 10
4
Functional Description........................................................................................................ 12
4.1
4.2
4.3
4.4
4.5
Analog Front End........................................................................................................... 12
VSB/QAM Demodulator ................................................................................................... 12
Forward Error Correction.................................................................................................. 12
Output Formatter ........................................................................................................... 13
I2C Host Interface .......................................................................................................... 14
4.5.1
I 2C Write Operation............................................................................................. 15
4.5.2
I2C Read Operation ............................................................................................. 16
4.6
4.7
Tuner Control Interface.................................................................................................... 17
4.6.1
Tuner Write Operation .......................................................................................... 18
Tuner Read Operation .......................................................................................... 18
4.6.2
Antenna Control Interface................................................................................................. 19
4.7.1
4.7.2
4.7.3
Antenna Interrogation/Initialization ............................................................................ 20
Transmit Data to Antenna Operation ......................................................................... 21
Receive Data from Antenna Operation ....................................................................... 21
4.8
4.9
General-Purpose IO (GPIO) .............................................................................................. 21
Clock Circuits ............................................................................................................... 22
4.10 Power-Up Sequence....................................................................................................... 22
4.11 Reset......................................................................................................................... 22
4.12 Power Down ................................................................................................................ 23
4.13 Power-Supply Voltage Requirements ................................................................................... 23
High-K PCB Design Recommendations................................................................................. 24
Host Processor I2C Register Summary.................................................................................. 25
5
6
6.1
Overview..................................................................................................................... 25
6.2
I2C Register Definitions.................................................................................................... 27
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Receiver Control Register 1 / Soft Reset..................................................................... 27
Receiver Control Register 2.................................................................................... 28
VSB Control Register ........................................................................................... 28
AGC Control Register........................................................................................... 29
VSB FEC Time Counter Register 1 ........................................................................... 29
VSB FEC Time Counter Register 2 ........................................................................... 30
VSB FEC Time Counter Register 3 ........................................................................... 30
QAM FEC Time Counter Register 1 .......................................................................... 31
QAM FEC Time Counter Register 2 .......................................................................... 31
6.2.10 QAM FEC Time Counter Register 3 .......................................................................... 31
6.2.11 VSB FEC Segment Error Count Threshold Register 1 ..................................................... 32
6.2.12 VSB FEC Segment Error Count Threshold Register 2 ..................................................... 32
6.2.13 Update Status Control Register ............................................................................... 32
6.2.14 Receiver Status Register ....................................................................................... 33
6.2.15 AGC Status Register 1.......................................................................................... 33
6.2.16 AGC Status Register 2.......................................................................................... 33
6.2.17 AGC Status Register 3.......................................................................................... 34
6.2.18 NTSC Rejection Filter Status Register ....................................................................... 34
2
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6.2.19 Timing Recovery Status Register 1 ........................................................................... 34
6.2.20 Timing Recovery Status Register 2 ........................................................................... 34
6.2.21 Timing Recovery Status Register 3 ........................................................................... 35
6.2.22 Timing Recovery Status Register 4 ........................................................................... 35
6.2.23 Timing Recovery Status Register 5 ........................................................................... 35
6.2.24 Timing Recovery Status Register 6 ........................................................................... 35
6.2.25 Pilot Tracking Status Register 1 ............................................................................... 36
6.2.26 Pilot Tracking Status Register 2 ............................................................................... 36
6.2.27 Pilot Tracking Status Register 3 ............................................................................... 36
6.2.28 Carrier Recovery Status Register 1........................................................................... 36
6.2.29 Carrier Recovery Status Register 2........................................................................... 37
6.2.30 Carrier Recovery Status Register 3........................................................................... 37
6.2.31 Carrier Recovery Status Register 4........................................................................... 37
6.2.32 Carrier Recovery Status Register 5........................................................................... 37
6.2.33 Carrier Recovery Status Register 6........................................................................... 38
6.2.34 FEC Status Register 1 .......................................................................................... 38
6.2.35 FEC Status Register 2 .......................................................................................... 39
6.2.36 FEC Status Register 3 .......................................................................................... 39
6.2.37 FEC Status Register 4 .......................................................................................... 39
6.2.38 GPIO Alternate Function Select Register .................................................................... 40
6.2.39 GPIO Output Data Register .................................................................................... 40
6.2.40 GPIO Output Enable Register ................................................................................. 41
6.2.41 GPIO Input Data Register ...................................................................................... 41
6.2.42 MPEG Interface Output Enable Register 1 .................................................................. 42
6.2.43 MPEG Interface Output Enable Register 2 .................................................................. 43
6.2.44 Tuner Control Interface – I2C Slave Device Address Register ............................................ 43
6.2.45 Tuner Control Interface – Data Register 1 Through 8 ...................................................... 43
6.2.46 Tuner Control Interface – Control and Status Register..................................................... 44
6.2.47 Antenna Control Interface – Control and Status Register.................................................. 44
6.2.48 Antenna Control Interface – Transmit Data Register 1..................................................... 45
6.2.49 Antenna Control Interface – Transmit Data Register 2..................................................... 45
6.2.50 Antenna Control Interface – Receive Data Register 1...................................................... 45
6.2.51 Antenna Control Interface – Receive Data Register 2...................................................... 46
6.2.52 Firmware ID – ROM Version Register ........................................................................ 46
6.2.53 Firmware ID – RAM Major Version Register................................................................. 46
6.2.54 Firmware ID – RAM Minor Version Register................................................................. 46
6.2.55 Device ID LSB Register ........................................................................................ 47
6.2.56 Device ID MSB Register........................................................................................ 47
6.2.57 Miscellaneous Control Register................................................................................ 47
6.2.58 Software Interrupt Raw Status Register ...................................................................... 48
6.2.59 Software Interrupt Status Register ............................................................................ 48
6.2.60 Software Interrupt Mask Register ............................................................................. 49
6.2.61 Software Interrupt Clear Register ............................................................................. 50
7
Electrical Specifications...................................................................................................... 51
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings............................................................................................... 51
Recommended Operating Conditions ................................................................................... 52
DC Electrical Characteristics ............................................................................................. 52
Analog Input Characteristics.............................................................................................. 53
Timing Characteristics ..................................................................................................... 54
7.5.1
7.5.2
7.5.3
Crystal and Input Clock......................................................................................... 54
Device Reset..................................................................................................... 54
MPEG Interface.................................................................................................. 55
7.5.3.1 Parallel Mode (Data Only)...................................................................................... 55
Contents
3
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VSB/QAM Receiver
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7.5.3.2 Serial Mode (Data Only)........................................................................................ 56
7.5.3.3 Parallel Mode (Data With Redundancy)...................................................................... 57
7.5.3.4 Serial Mode (Data With Redundancy) ........................................................................ 58
7.5.4
Host and Tuner I2C Interface .................................................................................. 59
8
Application Circuit.............................................................................................................. 60
4
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List of Figures
2-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
TVP9900 Block Diagram .......................................................................................................... 8
Parallel Transport Stream Timing Diagram (Data Only) ..................................................................... 13
Serial Transport Stream Timing Diagram (Data Only) ....................................................................... 13
Parallel Transport Stream Timing Diagram (Data + Redundancy) ......................................................... 14
Serial Transport Stream Timing Diagram (Data + Redundancy) ........................................................... 14
Tuner Control Interface System ................................................................................................. 17
Antenna Control Interface System.............................................................................................. 19
25-MHz Crystal Oscillation....................................................................................................... 22
4-MHz Clock Input ................................................................................................................ 22
Thermal Land Size and Via Array............................................................................................... 24
Crystal or Clock Timing Waveform ............................................................................................. 54
Device Reset Signal Timing Waveforms....................................................................................... 54
MPEG Interface – Parallel Mode (Data Only) Timing Waveforms.......................................................... 55
MPEG Interface – Serial Mode (Data Only) Timing Waveforms............................................................ 56
MPEG Interface – Parallel Mode (Data With Redundancy) Timing Waveforms.......................................... 57
MPEG Interface – Serial Mode (Data with Redundancy) Timing Waveforms............................................. 58
I2C SCL and SDA Timing Waveforms.......................................................................................... 59
I2C Start and Stop Conditions Timing Waveforms............................................................................ 59
List of Figures
5
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VSB/QAM Receiver
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List of Tables
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
6-1
7-1
7-2
7-3
7-4
7-5
7-6
7-7
Terminal Functions................................................................................................................ 10
MPEG-2 Transport Stream Interface ........................................................................................... 13
MPEG-2 Transport Stream Output Clock Frequency ........................................................................ 14
I2C Terminal Description ......................................................................................................... 15
I2C Host Interface Device Write Addresses.................................................................................... 15
I2C Host Interface Device Read Address ...................................................................................... 16
Tuner Control Interface Registers............................................................................................... 17
Antenna Control Interface Registers............................................................................................ 19
Antenna Control Interface Pins.................................................................................................. 20
I2C Host Interface Registers ..................................................................................................... 25
Crystal and Input Clock Timing.................................................................................................. 54
Device Reset Timing.............................................................................................................. 54
Parallel Mode (Data Only) Timing .............................................................................................. 55
Serial Mode (Data Only) Timing................................................................................................. 56
Parallel Mode (Data With Redundancy) Timing............................................................................... 57
Serial Mode (Data With Redundancy) Timing................................................................................. 58
Host and Tuner I 2C Interface Timing .......................................................................................... 59
6
List of Tables
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VSB/QAM Receiver
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1
Introduction
The TVP9900 is a cost-effective digital TV (DTV) front-end IC targeted for low-cost high-volume DTV
receivers. The TVP9900 is a system-on-chip (SoC) device that integrates the main functions of a DTV
front-end system, including programmable gain amplifier (PGA), A/D converter, VSB demodulator, ATSC
forward error correction (FEC), QAM demodulator, and ITU-T Annex B FEC. It provides rich peripheral
support including AGC control, tuner control, CEA-909 antenna control, and host I2C interface. The
TVP9900 supports processing of ATSC VSB or ITU-T Annex B QAM IF inputs.
1.1 Features
•
Host Interrupt for Remote Monitoring of Signal
Quality
•
•
ATSC 8-VSB Demodulation and FEC
ITU-J.83B Compliant 64/256 QAM
Demodulation and FEC
•
•
•
•
SNR Monitor
BER Monitor
•
Direct 44-MHz IF Sampling Eliminates Need for
External Downconverter
Integrated De-Interleaver RAM
•
•
•
Integrated IF PGA
Parallel/Serial MPEG Output Interface With
Error Packet Indicator
Integrated High-Speed 10-bit A/D Converter
•
•
•
Direct Tuner Control Interface
Integrated Digital Filter Relaxes External Tuner
Filters
EIA/CEA-909 Antenna Control Interface
•
•
•
•
•
Sigma-Delta DAC for AGC Control
Adjacent Channel Filter
Option for 4-MHz Clock Input Driven by MOP
IC in Tuner, So No Quartz Crystal Required for
Demodulator
NTSC Co-Channel Rejection Filter
All Digital Timing Recovery
•
•
•
External DAC and VCXO for Clock Recovery
Not Required
Pilot Tracking Loop With Lock Status Indicator
Signal
Equalizer Covers Echo Profile Required by
ATSC A.74 Guideline
•
•
Decision-Directed Carrier Phase Tracking
Loop
Superior Multipath Performance Demodulating
for Brazil Ensembles A Through E
Field and Segment Synchronization With Sync
Status Indicator Signal
•
•
Power-Down Mode
80-Pin TQFP Package
1.2 Ordering Information(1)
PACKAGED DEVICES
80-Pin TQFP-PowerPAD
TVP9900PFP
TA
PACKAGE OPTION
Tray
0°C to 70°C
TVP9900PFPR
Tape and Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TVP9900
VSB/QAM Receiver
www.ti.com
SLEA064–MARCH 2007
2
Block Diagram
ATSC FEC
DCLK
BYTE_START
PACCLK
AIFIN_P
Output
VSB/QAM
AFE
AIFIN_N
Formatter
Demodulator
DATAOUT[7:0]
DERROR
ITU-T J.83
AGCOUT
Annex B FEC
INTREQ
VBUS
TUNSDA
TUNSCL
Tuner
Interface
MCU
CEA-909
Interface
ANTCNTLIO
GPIO [7:0]
ROM
RAM
Interrupt Ctrl
JTAG
GPIO
I2CSDA
I2CSCL
Host
Interface
PLL
Interface
Figure 2-1. TVP9900 Block Diagram
8
Block Diagram
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3
Terminal Assignments
3.1 Pinout
DATAOUT0
DATAOUT1
DVDD_1_5
DGND
DATAOUT2
DATAOUT3
DATAOUT4
IOVDD_3_3
IOGND
DATAOUT5
DATAOUT6
DATAOUT7/SERDATA0
DVDD_1_5
DGND
AGND
AVDD_3_3
AIFIN_P
AIFIN_N
AVDD_3_3
AGND
AVDD_1_5
AGND
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AGND_PLL
AVDD_PLL_1_5
XTALOUT
XTALREF
XTALIN
9
TVP9900
80-Pin TQFP
(Top View)
10
11
12
13
14
15
16
17
18
19
20
CLKIN
DIVINSEL
CLKOUT
DGND
DVDD_1_5
PACCLK
BYTESTART
IOVDD_3_3
IOGND
DCLK
DGND
IOGND
IOVDD_3_3
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3.2 Terminal Functions
Table 3-1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
IF INTERFACE
AIFIN_P
3
4
I
I
Analog positive differential IF input
Analog negative differential IF input
AIFIN_N
TRANSPORT STREAM INTERFACE
DCLK
42
O
O
MPEG-2 data clock output
MPEG-2 Byte Start signal. An active high output signal that indicates the first byte of a
transport stream data packet.
BYTE_START
45
MPEG-2 interface packet framing signal. An active high output signal that remains high
for the entire length of the valid data packet.
PACCLK
46
40
49
O
O
O
MPEG-2 interface data error. An active high output signal that indicates an error in the
data output packet. Indicates an error in the input data. This pin should be tied low if not
in use.
DERROR
1. MPEG-2 parallel data output. Bit 7 is the first bit of the transport stream.
2. MPEG-2 serial data output
DATAOUT7/SERDATA0
50, 51,
54, 55,
56, 59,
60
DATAOUT[6:0]
O
MPEG-2 parallel data output bits 6-0.
CLOCK SIGNALS
Crystal input. Input to the on-chip oscillator from an external crystal. The required crystal
frequency is 25 MHz. This input can also be driven by an external clock source instead of
a crystal. When using an external clock source, a 4 MHz or 25 MHz clock must be used.
NOTE: If an external clock source is used, the input can only be used with 1.5-V signal
levels.
XTALIN
13
I
XTALOUT
XTALREF
CLKIN
11
12
14
O
I
Crystal output. Output from the on-chip oscillator to an external crystal.
External crystal reference. This pin is used for the external crystal capacitor ground
reference.
I
Test clock input. For normal operation, this input should be tied low.
PLL VCO divider default input select. This input is used to select the default VCO divider
value for the PLL. If a 25-MHz crystal or clock is used for XTALIN, then DIVINSEL should
be driven low. If a 4-MHz crystal or clock is used for XTALIN, then DIVINSEL should be
driven high.
DIVINSEL
CLKOUT
15
16
I
O
Test clock output. For normal operation, this output is not used.
MISCELLANEOUS SIGNALS
AGCOUT
28
29
30
31
O
AGC control Delta-Sigma DAC output.
ANTCNTLIO
I/O
I/O
I/O
Smart antenna control interface input/output.
TUNSDA
Tuner I2C serial data input/output. NOTE: The output functions as an open-drain.
Tuner I2C serial clock. NOTE: The output functions as an open-drain.
TUNSCL
1. General purpose I/O
2. Interrupt request output
GPIO7/INTREQ
GPIO6
61
62
65
I/O
I/O
I/O
I/O
1. General purpose I/O
2. Reserved
1. General purpose I/O
2. Sync output
GPIO5/SYNCOUT
66, 67,
70
GPIO[4:2]
GPIO1
General purpose I/O
Dedicated to Smart Antenna support. Outputs direction of signal on pin 29 in Smart
Antenna 1-pin mode.
0 = Signal input from antenna to TVP9900, pin 29
1 = Signal output from TVP9900 pin 29 to antenna
71
O
10
Terminal Assignments
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Table 3-1. Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1. General purpose I/O
2. Antenna Control Input
GPIO0/ANTCNTLIN
72
I/O
System reset. An active-low asynchronous input that initializes the device to the default
state.
RESETZ
21
39
I
I
I
PWRDOWN
TMSEL[3:0]
Power down terminal. An active high signal puts the device in a low power state.
22, 23,
26, 27
Test mode select. Tie low for normal operation.
HOST INTERFACE
I2CSDA
I2CSCL
34
35
I/O
I/O
Host I2C serial data input/output. NOTE: The pin functions as an open-drain output.
Host I2C serial clock. NOTE: The pin functions as an open-drain output.
Host I2C device address select. Determines address for I2C (sampled during reset). A
pullup or pulldown 10-kΩ resistor is needed to program the terminal to the desired
address.
I2CA0
38
I
0 = Address is 0xB8h
1 = Address is 0xBAh
POWER SUPPLIES
18, 25,
37, 48,
58, 68,
73
DVDD_1_5
P
P
Digital power supply. Connect to 1.5-V digital supply.
Digital power supply return. Connect to digital ground.
17, 24,
36, 41,
47, 57,
69, 74
DGND
20, 33,
44, 53,
64
IOVDD_3_3
IOGND
P
P
IO power supply. Connect to 3.3-V digital supply.
IO power supply return. Connect to digital ground.
19, 32,
43, 52,
63
AVDD_3_3
AVDD_1_5
2, 5
7
P
P
Analog power supply. Connect to 3.3-V analog supply.
Analog power supply. Connect to 1.5-V analog supply.
1, 6, 8,
75
AGND
P
Analog power supply return. Connect to analog ground.
AVDD_PLL_1_5
AGND_PLL
NSUB
10
9
P
P
P
P
P
O
O
PLL power supply. Connect to 1.5-V analog supply.
PLL power supply return. Connect to analog ground.
Die substrate. Connect to PCB ground.
80
77
76
79
78
AVDD_REF_3_3
AGND_REF
BGREFCAP
BIASRES
Analog reference power supply. Connect to 3.3-V analog supply.
Analog reference ground. Connect to analog ground.
Band-gap reference capacitor connection
Analog bias register. Connect through a 24-kΩ resistor to PCB ground.
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4
Functional Description
4.1 Analog Front End
The TVP9900 receiver has an analog input channel that accepts one differential or single-ended 44-MHz
center frequency IF input, which are ac-coupled. The receiver supports a maximum input differential
voltage range of 1 Vpp with PGA setting at unity gain. The programmable gain amplifier (PGA) and the
AGC circuit work together and ensure that the input signal is amplified sufficiently to ensure the proper
input range for the ADC. The ADC has 10 bits of resolution. The clock input for the ADC comes from the
PLL. An external downconverter is not required to use this IF direct sampling method. The analog front
end and adjacent digital filter can potentially relax the requirement for external analog filters, and only one
external SAW filter is required.
4.2 VSB/QAM Demodulator
The VSB/QAM demodulator is designed for 8-VSB demodulation compliant with ATSC, and 64/256 QAM
demodulation compliant with ITU-T J83 Annex B. The VSB/QAM demodulator in the TVP9900 is
composed of the following blocks:
•
•
•
•
•
•
•
•
Automatic gain control
Adjacent channel filter
NTSC rejection filter
Timing recovery
Pilot tracking
Matched filter
Decision feedback equalizer
Carrier recovery
The all-digital demodulator architecture does not require an external downconverter, AGC control DAC,
clock recovery VCXO, or carrier recovery VCXO. This architecture makes a low-cost system
implementation possible.
4.3 Forward Error Correction
Forward Error Correction (FEC) in the TVP9000 includes the following blocks:
•
QAM FEC
–
–
–
–
–
–
Trellis decoder
Synchronizer
De-randomizer
De-interleaver
Reed Solomon decoder
MPEG deframer
•
VSB FEC
–
–
–
–
–
Trellis decoder
Synchronizer
De-interleaver
Reed Solomon decoder
De-randomizer
The Trellis decoder is designed for help protect against short-burst interference. The VSB synchronizer
performs segment and frame synchronization and outputs the synchronization signal with data. An internal
RAM is shared by both VSB and QAM modes, and additional external RAM is not required.
12
Functional Description
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4.4 Output Formatter
The TVP9900 transport stream interfaces directly to the back-end IC, which provides transport stream
compliance with ISO/IEC 13818-1 in parallel or serial modes. The details of the transport stream interface
are shown in Table 4-1. In serial mode, DATAOUT[7] is used as the serial data output, with the MSB
output first. The maximum output rate is 42.1 Mbit/s in serial mode. The polarity of DCLK, BYTE_START,
DERROR, and PACCLK is programmable.
Table 4-1. MPEG-2 Transport Stream Interface
TERMINAL
DCLK
TYPE
DESCRIPTION
O
Parallel/serial clock output
Parallel/serial data output
DATAOUT[7:0]
O
DATAOUT7 is the first bit of the transport stream in parallel mode.
DATAOUT7 is the serial data output in serial mode.
BYTE_START
PACCLK
O
O
Packet sync, indicates the start byte of a transport packet
Packet enable, indicates the valid packet data
Figure 4-1 and Figure 4-2 show the parallel and serial transport stream timing diagrams in data-only
mode. In data-only mode, 188 bytes of data is transferred from the transport stream interface
continuously. PACCLK is always kept high.
DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes
Figure 4-1. Parallel Transport Stream Timing Diagram (Data Only)
DCLK
1st byte
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
1
0
7
6
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes
Figure 4-2. Serial Transport Stream Timing Diagram (Data Only)
Figure 4-3 and Figure 4-4 show the parallel and serial transport stream timing diagrams in data and
redundancy mode. In data and redundancy mode, 188 bytes of data is transferred from the transport
stream interface with redundant data bytes. PACCLK only becomes high when the data is valid.
Redundancy data is 20 bytes in the ATSC standard and 16 bytes in ITU-T J.83 Annex B.
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DCLK
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes
Parity 16 or 20 bytes
Figure 4-3. Parallel Transport Stream Timing Diagram (Data + Redundancy)
DCLK
1st byte
7
6
5
4
3
2
1
0
7
6
1
0
7
6
1
0
7
6
5
DATAOUT[7:0]
BYTE_START
PACCLK
Data 188 bytes
Parity 16 or 20 bytes
Figure 4-4. Serial Transport Stream Timing Diagram (Data + Redundancy)
Table 4-2 shows the transport stream clock frequency in each mode.
Table 4-2. MPEG-2 Transport Stream Output Clock Frequency
DATA ONLY
DATA + REDUNDANCY
BIT RATE
(Mbps)
MODE
SERIAL CLOCK
PARALLEL CLOCK
(MHz)
SERIAL CLOCK
PARALLEL CLOCK
(MHz)
(MHz)
(MHz)
8VSB
64QAM
256QAM
19.39266
26.97035
38.81070
19.39266
26.97035
38.81070
2.42408
3.37129
4.85133
21.45571
29.26570
42.11374
2.68196
3.65821
5.26422
4.5 I2C Host Interface
Communication with the TVP9900 receiver is via an I2C host interface. The I2C standard consists of two
signals, the serial input/output data (I2CSDA) line and the input/output clock line (I2CSCL), which carry
information between the devices connected to the bus. A 1-bit control signal (I2CA0) is used for slave
address selection. Although an I2C system can be multi-mastered, the TVP9900 can function as a slave
device only. Since I2CSDA and I2CSCL are kept open-drain at logic high output level or when the bus is
not driven, the user should connect I2CSDA and I2CSCL to IOVDD_3.3 via a pullup resistor on the board.
At the trailing edge of reset, the status of the I2CA0 line is sampled to determine the device address used.
Table 4-3 summarizes the terminal functions of the I2C-mode host interface. Table 4-4 and Table 4-5
show the device address selection options.
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Table 4-3. I2C Terminal Description
SIGNAL
TYPE
I
DESCRIPTION
I2CA0
I2CSCL
I2CSDA
Slave address selection
Input/output clock line
Input/output data line
I/O (open drain)
I/O (open drain)
Table 4-4. I2C Host Interface Device Write Addresses
I2CA0
WRITE ADDRESS
0
1
B8h
BAh
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL, except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I2C stop condition.
Every byte placed on the SDA must be 8 bits long. The number of bytes that can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
4.5.1 I 2C Write Operation
Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to
the TVP9900 receiver by generating a start condition (S), followed by the TVP9900 I2C address (as shown
below), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge
from the TVP9900 receiver, the master presents the sub-address of the register or the first of a block of
registers it wants to write, followed by one or more bytes of data, MSB first. The TVP9900 receiver
acknowledges each byte after completion of each transfer. The I2C master terminates the write operation
by generating a stop condition (P).
Step 1
0
I2C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
0
Step 3
9
I2C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Write register address (master)
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Step 5
9
I2C Acknowledge (slave)
A
Step 6
7
6
5
4
3
2
1
0
I2C Write data (master)
Data
Data
Data
Data
Data
Data
Data
Data
(1)
9
Step 7
I2C Acknowledge (slave)
A
Step 8
0
I2C Stop (master)
P
(1) Repeat steps 6 and 7 until all data have been written.
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4.5.2 I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C
master initiates a write operation to the TVP9900 receiver by generating a start condition (S) followed by
the TVP9900 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving
acknowledges from the TVP9900 receiver, the master presents the sub-address of the register or the first
of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle
immediately by generating a stop condition (P).
Table 4-5. I2C Host Interface Device Read Address
I2CA0
READ ADDRESS
0
1
B8h
BAh
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the
TVP9900 receiver by generating a start condition, followed by the TVP9900 I2C address (as shown below
for a read operation), in MSB-first bit order, followed by a 1 to indicate a read cycle. After an acknowledge
from the TVP9900 receiver, the I2C master receives one or more bytes of data from the TVP9900
receiver. The I2C master acknowledges the transfer at the end of each byte. After the last data byte
desired has been transferred from the TVP9900 receiver to the master, the master generates a not
acknowledge, followed by a stop.
Read Phase 1
Step 1
0
I2C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
0
Step 3
9
I2C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Write register address (master)
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Step 5
9
I2C Acknowledge (slave)
A
Step 6
0
I2C Stop (master)
P
Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
0
Step 9
9
I2C Acknowledge (slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read data (slave)
Data
Data
Data
Data
Data
Data
Data
Data
(1)
9
Step 11
I2C Not Acknowledge (master)
A
Step 12
0
I2C Stop (master)
P
(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
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4.6 Tuner Control Interface
The TVP9900 has an I2C-compatible two-wire serial interface that can be used by the host processor for
tuner control. This dedicated tuner interface can be used by the host processor to transfer data to/from the
tuner in order to isolate the tuner from the main system I2C bus. As a result, noise coupling to the tuner
from host processor I2C bus transfers should be minimized.
The TVP9900 tuner control interface operates as an I2C bus master and supports both 100-kbps and
400-kbps data transfer rates. The mode and transfer rate is set in the Tuner Control Interface – Control
and Status Register (5Eh), bit 0. The device does not support a multi-master bus environment (bus
arbitration is not supported).
To transfer data to/from the tuner, the host processor first writes the transaction to a set of registers in the
TVP9900 via the host processor I2C interface. Then the TVP9900 internal MCU transfers the data to/from
the tuner via the tuner control interface.
TUNSCL and TUNSDA need to be pulled up to the 3.3-V supply (IOVDD) and not to a 5-V supply.
Figure 4-5 shows the block diagram of the tuner control interface system.
MCU
From
Tuner
Control
Interface
Host
I2C
To
Tuner
TUNSDA
TUNSCL
SDA
SCL
Host
Processor
Interface
Figure 4-5. Tuner Control Interface System
Table 4-6 lists the I2C registers and their functions used to control the tuner interface.
Table 4-6. Tuner Control Interface Registers
REGISTER
55h
FUNCTION
Tuner I2C slave address and R/W control
56h to 5Dh
5Eh
Data registers 1 through 8
Byte Count, Transaction Start, and I2C Mode
Software Interrupt Raw Status, Status, Mask, and Clear – Transaction Error
and Done Status
F9, FB, FD, FFh
When the TVP9900 tuner I2C interface is used, rather than controlling the tuner over the host processor
I2C bus interface, two status bits are provided in the TVP9900 to indicate a transaction error or the
completion of a successful transaction. The TCIERROR bit in the TVP9900 Software Interrupt Status
Register (FBh) gets set as a result of a transaction error. The TCIDONE bit in the same register gets set
at the end of a normal transaction; it does not get set for an abnormal transaction. The TVP9900 can be
configured so that setting the TCIERROR or TCODONE status bits can assert the INTREQ output of the
TVP9900; this requires the mask bits to be configured correctly in the TVP9900 Software Interrupt Mask
Register (FDh).
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If the host INTREQ is not used, the TCIDONE and TCIERROR interrupts should be masked and the host
should poll the TCIDONE status bit to determine when the transaction is complete, and the host should
poll the TCIERROR status bit to determine when an error has occurred.
Tuner data transfers occur utilizing the following illustrated formats.
4.6.1 Tuner Write Operation
The following steps are required to initiate a write operation to the tuner. The host processor first writes
the required transaction data to a set of registers in the TVP9900 via the host processor I2C interface.
Step 1
Set tuner I2C slave address (bits 7:1) and read/write control (bit 0 = 0)
Write data bytes to be sent to tuner; 56h is first byte sent
Register 55h
Step 2
Registers 56h to 5Dh
Step 3
Set byte count (bits 7:5) and I2C mode (bit 0)
Set bit 2 to 1 to start transaction to tuner
Register 5Eh
Step 4
Register FBh
Check state of bits 1:0 or INTREQ pin to verify successful transaction
After the transaction has been initiated, the TVP9900 internal MCU transfers the data to the tuner via the
tuner control interface. Acting as the I2C master, the TVP9900 initiates a write operation to the tuner (as
shown below), by generating a start condition, followed by the tuner I2C address, in MSB-first bit order,
followed by a 0 to indicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900
presents the sub-address of the register, if needed, followed by one or more bytes of data, MSB first. The
tuner acknowledges each byte after completion of each transfer. The TVP9900 terminates the write
operation by generating a stop condition.
TVP9900/Tuner Write Operation
Device
Address
Base
Address
SDA
Start
W
Ack
Ack
Data 1
Ack
...
Data N
Ack
Stop
4.6.2 Tuner Read Operation
The following steps are required to initiate a read operation from the tuner. The host processor first writes
the required transaction data to a set of registers in the TVP9900 via the host processor I2C interface,
then reads the data bytes received from the tuner stored in TVP9900 registers.
Step 1
Set tuner I2C slave address (bits 7:1) and read/write control (bit 0 = 1)
Register 55h
Step 2
Set byte count (bits 7:5) and I2C mode (bit 0)
Set bit 2 to 1 to start transaction to tuner
Register 5Eh
Step 3
Register FBh
Check state of bits 1:0 or INTREQ pin to verify successful transaction
Read data bytes from tuner; 56h is first byte received
Step 4
Registers 56h to 5Dh
After the transaction has been initiated, the TVP9900 internal MCU transfers the data from the tuner via
the tuner control interface. The read operation consists of two phases, as shown below. The first phase is
the address phase. In this phase, the TVP9900 I2C master initiates a write operation to the tuner by
generating a start condition, followed by the tuner I2C address, in MSB-first bit order, followed by a 0 to
indicate a write cycle. After receiving an acknowledge from the tuner, the TVP9900 presents the
sub-address of the register, if needed. After the cycle is acknowledged, the master terminates the cycle
immediately by generating a stop condition.
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The second phase is the data phase. In this phase, the TVP9900 I2C master initiates a read operation to
the tuner by generating a start condition, followed by the tuner I2C address, in MSB-first bit order, followed
by a 1 to indicate a read cycle. After an acknowledge from the tuner, the TVP9900 receives one or more
bytes of data from the tuner. The TVP9900 acknowledges the transfer at the end of each byte. After the
last data byte desired has been transferred from the tuner to the TVP9900, the TVP9900 generates a not
acknowledge, followed by a stop.
TVP9900/Tuner Set Start Address, Then Read Operation
Device
Address
Base
Address
SDA
SDA
Start
Start
W
R
Ack
Ack
Ack
Ack
Stop
...
Device
Address
Data 1
Data N
Ack
Stop
4.7 Antenna Control Interface
The TVP9900 has an antenna control interface compliant with EIA/CEA-909. The TVP9900 receives the
antenna parameters from the host processor via I2C, and sends a modulated PWM signal to the antenna.
The antenna parameters include antenna direction, antenna polarization, preamplifier gain and channel
number. This interface can be used to automatically optimize the signal by adjusting the antenna
configuration for the best possible reception.
Figure 4-6 shows the block diagram of the antenna control interface system.
Figure 4-6. Antenna Control Interface System
Table 4-7 lists the I2C registers and their functions used with the antenna control interface.
Table 4-7. Antenna Control Interface Registers
REGISTER
4Fh
FUNCTION
GPIO Alternate Function Select
5Fh
Antenna Control Interface – Control and Status
Antenna Control Interface – Transmit Data
Antenna Control Interface – Receive Data
60h to 61h
62h to 63h
Software Interrupt Raw Status, Status, Mask, and Clear – Transaction
Complete and Timeout Status
F9, FB, FD, FFh
The TVP9900 supports two modes of antenna control: Mode A for basic control (transmit transaction only)
and Mode B for advanced control (transmit and receive transactions) as defined in the CEA-909 standard.
For Mode B operation, the TVP9900 supports both 1-pin and 2-pin operation. In 1-pin mode, the data
input and output are muxed into one pin (pin 29), and in 2-pin mode the input and output use separate
pins (pin 29 for output, pin 72 for input.) The desired pin mode is selected by setting register 5Fh, bit 0.
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Table 4-8 lists the TVP9900 pins and their functions used with the antenna control interface.
Table 4-8. Antenna Control Interface Pins
PIN
29
NAME
ANTCNTLIO
FUNCTION
Antenna control interface input/output
71
GPIO1
Signal direction of pin 29 in 1-pin mode
Antenna control input for 2-pin mode
72
GPIO0/ANTCNTLIN
The GPIO1 pin provides dedicated smart antenna control support, and in 1-pin mode this pin outputs the
direction of the signal on pin 29:
GPIO1 = 0 indicates signal input from antenna to TVP9900 pin 29
GPIO1 = 1 indicates signal output from TVP9900 pin 29 to antenna
Four status bit are provided in the TVP9900 to indicate the completion of a successful receive or transmit
transaction, or if a transaction timeout has occurred.
•
•
•
The ACIRXCT bit in the TVP9900 Software Interrupt Status Register (FBh) gets set when the receive
transaction from a Mode B antenna is complete.
The ACITXCT bit in the same register gets set when the transmit transaction to the antenna is
complete.
The ACIRXTO bit in the same register gets set when an interface timeout has occurred due to no reply
form the antenna following a transmit transaction, or an incomplete receive transaction from the
antenna.
•
The RXERR bit in the Antenna Control Interface Control and Status Register (5Fh) is set if an
incomplete receive transaction occurs.
The TVP9900 can be configured so that setting the ACIRXCT, ACITXCT, or ACIRXTO status bits can
assert the INTREQ output of the TVP9900; this requires the mask bits to be configured correctly in the
TVP9900 Software Interrupt Mask Register (FDh).
If the host INTREQ is not used, the ACIRXCT, ACITXCT, and ACIRXTO interrupts should be masked and
the host should poll the ACIRXCT and ACITXCT status bits to determine when the transactions are
complete, and the host should poll the ACIRXTO and RXERR status bits to determine when a receive
timeout or error has occurred.
Antenna control data transfers occur utilizing the following illustrated formats.
4.7.1 Antenna Interrogation/Initialization
The following steps are required to interrogate and initialize a smart antenna. The host processor first
writes the required transaction data to a set of registers in the TVP9900 via the host processor I2C
interface.
1. The system host processor transmits to the antenna a basic Mode A 14-bit serial data stream with an
RF channel number of zero.
2. The system tri-states the line and waits 100 ms for a reply message from the antenna controller. If no
response is received, a timeout occurs, and the antenna controller is assumed to be a Mode A system.
The system uses only transmit operations for antenna control.
3. If the antenna responds with a 10-bit program identifier, the antenna controller is assumed to be a
Mode B system, and the system uses transmit and receive operations for antenna control.
This initialization is optional. If the system has only Mode A enabled, with no Mode B support, then this
initialization step may be omitted.
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4.7.2 Transmit Data to Antenna Operation
The following steps are required to transmit data to the antenna. The host processor writes the required
transaction data to a set of registers in the TVP9900, as described below, via the host processor I2C
interface.
Step 1
Set TXRXSEL (bit 2 = 1) to select a transmit data transaction, and set MODE (bit 4 = 1) to enable auto receive
Register 5Fh
mode
Step 2
Registers 60h to 61h
Load 14-bit data value to be transmitted to antenna
Step 3
Register 5Fh
Set TXSTART (bit 3) to 1 to start transmit transaction to tuner
Check state of bit 4 or INTREQ pin to verify successful transaction
Step 4
Register FBh
4.7.3 Receive Data from Antenna Operation
After an antenna transmit transaction is executed, a Mode B antenna should respond with a 10-bit data
value within 100 ms. If the receive data is not received within 100 ms, then a receive timeout occurs. The
following steps are required to receive data from the antenna. The host processor first writes the required
transaction data to a set of registers in the TVP9900, as described below, via the host processor I2C
interface, then reads the data bytes received from the antenna stored in TVP9900 registers.
Step 1
Set TXRXSEL (bit 2 = 0) to select a receive data transaction, and set MODE (bit 4 = 1) to enable auto receive
Register 5Fh
mode
Step 2
Register FBh
Check state of bit 5 or INTREQ pin to verify successful transaction, or wait for timeout interrupt (bit 3) to occur
Read 10-bit data value received from antenna
Step 3
Registers 62h to 63h
Step 4
Register 5Fh
Read RXERR value (bit 5)
The RXERR bit is set to 1 to indicate an error occurred when receiving data from a Mode B antenna. If a
non-zero data value was received from the antenna and no error occurred, then the data is valid and the
antenna is a Mode B antenna. If the data value is zero and no error occurred, then a receive transaction
did not occur and it is assumed that the antenna is a Mode A antenna.
4.8 General-Purpose IO (GPIO)
The TVP9900 has eight general-purpose IO pins, GPIO0–GPIO7. GPIO1 is a dedicated pin for Smart
Antenna support. GPIO0, GPIO5, GPIO6, and GPIO7 are shared pins and can be programmed as the
following dedicated functions. See register 4Fh description for details about selecting these alternate
functions. All pins are configured as inputs at device power-up.
•
•
•
•
GPIO0 – Antenna control input
GPIO5 – Sync output
GPIO6 – Reserved
GPIO7 – Interrupt request output
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4.9 Clock Circuits
An internal PLL generates all clocks required in the chip. A 25-MHz clock is required to derive the PLL.
Most tuner devices have a 4-MHz crystal oscillator that can be output to the demodulator as a clock
source. In the TVP9900, a 4-MHz clock input also can be used as the clock source. A 4-MHz clock is
input to the TVP9900 receiver on terminal 13 (XTALIN), or a crystal of 25-MHz fundamental resonant
frequency may be connected across terminals 13 (XTALIN) and 11 (XTALOUT). Figure 4-7 shows the
reference clock configuration of 25-MHz crystal oscillation. NOTE: The oscillator input, XTALIN, is not
3.3-V tolerant and only works at 1.5-V signal levels.
TVP9900
25 MHz
Crystal
XTALIN
XTALOUT
XTALREF
Figure 4-7. 25-MHz Crystal Oscillation
Figure 4-8 shows the reference clock configuration of 4-MHz clock input.
TVP9900
4 MHz
XTALIN
Clock
XTALOUT
Figure 4-8. 4-MHz Clock Input
4.10 Power-Up Sequence
No specific power-supply sequence is required, as long as all power supplies are ramped to valid
operating levels within 500 ms of one another. Output or bidirectional buffers power-up with the output
buffers in tri-state mode.
4.11 Reset
The reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device at
power-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of
1 ms after all power-supply voltages are stable at the recommended operating voltage. Internal circuits
synchronize the power-on reset with internal clocks; therefore, the RESETZ signal must remain active low
for a minimum of 1 µs after the crystal oscillator and clocks are stable.
Reset may be asserted any time after power up and stable crystal oscillation and must remain asserted for
at least 1 µs. A minimum of 200 µs must be allowed after reset before commencing I2C operations.
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4.12 Power Down
There is no required power-down sequence for the TVP9900.
4.13 Power-Supply Voltage Requirements
The digital core uses a 1.5-V power supply. The digital IO cells use a 3.3-V power supply. Note that the
exception is for the oscillator input, XTALIN, which is not 3.3-V tolerant and only works at 1.5-V signal
levels. The analog circuitry uses both a 1.5-V and a 3.3-V power supply.
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5
High-K PCB Design Recommendations
In order to effectively transfer heat out of the package and to keep the die junction temperature below
105°C, the TVP9900 is packaged in the thermal PowerPAD™ package, which has an exposed metal pad
on the bottom of the device. To effectively use this package, the following PCB design requirements must
be followed.
•
An array of thermal vias should be placed in the board at the placement location of the TVP9900, as
shown in Figure 5-1.
•
•
•
•
The ideal thermal land size is 10 mm × 10 mm, and the ideal thermal via pattern is a 6 × 6 array.
The vias should be connected to the PCB ground plane.
The exposed metal pad of the TVP9900 should be soldered to these vias.
The copper trace thickness should be 0.071 mm (2 oz), if possible.
1.4 mm
0.33 mm
10 mm
10 mm
10-mm × 10-mm thermal land size
6 × 6 array of vias
1.4-mm via spacing
0.33-mm via diameter
Figure 5-1. Thermal Land Size and Via Array
Each of these recommendations is important to maximize the heat-sinking characteristics of the PCB.
Refer to the Texas Instruments application report, PowerPAD™ Thermally Enhanced Package (literature
number SLMA002), for more detailed information.
24
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6
Host Processor I2C Register Summary
6.1 Overview
The TVP9900 IC is controlled by a host processor by using a set of control and status registers. Access to
these registers by the host processor is via an I2C serial interface. A summary of the I2C host interface
registers is given in Table 6-1.
Table 6-1. I2C Host Interface Registers
ADDRESS
00h
REGISTER NAME
Receiver Control Register 1 / Soft Reset
DEFAULT
20h
R/W
R/W
R/W
01h
Receiver Control Register 2
11h
02h
Reserved
03h
VSB Control Register
02h
07h
R/W
R/W
04h
AGC Control Register
05h–1Ah
1Bh
Reserved
VSB FEC Time Counter Control Register 1
BCh
64h
00h
00h
08h
00h
05h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1Ch
VSB FEC Time Counter Control Register 2
1Dh
VSB FEC Time Counter Control Register 3
1Eh
QAM FEC Time Counter Control Register 1
1Fh
QAM FEC Time Counter Control Register 2
20h
QAM FEC Time Counter Control Register 3
21h
VSB FEC Segment Error Count Threshold 1
VSB FEC Segment Error Count Threshold 2
Reserved
22h
23h–24h
25h
Update Status Control Register
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
R/W
R
26h
Receiver Status Register
27h
AGC Status Register 1 – AGC LF Accumulator Output (7:0)
AGC Status Register 2 – AGC LF Accumulator Output (15:8)
AGC Status Register 3 – AGC LF Accumulator Output (19:16)
NTSC Rejection Filter Status Register
R
28h
R
29h
R
2Ah
R
2Bh
Timing Recovery Status Register 1 – DTR LF Accumulator Output (7:0)
Timing Recovery Status Register 2 – DTR LF Accumulator Output (15:8)
Timing Recovery Status Register 3 – DTR LF Accumulator Output (23:16)
Timing Recovery Status Register 4 – DTR LF Accumulator Output (31:24)
Timing Recovery Status Register 5 – DTR LF Accumulator Output (39:32)
Timing Recovery Status Register 6 – DTR LF Accumulator Output (43:40)
Reserved
R
2Ch
R
2Dh
R
2Eh
R
2Fh
R
30h
R
31h–33h
34h
Pilot Tracking Status Register 1 – DPT LF Accumulator Output (7:0)
Pilot Tracking Status Register 2 – DPT LF Accumulator Output (15:8)
Pilot Tracking Status Register 3 – DPT LF Accumulator Output (19:16)
Reserved
N/A
N/A
N/A
R
R
R
35h
36h
37h–38h
39h
Carrier Recovery Status Register 1 – DCL Average Error (7:0)
Carrier Recovery Status Register 2 – DCL Average Error (15:8)
Carrier Recovery Status Register 3 – DCL Average Error (19:16)
Carrier Recovery Status Register 4 – QAM DCL LF Accumulator Output (7:0)
Carrier Recovery Status Register 5 – QAM DCL LF Accumulator Output (15:8)
Carrier Recovery Status Register 6 – QAM DCL LF Accumulator Output (19:16)
Reserved
N/A
N/A
N/A
N/A
N/A
N/A
R
R
R
R
R
R
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh–40h
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Table 6-1. I2C Host Interface Registers (continued)
ADDRESS
REGISTER NAME
DEFAULT
R/W
41h
42h
Forward Error Correction Status Register 1
Reserved
N/A
R
43h
Forward Error Correction Status Register 2 – FEC Segment Error Count (7:0)
Forward Error Correction Status Register 3 – FEC Segment Error Count (11:8)
Forward Error Correction Status Register 4
Reserved
N/A
N/A
N/A
R
R
R
44h
45h
46h–4Eh
4Fh
GPIO Alternate Function Select Register
GPIO Output Data Register
00h
00h
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R
50h
51h
GPIO Output Enable Register
52h
GPIO Input Data Register
53h
MPEG Interface Output Enable Register 1
MPEG Interface Output Enable Register 2
Tuner Control Interface – I2C Slave Device Address
Tuner Control Interface – Data Register 1
Tuner Control Interface – Data Register 2
Tuner Control Interface – Data Register 3
Tuner Control Interface – Data Register 4
Tuner Control Interface – Data Register 5
Tuner Control Interface – Data Register 6
Tuner Control Interface – Data Register 7
Tuner Control Interface – Data Register 8
Tuner Control Interface – Control and Status Register
Antenna Control Interface – Control and Status Register
Antenna Control Interface – Transmit Data Register 1
Antenna Control Interface – Transmit Data Register 2
Antenna Control Interface – Receive Data Register 1
Antenna Control Interface – Receive Data Register 2
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h–6Fh
70h
Firmware ID – ROM Version
02h
00h
00h
R
R
R
71h
Firmware ID – RAM Major Version
Firmware ID – RAM Minor Version
Reserved
72h
73h–7Fh
80h
Device ID LSB
00h
99h
R
R
81h
Device ID MSB
82h–EDh
EEh
EFh–F8h
F9h
Reserved
Miscellaneous Control Register
00h
00h
00h
00h
00h
R/W
R
Reserved
Software Interrupt Raw Status Register
Reserved
FAh
FBh
FCh
FDh
FEh
FFh
Software Interrupt Status Register
Reserved
R
Software Interrupt Mask Register
Reserved
R/W
W
Software Interrupt Clear Register
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6.2 I2C Register Definitions
6.2.1 Receiver Control Register 1 / Soft Reset
Any write to this register causes a soft reset, which puts the receiver back into signal acquisition, and
enables any changes made to registers 01h to 22h. Recommend performing soft reset after channel
change.
Address
00h
20h
Default
Bit
7
6
MPEGSEL
R/W
5
DCLKPS
R/W
4
BYSTPS
R/W
3
DERRPS
R/W
2
PCLKPS
R/W
1
0
Mnemonic
Type
RDNSEL
R/W
0
DMDSEL
R/W
Default
0
1
0
0
0
00
BIT
MNEMONIC
NAME
MPEG interface
DESCRIPTION
The MPEG interface redundancy select is used by the host processor to select
the data with redundancy output mode.
0 = No redundancy (data only mode) selected (default)
1 = Data with redundancy mode selected
7
RDNSEL
redundancy select
The MPEG interface serial output select is used by the host processor to
select the serial versus parallel output mode for the MPEG interface.
0 = 8-bit parallel data output mode selected (default)
1 = Serial data output mode selected
MPEG interface serial
output select
6
5
MPEGSEL
DCLKPS
The MPEG interface data clock output polarity select is used by the host
processor to select the polarity of the DCLK output pin.
0 = All MPEG interface output signals transition with respect to the rising edge
MPEG interface data
clock output polarity select of DCLK
1 = All MPEG interface output signals transition with respect to the falling edge
of DCLK (default)
The MPEG interface byte start output polarity select is used by the host
MPEG interface byte start processor to select the polarity of the BYTESTART output pin.
4
3
2
BYSTPS
DERRPS
PCLKPS
output polarity select
0 = BYTESTART is active high (default)
1 = BYTESTART is active low
The MPEG interface data error output polarity select is used by the host
MPEG interface data error processor to select the polarity of the DERROR output pin.
output polarity select
0 = DERROR is active high (default)
1 = DERROR is active low
The MPEG interface packet clock output polarity select is used by the host
processor to select the polarity of the PACCLK output pin.
MPEG interface packet
clock output polarity select 0 = PACCLK is active high (default)
1 = PACCLK is active low
The VSB or QAM mode select bits are used by the host processor to select
the demodulation type to be used by the TVP9900 receiver device.
00 = 8 VSB mode selected (default)
demodulation mode select 01 = Reserved
10 = 64 QAM mode selected
11 = 256 QAM mode selected
VSB or QAM
1:0
DMDSEL
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6.2.2 Receiver Control Register 2
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
01h
Default
Bit
11h
7
6
5
4
Reserved
R/W
3
2
1
DAFBYP
R/W
0
Reserved
R/W
Mnemonic
Type
Reserved
Reserved
IQSWAP
DNFCTRL
R/W
R
0
R
0
R
0
Default
1
00
0
1
BIT
MNEMONIC
NAME
DESCRIPTION
7:6
—
Reserved
IQ swap
Reserved for future use
Timing recovery spectral shift
0 = Shift spectrum positive frequency (default)
1 = Shift spectrum negative frequency. For QAM mode, this bit swaps I and Q.
5
4
IQSWAP
—
Reserved
Reserved for future use. Always set to 1.
NTSC detection circuit control for VSB (always bypassed for QAM)
00 = Use detection circuit (default)
01 = Force bypass of NTSC filter
10 = Force insertion of NTSC filter
11 = Reserved
NTSC detection circuit
control
3:2
DNFCTRL
Adjacent channel filter bypass for VSB (always bypassed for QAM)
0 = Enable the adjacent channel filter (default)
1 = Bypass the adjacent channel filter
Adjacent channel filter
bypass
1
0
DAFBYP
—
Reserved
Reserved for future use. Always set to 1.
6.2.3 VSB Control Register
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
03h
Default
Bit
02h
7
6
5
4
RSTDIS
R/W
0
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
7:5
—
Reserved
Reserved for future use
Disable VSB automatic soft reset mode.
0 = Firmware automatically restarts acquisition when there are too many
segment errors (default)
1 = Disable automatic restarts
4
RSTDIS
—
Auto restart disable
Reserved
3:0
Reserved for future use. Always set to 2h.
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6.2.4 AGC Control Register
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
04h
Default
Bit
07h
7
6
5
4
3
2
DAGINV
R/W
1
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
0
R
0
R
0
R
0
R
0
R
Default
11
BIT
MNEMONIC
NAME
DESCRIPTION
7:3
—
Reserved
Reserved for future use
The Automatic Gain Control output signal (AGCOUT) invert select bit is used
by the host processor to change the polarity of the output signal.
0 = AGCOUT is non-inverted
AGC output signal invert
select
2
DAGINV
—
1 = AGCOUT is inverted (default)
1:0
Reserved
Reserved for future use. Always set to 3h.
6.2.5 VSB FEC Time Counter Register 1
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
1Bh
BCh
7
Default
Bit
6
5
4
3
2
1
0
Mnemonic
Type
FCSFRSTIMECOUNT1
R/W
Default
0xBC
BIT
MNEMONIC
NAME
DESCRIPTION
VSB update interval
count, bits (7:0)
Update interval count value (RS blocks) for segment error count; bits (7:0)
of 24-bit value. The remaining bits are stored in registers 1Ch and 1Dh.
7:0
FCSFRSTIMECOUNT1
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6.2.6 VSB FEC Time Counter Register 2
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
1Ch
64h
7
Default
Bit
6
5
4
3
2
1
0
Mnemonic
Type
FCSFRSTIMECOUNT2
R/W
Default
0x64
BIT
MNEMONIC
NAME
DESCRIPTION
VSB update interval
count, bits (15:8)
Update interval count value (RS blocks) for segment error count; bits (15:8)
of 24-bit value
7:0
FCSFRSTIMECOUNT2
6.2.7 VSB FEC Time Counter Register 3
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
1Dh
00h
7
Default
Bit
6
5
4
3
2
1
0
Mnemonic
Type
FCSFRSTIMECOUNT3
R/W
Default
0x00
BIT
MNEMONIC
NAME
DESCRIPTION
VSB update interval
count, bits (23:16)
Update interval count value (RS blocks) for segment error count; bits
(23:16) of 24-bit value
7:0
FCSFRSTIMECOUNT3
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6.2.8 QAM FEC Time Counter Register 1
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
1Eh
00h
7
Default
Bit
6
5
4
3
2
1
0
Mnemonic
Type
JCSJRSTIMECOUNT1
R/W
Default
0x08
BIT
MNEMONIC
NAME
DESCRIPTION
QAM Update interval
count, bits (7:0)
Update interval count value (RS blocks) for segment error count; bits (7:0) of
24-bit value. The remaining bits are stored in registers 1Fh and 20h.
7:0
JCSJRSTIMECOUNT1
6.2.9 QAM FEC Time Counter Register 2
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
1Fh
08h
7
Default
Bit
6
5
4
3
2
1
0
Mnemonic
Type
JCSJRSTIMECOUNT2
R/W
Default
0x08
BIT
MNEMONIC
NAME
DESCRIPTION
QAM Update interval
count, bits (15:8)
Update interval count value (RS blocks) for segment error count; bits (15:8) of
24-bit value
7:0
JCSJRSTIMECOUNT2
6.2.10 QAM FEC Time Counter Register 3
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
20h
00h
7
Default
Bit
6
5
4
3
2
1
0
Mnemonic
Type
JCSJRSTIMECOUNT3
R/W
Default
0x00
BIT
MNEMONIC
NAME
DESCRIPTION
QAM Update interval
count, bits (23:16)
Update interval count value (RS blocks) for segment error count; bits (23:16)
of 24-bit value
7:0
JCSJRSTIMECOUNT3
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6.2.11 VSB FEC Segment Error Count Threshold Register 1
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
21h
05h
7
Default
Bit
6
5
4
3
2
1
0
Mnemonic
Type
UNCORRINT1
R/W
Default
0x05
BIT
MNEMONIC
NAME
DESCRIPTION
Segment Error Count
threshold, bits (7:0)
Segment error count threshold; bits (7:0) of a 12-bit value. The remaining bits
are stored in register 22h.
7:0
UNCORRINT1
6.2.12 VSB FEC Segment Error Count Threshold Register 2
A Soft Reset is required to enable any changes made to this register. A Soft Reset is initiated by writing to
register 00h.
Address
Default
Bit
22h
00h
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
UNCORRINT2
R
0
R
0
R
0
R
0
R/W
0h
Default
BIT
MNEMONIC
NAME
DESCRIPTION
7:4
Reserved
Reserved
Reserved for future use
Segment error count
threshold, bits (11:8)
3:0
UNCORRINT2
Segment error count threshold; bits (11:8) of a 12-bit value
6.2.13 Update Status Control Register
Address
Default
Bit
25h
00h
7
6
5
4
3
2
1
0
UPDATE
R/W
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
0
BIT
MNEMONIC
NAME
DESCRIPTION
7:1
—
Reserved
Reserved for future use
Update all status registers (26h to 45h)
Host writes a 1 to this bit to update all the status registers. Host should then
read this bit until it reads 0; the status update is then complete, and it is safe to
read any/all of the status registers.
0
UPDATE
Update status registers
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6.2.14 Receiver Status Register
Address
26h
Bit
7
6
5
4
Reserved
R
3
ERRCNT
R
2
Reserved
R
1
SLCERR
R
0
FLDSYNC
R
Mnemonic
Type
Reserved
Reserved
R
0
R
Default
N/A
N/A
N/A
N/A
N/A
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:4
—
Reserved
Reserved for future use
Immediate RS segment error count threshold status bit
0 = RS segment error count is below threshold
1 = RS segment error count is above threshold
Reed Solomon segment
error count status
3
2
1
ERRCNT
—
Reserved
Reserved for future use
Immediate slicer error threshold status bit
0 = Slicer error is below threshold
1 = Slicer error is above threshold
SLCERR
Slicer error status
Immediate field sync lock status bit
0 = Field sync is lost
0
FLDSYNC
Field sync lock status
1 = Field sync is locked (not lost)
6.2.15 AGC Status Register 1
Address
27h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DAGLFACC1STAT
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
Bits (7:0) of the 20-bit AGC loop filter accumulator output. The remaining bits
are stored in registers 28h and 29h. These register values are updated by
writing a 1 to register 25h, bit 0.
AGC accumulator output,
bits (7:0)
7:0
DAGLFACC1STAT
6.2.16 AGC Status Register 2
Address
28h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DAGLFACC2STAT
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
AGC accumulator output,
bits (15:8)
7:0
DAGLFACC2STAT
Bits (15:8) of the 20-bit AGC loop filter accumulator output
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6.2.17 AGC Status Register 3
Address
29h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
DAGLFACC3STAT
R
0
R
0
R
0
R
0
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:4
—
Reserved
Reserved for future use
AGC accumulator output,
bits (19:16)
3:0
DAGLFACC3STAT
Bits (19:16) of the 20-bit AGC loop filter accumulator output
6.2.18 NTSC Rejection Filter Status Register
Address
2Ah
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DNFDETECT
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:1
—
Reserved
Reserved for future use
NTSC detection circuit status
0 = NTSC is NOT detected
1 = NTSC is detected
NTSC detection circuit
status
0
DNFDETECT
6.2.19 Timing Recovery Status Register 1
Address
2Bh
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DTRLFACC1STAT
R
Default
N/A
BIT
MNEMONIC
NAME
Timing recovery
DESCRIPTION
Bits (7:0) of the 44-bit timing recovery loop filter accumulator output. The
remaining bits are stored in registers 2Ch to 30h. These register values are
updated by writing a 1 to register 25h, bit 0.
7:0
DTRLFACC1STAT accumulator output,
bits (7:0)
6.2.20 Timing Recovery Status Register 2
Address
2Ch
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DTRLFACC2STAT
R
Default
N/A
BIT
MNEMONIC
NAME
Timing recovery
DESCRIPTION
7:0
DTRLFACC2STAT accumulator output,
bits (15:8)
Bits (15:8) of the 44-bit timing recovery loop filter accumulator output
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6.2.21 Timing Recovery Status Register 3
Address
2Dh
Bit
7
6
5
4
3
2
1
0
0
0
0
Mnemonic
Type
DTRLFACC3STAT
R
Default
N/A
BIT
MNEMONIC
NAME
Timing recovery
DESCRIPTION
7:0
DTRLFACC3STAT accumulator output,
bits (23:16)
Bits (23:16) of the 44-bit timing recovery loop filter accumulator output
6.2.22 Timing Recovery Status Register 4
Address
2Eh
Bit
7
6
5
4
3
2
1
Mnemonic
Type
DTRLFACC4STAT
R
Default
N/A
BIT
MNEMONIC
NAME
Timing recovery
DESCRIPTION
7:0
DTRLFACC4STAT accumulator output,
bits (31:24)
Bits (31:24) of the 44-bit timing recovery loop filter accumulator output
6.2.23 Timing Recovery Status Register 5
Address
2Fh
Bit
7
6
5
4
3
2
1
Mnemonic
Type
DTRLFACC5STAT
R
Default
N/A
BIT
MNEMONIC
NAME
Timing recovery
DESCRIPTION
7:0
DTRLFACC5STAT accumulator output,
bits (39:32)
Bits (39:32) of the 44-bit timing recovery loop filter accumulator output
6.2.24 Timing Recovery Status Register 6
Address
30h
Bit
7
6
5
4
3
2
1
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
DTRLFACC6STAT
R
0
R
0
R
0
R
0
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:4
—
Reserved
Reserved for future use
Timing recovery
3:0
DTRLFACC6STAT accumulator output,
bits (43:40)
Bits (43:40) of the 44-bit timing recovery loop filter accumulator output
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6.2.25 Pilot Tracking Status Register 1
Address
34h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DPTLFACC1STAT
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
Bits (7:0) of the 20-bit pilot tracking loop filter accumulator output. The
remaining bits are stored in registers 35h and 36h. These register values are
updated by writing a 1 to register 25h, bit 0.
Pilot tracking accumulator
output, bits (7:0)
7:0
DPTLFACC1STAT
6.2.26 Pilot Tracking Status Register 2
Address
35h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DPTLFACC2STAT
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
Pilot tracking accumulator
output, bits (15:8)
7:0
DPTLFACC2STAT
Bits (15:8) of the 20-bit pilot tracking loop filter accumulator output
6.2.27 Pilot Tracking Status Register 3
Address
36h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
DPTLFACC3STAT
R
0
R
0
R
0
R
0
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:4
—
Reserved
Reserved for future use
Pilot tracking accumulator
output, bits (19:16)
3:0
DPTLFACC3STAT
Bits (19:16) of the 20-bit pilot tracking loop filter accumulator output
6.2.28 Carrier Recovery Status Register 1
Address
39h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DCLAVGERR1STAT
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
Bits (7:0) of the 20-bit DCL average error (derotator SNR) value. The
remaining bits are stored in registers 3Ah and 3Bh. These register values are
updated by writing a 1 to register 25h, bit 0.
DCLAVGERR1ST DCL average error, bits
AT (7:0)
7:0
Host Processor I2C Register Summary
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6.2.29 Carrier Recovery Status Register 2
Address
3Ah
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DCLAVGERR2STAT
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
DCLAVGERR2ST DCL average error,
AT bits (15:8)
7:0
Bits (15:8) of the 20-bit DCL average error (derotator SNR) value
6.2.30 Carrier Recovery Status Register 3
Address
3Bh
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
DCLAVGERR3STAT
R
0
R
0
R
0
R
0
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:4
—
Reserved
Reserved for future use
DCLAVGERR3ST DCL average error,
AT bits (19:16)
3:0
Bits (19:16) of the 20-bit DCL average error (derotator SNR) value
6.2.31 Carrier Recovery Status Register 4
Address
3Ch
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DCLLFACC1STAT
R
Default
N/A
BIT
MNEMONIC
NAME
QAM DCL loop filter
DESCRIPTION
Bits (7:0) of the 20-bit DCL loop filter accumulator output for QAM. The
remaining bits are stored in registers 3Dh and 3Eh. These register values
are updated by writing a 1 to register 25h, bit 0.
7:0
DCLLFACC1STAT
accumulator output, bits (7:0)
6.2.32 Carrier Recovery Status Register 5
Address
3Dh
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
DCLLFACC2STAT
R
Default
N/A
BIT
MNEMONIC
NAME
QAM DCL loop filter
accumulator output, bits (15:8)
DESCRIPTION
7:0
DCLLFACC2STAT
Bits (15:8) of the 20-bit DCL loop filter accumulator output for QAM.
Host Processor I2C Register Summary
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6.2.33 Carrier Recovery Status Register 6
Address
3Eh
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
DCLLFACC3STAT
R
0
R
0
R
0
R
0
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:4
—
Reserved
Reserved for future use
QAM DCL loop filter
3:0
DCLLFACC3STAT accumulator output,
bits (19:16)
Bits (19:16) of the 20-bit DCL loop filter accumulator output for QAM.
6.2.34 FEC Status Register 1
6.2.34.1 VSB Mode
Address
41h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
FECSADDR1
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:2
Reserved
Reserved for future use
FEC synchronizer status bits
00 = Searching for sync (data not valid)
01 = Locked sync (data valid)
10 = Reserved
FECSADDR1
1:0
FEC synchronizer status
11 = Sync lost (data not valid)
6.2.34.2 QAM Mode
Address
41h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
FECSADDR1
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
Trellis sync status bits
00 = Sync locked, error under threshold
01 = Reserved
7:6
Trellis sync status
10 = Sync locked, error above threshold
11 = Hunting for sync
Current deinterleaver control
work value
5:2
1:0
FECSADDR1
Current deinterleaver control work value
FEC synchronizer status bits
00 = Searching for sync (data not valid)
01 = Locked sync (data valid)
10 = Reserved
FEC synchronizer status
11 = Sync lost (data not valid)
Host Processor I2C Register Summary
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6.2.35 FEC Status Register 2
Address
43h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
FECSADDR2
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
Bits (7:0) of the 12-bit FEC segment error count value. Bits (11:8) are stored in
register 44h, bits (7:4). These register values are updated by writing a 1 to
register 25h, bit 0.
FEC segment error count,
bits (7:0)
7:0
FECSADDR2
6.2.36 FEC Status Register 3
Address
44h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
FECSADDR3
R
Default
N/A
BIT
7:4
3:0
MNEMONIC
NAME
DESCRIPTION
FEC segment error count,
bits (11:8)
Bits (11:8) of the 12-bit FEC segment error count value
Reserved for future use
FECSADDR3
Reserved
6.2.37 FEC Status Register 4
6.2.37.1 VSB Mode
Address
45h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
FECSADDR4
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:0
FECSADDR4
Reserved
Reserved for future use
6.2.37.2 QAM Mode
Address
45h
Bit
7
6
5
4
3
2
1
0
Mnemonic
Type
FECSADDR4
R
Default
N/A
BIT
MNEMONIC
NAME
DESCRIPTION
7:5
Reserved
Reserved for future use
Deframer synchronization
0 = Sync not locked
1 = Sync locked
4
FECSADDR4
Deframer synchronization
Frame error maximum
3:0
Maximum number of frame errors encountered
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6.2.38 GPIO Alternate Function Select Register
Address
Default
Bit
4Fh
00h
7
GPIO7FS
R/W
6
GPIO6FS
R/W
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
0
R
0
R
0
R
0
R
0
R
0
Default
0
0
BIT
MNEMONIC
NAME
DESCRIPTION
The GPIO bit 7 function select bit is used by the host processor to select the
alternate function of the GPIO7 device pin.
0 = Configures the GPIO7 pin as General Purpose IO bit 7 (default).
1 = Configures the GPIO7 pin as the host processor INTREQ output.
7
GPIO7FS
GPIO bit 7 function select
The GPIO bit 6 and GPIO bit 5 function select bit is used by the host
processor to select the alternate function for both the GPIO6 and GPIO5
device pins.
0 = Configures the GPIO6 pin as General Purpose IO bit 6 and GPIO5 pin as
General Purpose IO bit 5 (default).
GPIO bit 6 and GPIO bit 5
function select
6
GPIO6FS
1 = Configures the GPIO5 pin as the SYNCOUT output. The GPIO6 pin is
reserved.
5:2
1
—
—
Reserved
Reserved
Reserved for future use
NOTE: The GPIO1 pin is dedicated to Smart Antenna support. This pin
outputs the direction of the signal on pin 29 in Smart Antenna 1-pin mode (see
register 5Fh, bit 0).
If GPIO1 = 0, signal input from antenna to TVP9900 pin 29
If GPIO1 = 1, signal output from TVP9900 pin 29 to antenna
NOTE: The GPIO0 pin has an alternate function, which is the Antenna Control
Interface input (ANTCNTLIN) when 2-pin mode is selected for this interface.
See the Antenna Control Interface Control and Status Register (5Fh), bit 0 (pin
mode select), for information on how to select this alternate function.
0
—
Reserved
6.2.39 GPIO Output Data Register
Address
Default
Bit
50h
00h
7
6
GPDO6
R/W
0
5
GPDO5
R/W
0
4
GPDO4
R/W
0
3
GPDO3
R/W
0
2
GPDO2
R/W
0
1
Reserved
R/W
0
GPDO0
R/W
0
Mnemonic
Type
GPDO7
R/W
0
Default
0
BIT
MNEMONIC
NAME
DESCRIPTION
General purpose data
output bit 7
General purpose data output bit 7 is used by the host processor to set the data
value on the GPIO7 device pin.
7
GPDO7
General purpose data
output bit 6
General purpose data output bit 6 is used by the host processor to set the data
value on the GPIO6 device pin.
6
5
4
3
GPDO6
GPDO5
GPDO4
GPDO3
General purpose data
output bit 5
General purpose data output bit 5 is used by the host processor to set the data
value on the GPIO5 device pin.
General purpose data
output bit 4
General purpose data output bit 4 is used by the host processor to set the data
value on the GPIO4 device pin.
General purpose data
output bit 3
General purpose data output bit 3 is used by the host processor to set the data
value on the GPIO3 device pin.
General purpose data
output bit 2
General purpose data output bit 2 is used by the host processor to set the data
value on the GPIO2 device pin.
2
1
0
GPDO2
—
Reserved
Reserved for future use
General purpose data
output bit 0
General purpose data output bit 0 is used by the host processor to set the data
value on the GPIO0 device pin.
GPDO0
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6.2.40 GPIO Output Enable Register
Address
Default
Bit
51h
FFh
7
GPIO7OE
R/W
6
GPIO6OE
R/W
5
GPIO5OE
R/W
4
GPIO4OE
R/W
3
GPIO3OE
R/W
2
GPIO2OE
R/W
1
Reserved
R/W
0
GPIO0OE
R/W
Mnemonic
Type
Default
1
1
1
1
1
1
1
1
BIT
MNEMONIC
NAME
DESCRIPTION
General purpose IO bit 7 output enable is used by the host processor to
configure the GPIO7 device pin as either an input or output.
0 = Configures GPIO7 as an output
General purpose IO bit 7
output enable
7
GPIO7OE
1 = Configures GPIO7 as an input (default)
General purpose IO bit 6 output enable is used by the host processor to
configure the GPIO6 device pin as either an input or output.
0 = Configures GPIO6 as an output
General purpose IO bit 6
output enable
6
5
4
3
GPIO6OE
GPIO5OE
GPIO4OE
GPIO3OE
1 = Configures GPIO6 as an input (default)
General purpose IO bit 5 output enable is used by the host processor to
configure the GPIO5 device pin as either an input or output.
0 = Configures GPIO5 as an output
General purpose IO bit 5
output enable
1 = Configures GPIO5 as an input (default)
General purpose IO bit 4 output enable is used by the host processor to
configure the GPIO4 device pin as either an input or output.
0 = Configures GPIO4 as an output
General purpose IO bit 4
output enable
1 = Configures GPIO4 as an input (default)
General purpose IO bit 3 output enable is used by the host processor to
configure the GPIO3 device pin as either an input or output.
0 = Configures GPIO3 as an output
General purpose IO bit 3
output enable
1 = Configures GPIO3 as an input (default)
General purpose IO bit 2 output enable is used by the host processor to
configure the GPIO2 device pin as either an input or output.
0 = Configures GPIO2 as an output
General purpose IO bit 2
output enable
2
1
0
GPIO2OE
—
1 = Configures GPIO2 as an input (default)
Reserved
Reserved for future use
General purpose IO bit 0 output enable is used by the host processor to
configure the GPIO0 device pin as either an input or output.
0 = Configures GPIO0 as an output
General purpose IO bit 0
output enable
GPIO0OE
1 = Configures GPIO0 as an input (default)
6.2.41 GPIO Input Data Register
Address
Default
Bit
52h
00h
7
6
GPDI7
R
5
GPDI7
R
4
GPDI7
R
3
GPDI7
R
2
GPDI7
R
1
0
GPDI7
R
Mnemonic
Type
GPDI7
R
Reserved
R
0
Default
0
0
0
0
0
0
0
BIT
MNEMONIC
NAME
DESCRIPTION
General purpose data
input bit 7
General purpose data input bit 7 is used by the host processor to read the
data value on the GPIO7 device pin.
7
GPDI7
General purpose data
input bit 6
General purpose data input bit 6 is used by the host processor to read the
data value on the GPIO6 device pin.
6
5
4
GPDI6
GPDI5
GPDI4
General purpose data
input bit 5
General purpose data input bit 5 is used by the host processor to read the
data value on the GPIO5 device pin.
General purpose data
input bit 4
General purpose data input bit 4 is used by the host processor to read the
data value on the GPIO4 device pin.
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BIT
MNEMONIC
GPDI3
NAME
DESCRIPTION
General purpose data
input bit 3
General purpose data input bit 3 is used by the host processor to read the
data value on the GPIO3 device pin.
3
General purpose data
input bit 2
General purpose data input bit 2 is used by the host processor to read the
data value on the GPIO2 device pin.
2
1
0
GPDI2
—
Reserved
Reserved for future use
General purpose data
input bit 0
General purpose data input bit 0 is used by the host processor to read the
data value on the GPIO0 device pin.
GPDI0
6.2.42 MPEG Interface Output Enable Register 1
Address
Default
Bit
53h
00h
7
6
DO6OE
R/W
0
5
DO5OE
R/W
0
4
DO4OE
R/W
0
3
DO3OE
R/W
0
2
DO2OE
R/W
0
1
DO1OE
R/W
0
0
DO0OE
R/W
0
Mnemonic
Type
DO7OE
R/W
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
MPEG data output bit 7 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 7
output enable
7
DO7OE
1 = Output is enabled
MPEG data output bit 6 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 6
output enable
6
5
4
3
2
1
0
DO6OE
DO5OE
DO4OE
DO3OE
DO2OE
DO1OE
DO0OE
1 = Output is enabled
MPEG data output bit 5 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 5
output enable
1 = Output is enabled
MPEG data output bit 4 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 4
output enable
1 = Output is enabled
MPEG data output bit 3 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 3
output enable
1 = Output is enabled
MPEG data output bit 2 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 2
output enable
1 = Output is enabled
MPEG data output bit 1 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 1
output enable
1 = Output is enabled
MPEG data output bit 0 output enable is used by the host processor to enable
the output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data output bit 0
output enable
1 = Output is enabled
Host Processor I2C Register Summary
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6.2.43 MPEG Interface Output Enable Register 2
Address
Default
Bit
54h
00h
7
6
5
4
3
2
1
SYNCSOE
R/W
0
DCLKOE
R/W
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
0
R
0
R
0
R
0
R
0
R
0
Default
0
0
BIT
MNEMONIC
NAME
DESCRIPTION
7:2
—
Reserved
Reserved for future use
MPEG sync signals output enable is used by the host processor to enable the
MPEG interface sync signals, which are packet clock (PACCLK), byte start
MPEG sync signals output (BYTESTART) and data error (DERROR). After power-on reset, the outputs
1
0
SYNCSOE
DCLKOE
enable
are disabled.
0 = Outputs are disabled (default)
1 = Outputs are enabled
MPEG data clock output enable is used by the host processor to enable the
clock output. After power-on reset, the output is disabled.
0 = Output is disabled (default)
MPEG data clock output
enable
1 = Output is enabled
6.2.44 Tuner Control Interface – I2C Slave Device Address Register
The I2C slave device address register contains the 7-bit I2C slave device address and the read/write
transaction control bit to be used for the tuner device.
Address
Default
Bit
55h
00h
7
6
A5
R/W
0
5
A4
R/W
0
4
A3
R/W
0
3
A2
R/W
0
2
A1
R/W
0
1
A0
R/W
0
0
RW
R/W
0
Mnemonic
Type
A6
R/W
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
The slave device address bits are set by the host processor with the 7-bit I2C
slave address of the Tuner device to be accessed.
7:1
A(6:0)
Slave device address
The read/write control bit value is set by the host processor to program the
type of Tuner Control Interface I2C transaction to be done.
1 = Read transaction
0
RW
Read/write control
0 = Write transaction (default)
6.2.45 Tuner Control Interface – Data Register 1 Through 8
Address
Default
Bit
56h to 5Dh
00h
7
6
D6
R/W
0
5
D5
R/W
0
4
D4
R/W
0
3
D3
R/W
0
2
D2
R/W
0
1
D1
R/W
0
0
D0
R/W
0
Mnemonic
Type
D7
R/W
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
Data register 1 through data register 8 contain the data bytes to be sent to the
tuner for a write transaction or the data bytes received from the tuner for a
read transaction. The data byte contained in data register 1 (56h) shall be the
first byte sent to or read from the tuner.
7:0
D(7:0)
Data (7:0)
Host Processor I2C Register Summary
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6.2.46 Tuner Control Interface – Control and Status Register
Address
Default
Bit
5Eh
00h
7
6
BCNT2
R/W
0
5
BCNT2
R/W
0
4
3
2
START
R/W
0
1
0
MODE
R/W
0
Mnemonic
Type
BCNT2
R/W
0
Reserved
Reserved
Reserved
R
0
R
0
R
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
The byte count is used by the host processor to set the number of data bytes
to be transferred to/from the tuner device. The byte count should not include
the tuner I2C slave address byte.
7:5
BCNT(2:0)
Byte count
000b = 1 byte, 001b = 2 bytes, ..., 110b = 7 bytes, 111b = 8 bytes
4:3
2
—
Reserved
Reserved for future use
The transaction start bit is set to 1 by the host processor to indicate to the
MCU to start the transaction to the tuner. The MCU clears this bit at the end of
the transaction.
START
—
Transaction start
Reserved
1
Reserved for future use
The mode bit is used by the host processor to set the I2C transfer mode and
rate.
0 = Standard mode and 100-kbps transfer rate (default)
1 = Fast mode and 400-kbps transfer rate
0
MODE
I2C mode
6.2.47 Antenna Control Interface – Control and Status Register
Address
Default
Bit
5Fh
00h
7
6
Reserved
R/W
5
RXERR
R/W
0
4
MODE
R/W
0
3
TXSTART
R/W
2
TXRXSEL
R/W
1
TXDINV
R/W
0
0
PINSEL
R/W
0
Mnemonic
Type
Reserved
R
0
Default
0
0
0
BIT
MNEMONIC
NAME
DESCRIPTION
7:6
—
Reserved
Reserved for future use
The receive data error bit is set to 1 by the MCU to indicate an error occurred
when receiving data from a mode B antenna. The MCU clears this bit at the
beginning of the next transaction.
5
RXERR
Receive data error
The auto receive mode bit is set to 1 by the host processor to enable the
antenna control interface logic to automatically set-up the receive mode after a
transmit data transaction.
4
3
MODE
Auto receive mode
Transmit start
This bit is set to 1 by the host processor to start the transmit data transaction
to the antenna. The MCU clears this bit when the transaction is complete.
TXSTART
This bit is used by the host processor to select the next type of transaction to
be done by the antenna control interface. In manual mode, the host processor
controls this bit. In auto receive mode, the host processor sets this bit to 1 for
the transmit data transaction, and the MCU sets this bit to 0 after the
completion of the transmit transaction to enable the receive transaction.
0 = Receive data transaction
2
1
TXRXSEL
TXDINV
Transmit/receive select
Transmit data polarity
1 = Transmit data transaction
The transmit data polarity bit is set to 1 by the host processor to invert the
transmit data output.
0 = Normal polarity in conformance with CEA909
1 = Invert the transmit data output
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BIT
MNEMONIC
NAME
DESCRIPTION
The pin mode select bit is used by the host processor to select the antenna
control interface pin configuration. Before the 2-pin mode is selected, the
GPIO0 pin must be configured as an input in register 51h, bit 0.
0 = 2-pin mode (separate input and output pins are used, input = pin 72,
output = pin 29) (default)
0
PINSEL
Pin mode select
1 = 1-pin mode (one bidirectional pin is used, pin 29)
6.2.48 Antenna Control Interface – Transmit Data Register 1
Address
Default
Bit
60h
00h
7
6
TXD6
R/W
0
5
TXD5
R/W
0
4
TXD4
R/W
0
3
TXD3
R/W
0
2
TXD2
R/W
0
1
TXD1
R/W
0
0
TXD0
R/W
0
Mnemonic
Type
TXD7
R/W
0
Default
BIT
MNEMONIC
NAME
Transmit data (7:0)
DESCRIPTION
The least significant 8 bits of the 14-bit data word to be transmitted to the
antenna. Bits (13:8) are stored in register 61h, bits (5:0). The data word is set
by the host processor.
7:0
TXD(7:0)
6.2.49 Antenna Control Interface – Transmit Data Register 2
Address
Default
Bit
61h
00h
7
6
5
TXD13
R/W
0
4
TXD12
R/W
0
3
TXD11
R/W
0
2
TXD10
R/W
0
1
TXD9
R/W
0
0
TXD8
R/W
0
Mnemonic
Type
Reserved
Reserved
R
0
R
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
7:6
—
Reserved
Reserved for future use
The most significant 6 bits of the 14-bit data word to be transmitted to the
antenna. The data word is set by the host processor.
5:0
TXD(13:8)
Transmit data (13:8)
6.2.50 Antenna Control Interface – Receive Data Register 1
Address
Default
Bit
62h
00h
7
6
RXD6
R/W
0
5
RXD5
R/W
0
4
RXD4
R/W
0
3
RXD3
R/W
0
2
RXD2
R/W
0
1
RXD1
R/W
0
0
RXD0
R/W
0
Mnemonic
Type
RXD7
R/W
0
Default
BIT
MNEMONIC
NAME
Receive data (7:0)
DESCRIPTION
The least significant 8-bits of the 10-bit program code received from a mode B
antenna. Bits (9:8) are stored in register 63h, bits (1:0).
7:0
RXD(7:0)
Host Processor I2C Register Summary
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6.2.51 Antenna Control Interface – Receive Data Register 2
Address
Default
Bit
63h
00h
7
6
5
4
3
2
1
RXD9
R/W
0
0
RXD8
R/W
0
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
0
R
0
R
0
R
0
R
0
R
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
7:2
—
Reserved
Reserved for future use
The most significant 2 bits of the 10-bit program code received from a mode B
antenna.
1:0
RXD(9:8)
Receive data (9:8)
6.2.52 Firmware ID – ROM Version Register
Address
Default
Bit
70h
02h
7
6
5
4
3
2
1
1
1
0
0
0
Mnemonic
Type
ROMVER
R
Default
0x02
BIT
MNEMONIC
NAME
ROM version
DESCRIPTION
7:0
ROMVER
Version identification for ROM code
6.2.53 Firmware ID – RAM Major Version Register
Address
Default
Bit
71h
00h
7
6
5
4
3
2
Mnemonic
Type
RAM1VER
R
Default
0x00
BIT
MNEMONIC
NAME
Major RAM version
DESCRIPTION
7:0
RAM1VER
Major version identification for RAM code
6.2.54 Firmware ID – RAM Minor Version Register
Address
Default
Bit
72h
00h
7
6
5
4
3
2
Mnemonic
Type
RAM2VER
R
Default
0x00
BIT
MNEMONIC
NAME
Minor RAM version
DESCRIPTION
7:0
RAM2VER
Minor version identification for RAM code
Host Processor I2C Register Summary
46
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6.2.55 Device ID LSB Register
Address
Default
Bit
80h
00h
7
6
5
4
3
2
1
0
Mnemonic
Type
DEVID1
R
Default
0x00
BIT
MNEMONIC
NAME
Device ID LSB
DESCRIPTION
7:0
DEVID1
The LSB of the device ID
6.2.56 Device ID MSB Register
Address
Default
Bit
81h
99h
7
6
5
4
3
2
1
0
Mnemonic
Type
DEVID2
R
Default
0x99
BIT
MNEMONIC
NAME
Device ID MSB
DESCRIPTION
7:0
DEVID2
The MSB of the device ID
6.2.57 Miscellaneous Control Register
Address
Default
Bit
EEh
00h
7
6
5
4
3
2
INTRQPS
R/W
1
MCUMDE
R/W
0
MCURST
R/W
Mnemonic
Type
Reserved
Reserved
Reserved
Reserved
Reserved
R
0
R
0
R
0
R
0
R
0
Default
0
0
0
BIT
MNEMONIC
NAME
DESCRIPTION
7:3
—
Reserved
Reserved for future use
The interrupt request pin polarity select bit is used by the host processor to
select either an active low or active high INTREQ output. Note that when
active low is selected, the output goes tri-state when inactive (not driven high).
Hence a pullup resistor needs to be used on the PCB. This is done so interrupt
request sources from multiple ICs can be wired together.
Interrupt request pin
polarity select
2
INTRQPS
0 = INTREQ output pin is active low (default)
1 = INTREQ output pin is active high
The MCU memory mode is used by the host processor to select ROM or RAM
as the code memory for the internal TVP9900 MCU.
0 = MCU executes from ROM (default)
1
0
MCUMDE
MCURST
MCU memory mode
MCU reset
1 = MCU executes from RAM
The MCU reset bit is used by the host processor to do a soft reset of the
internal TVP9900 MCU.
0 = MCU not in reset mode (default)
1 = MCU in reset mode
Host Processor I2C Register Summary
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6.2.58 Software Interrupt Raw Status Register
The raw status bits in this register are cleared by the host processor by writing a 1 to the corresponding bit
in the Software Interrupt Clear Register (FFh). The intended use of the raw status registers is for events to
be monitored by the host processor via polling instead of interrupt driven.
Address
F9h
Default
Bit
00h
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
ACIRXCT
ACITXCT
ACIRXTO
Reserved
TCIERROR
TCIDONE
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
7:6
—
Reserved
Reserved for future use
The Antenna Control Interface receive transaction complete raw status bit is
set to 1 by the MCU when the receive transaction from a mode B antenna is
complete. This means an entire 10-bit data word was received. If an
incomplete receive transaction (less than 10-bits) occurs, then this bit is not
set; instead the ACIRXTO (bit 3) occurs. After the receive transaction is
complete, the host processor should also check the receive data error status
bit (RXERR) in the Antenna Control Interface Control and Status Register
(5Fh) to ensure that an error was not detected while receiving the data.
Antenna Control Interface
receive transaction
complete
5
ACIRXCT
Antenna Control Interface
transmit transaction
complete
The Antenna Control Interface transmit transaction complete raw status bit is
set to 1 by the MCU when the transmit transaction to the antenna is complete.
4
3
ACITXCT
ACIRXTO
The Antenna Control Interface receive timeout raw status bit is set to 1 by the
MCU when the 100-ms timeout has occurred. If a 100-ms timeout occurs, then
Antenna Control Interface the antenna either did not reply to the transmit transaction (it is a mode A
receive timeout
antenna) or an incomplete (less than 10-bits) receive transaction occurred. If
an incomplete transaction occurred, then the receive error status bit (RXERR)
in the Antenna Control Interface Control and Status Register (5Fh) is also set.
2
1
—
Reserved
Reserved for future use
The Tuner Control Interface transaction error raw status bit is set to 1 by the
MCU to indicate to the host processor that the tuner device did not respond to
the I2C transaction or that a NO ACK was received from the tuner when an
ACK was expected.
Tuner Control Interface
transaction error
TCIERROR
The Tuner Control Interface transaction done raw status bit is set to 1 by the
MCU at the end of a normal transaction to indicate to the host processor that
the tuner I2C transaction completed successfully. If an error occurs during a
transaction to the tuner, the MCU does not set this bit to 1.
Tuner Control Interface
transaction done
0
TCIDONE
6.2.59 Software Interrupt Status Register
The status bits in this register are the result of the logical AND of the corresponding raw status bits and
mask bits. A status bit is also automatically cleared when the corresponding raw status bit is cleared.
Unmasked status bits in this register assert the host processor interrupt request output pin, INTREQ, of
the TVP9900 when the status bit is set to 1. All unmasked hardware and software status bits are ORed
together to drive the INTREQ output pin.
Address
FBh
Default
Bit
00h
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
ACIRXCT
ACITXCT
ACIRXTO
Reserved
TCIERROR
TCIDONE
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
Host Processor I2C Register Summary
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BIT
MNEMONIC
NAME
DESCRIPTION
7:6
—
Reserved
Reserved for future use
Antenna Control Interface The Antenna Control Interface receive complete status bit is set to 1 (if
5
ACIRXCT
receive transaction
complete
unmasked) when the receive transaction from a mode B antenna is complete
and the bit is unmasked.
Antenna Control Interface The Antenna Control Interface transmit complete status bit is set to 1 (if
4
ACITXCT
transmit transaction
complete
unmasked) when the transmit transaction to the antenna is complete and the
bit is unmasked.
Antenna Control Interface The Antenna Control Interface receive timeout status bit is set to 1 (if
3
2
ACIRXTO
—
receive timeout
unmasked) when the 100-ms timeout has occurred and the bit is unmasked.
Reserved
Reserved for future use
The Tuner Control Interface transaction error status bit is set to 1 (if
unmasked) to indicate to the host processor that the tuner device did not
respond to the I2C transaction or that a NO ACK was received from the tuner
when an ACK was expected.
Tuner Control Interface
transaction error
1
0
TCIERROR
TCIDONE
The Tuner Control Interface transaction done status bit is set to 1 (if
unmasked) at the end of a normal transaction to indicate to the host processor
that the tuner I2C transaction completed successfully. If an error occurs during
a transaction to the tuner, the MCU does not set this bit to 1.
Tuner Control Interface
transaction done
6.2.60 Software Interrupt Mask Register
The interrupt mask registers are used by the host processor to mask unused interrupt sources. When an
interrupt status bit is masked, the event results in the raw status bit being set but does not result in the
status bit being set or the assertion of the interrupt request output pin, INTREQ.
Address
FDh
Default
Bit
00h
7
Reserved
R/W
6
Reserved
R/W
5
ACIRXCT
R/W
4
ACITXCT
R/W
3
ACIRXTO
R/W
2
Reserved
R/W
1
TCIERROR
R/W
0
TCIDONE
R/W
Mnemonic
Type
Default
0
0
0
0
0
0
0
0
BIT
MNEMONIC
NAME
DESCRIPTION
7:6
—
Reserved
Reserved for future use
This bit is used by the host processor to enable the Antenna Control Interface
receive transaction complete interrupt.
0 = Interrupt disabled (default)
Antenna Control Interface
receive transaction
complete interrupt mask
5
4
ACIRXCT
ACITXCT
1 = Interrupt enabled
This bit is used by the host processor to enable the Antenna Control Interface
transmit transaction complete interrupt.
0 = Interrupt disabled (default)
Antenna Control Interface
transmit transaction
complete interrupt mask
1 = Interrupt enabled
This bit is used by the host processor to enable the Antenna Control Interface
receive timeout interrupt.
0 = Interrupt disabled (default)
Antenna Control Interface
receive timeout interrupt
mask
3
2
1
ACIRXTO
—
1 = Interrupt enabled
Reserved
Reserved for future use
This bit is used by the host processor to enable the Tuner Control Interface
transaction error interrupt.
0 = Interrupt disabled (default)
Tuner Control Interface
transaction error interrupt
mask
TCIERROR
1 = Interrupt enabled
This bit is used by the host processor to enable the Tuner Control Interface
transaction done interrupt.
0 = Interrupt disabled (default)
Tuner Control Interface
transaction done interrupt
mask
0
TCIDONE
1 = Interrupt enabled
Host Processor I2C Register Summary
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6.2.61 Software Interrupt Clear Register
The interrupt clear registers are used by the host processor to clear the interrupt raw status and status
bits. To clear an interrupt, a 1 must be written to the corresponding bit in this register. The interrupt clear
bits are automatically reset to 0 by the TVP9900 hardware. When all unmasked interrupts are cleared, the
INTREQ device output pin is inactive.
Address
FFh
Default
Bit
00h
7
6
5
4
3
2
1
0
Mnemonic
Type
Reserved
Reserved
ACIRXCT
ACITXCT
ACIRXTO
Reserved
TCIERROR
TCIDONE
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Default
BIT
MNEMONIC
NAME
DESCRIPTION
7:6
—
Reserved
Reserved for future use
Antenna Control Interface
receive transaction complete
interrupt clear
This bit should be set to 1 by the host processor to clear the Antenna
Control Interface receive transaction complete raw status bit, which also
clears the status bit and interrupt if unmasked.
5
4
ACIRXCT
ACITXCT
Antenna Control Interface
This bit should be set to 1 by the host processor to clear the Antenna
transmit transaction complete Control Interface transmit transaction complete raw status bit, which also
interrupt clear
clears the status bit and interrupt if unmasked.
This bit should be set to 1 by the host processor to clear the Antenna
Control Interface receive timeout raw status bit, which also clears the
status bit and interrupt if unmasked.
Antenna Control Interface
receive timeout interrupt clear
3
2
1
ACIRXTO
—
Reserved
Reserved for future use
Tuner Control Interface
transaction error interrupt
clear
This bit should be set to 1 by the host processor to clear the Tuner Control
Interface transaction error raw status bit, which also clears the status bit
and interrupt if unmasked.
TCIERROR
Tuner Control Interface
transaction done interrupt
clear
This bit should be set to 1 by the host processor to clear the Tuner Control
Interface transaction done raw status bit, which also clears the status bit
and interrupt if unmasked.
0
TCIDONE
Host Processor I2C Register Summary
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7
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TVP9900 device.
All electrical and timing characteristics in this specification shall be valid over the recommended operating
conditions, unless otherwise noted.
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
DVDD_1_5
Supply voltage range
Supply voltage range
Supply voltage range
Supply voltage range
Supply voltage range
Supply voltage range
1.5 V digital core supply
–0.5 V to 2.1 V
–0.5 V to 4.2 V
IOVDD_3_3
AVDD_1_5
3.3 V IO cell supply
1.5 V analog core supply
3.3 V analog core supply
3.3 V reference supply
1.5 V PLL supply
–0.5 V to 2.1 V
AVDD_3_3
–0.5 V to 4.2 V
AVDD_REF_3_3
AVDD_PLL_1_5
–0.5 V to 4.2 V
–0.5 V to 2.1 V
XTALIN, oscillator input
Fail-safe LVCMOS
–0.5 V to AVDD_PLL_1_5 + 0.5 V
–0.5 V to IOVDD_3_3 + 0.5 V
–0.5 V to AVDD_3_3 + 0.5 V
–0.5 V to AVDD_PLL_1_5 + 0.5 V
–0.5 V to IOVDD_3_3 + 0.5 V
±20 mA
VI
Input voltage range
Differential IF inputs: AIFIN_P, AIFIN_N
XTALOUT, oscillator output
Fail-safe LVCMOS
VO
Output voltage range
IIK
Input clamp current
VI < 0 or VI > VCC
IOK
TA
Output clamp current
VO < 0 or VO > VCC
±20 mA
Operating free-air temperature range
Storage temperature range
0°C to 70°C
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended
operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
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7.2 Recommended Operating Conditions
MIN
NOM
1.5
3.3
1.5
3.3
1.5
3.3
MAX
1.65
UNIT
DVDD_1_5
1.5-V digital core supply voltage
3.3-V IO cell supply voltage
1.5-V analog core supply voltage
3.3-V analog core supply voltage
1.5-V PLL supply voltage
1.35
V
IOVDD_3_3
AVDD_1_5
3
3.6
1.65
V
V
V
V
V
1.35
AVDD_3_3
3
3.6
AVDD_PLL_1_5
AVDD_REF_3_3
1.35
1.65
3.3-V reference supply voltage
3
3.6
XTALIN
0
AVDD_PLL_1_5
IOVDD_3_3
AVDD_PLL_1_5
IOVDD_3_3
AVDD_PLL_1_5
IOVDD3_3
0.3(AVDD_PLL_1_5)
0.3(IOVDD_3_3)
–8
VI
Input voltage
V
V
V
V
LVCMOS
XTALOUT
LVCMOS
XTALIN
0
0
VO
VIH
VIL
Output voltage
0
0.7(AVDD_PLL_1_5)
High-level input voltage
Low-level input voltage
LVCMOS
XTALIN
0.7(IOVDD_3_3)
0
0
LVCMOS
LVCMOS
LVCMOS
XTALIN
IOH
IOL
High-level output current
Low-level output current
mA
mA
8
25
25
fclock
Clock input frequency
MHz
CLKIN
tt
Input transition, rise and fall time, 10% to 90%
Operating free-air temperature
0
0
0
25
70
ns
°C
°C
TA
TJ
25
25
Operating junction temperature
105
7.3 DC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
0.8(IOVDD_3_3)
TYP
MAX UNIT
VOH
High-level output voltage
Low-level output voltage
Low-level input current
LVCMOS IOH = –8 mA
V
VOL
LVCMOS IOL = 8 mA
VI = VIL (min)
0.22(IOVDD_3_3)
V
IIL
±1
±1
µA
IIH
High-level input current
VI = VIH (max)
µA
IOZ
High-impedance output current
1.5-V digital core supply current
3.3-V IO cell supply current
±20
µA
(1)
(1)
(1)
IDVDD_1_5
IIOVDD_3_3
IAVDD_1_5
IAVDD_3_3
IAVDD_PLL_1_5
IAVDD_REF_3_3
630
3
mA
mA
mA
mA
mA
mA
1.5-V analog core supply current
3.3-V analog core supply current
1.5-V analog PLL supply current
3.3-V analog reference supply current
0.2
45
5
(1)
(1)
(1)
22
8-VSB mode with
parallel MPEG
output(1)
1.2
W
PD
Power dissipation
Power-down mode
0.45
8
mW
pF
Ci
Input capacitance
Output capacitance
Co
8
pF
(1) For typical values: nominal voltages, TA = 25°C
52
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7.4 Analog Input Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.4
0
MAX
UNIT
Vp-p
kΩ
VI
RI
CI
Differential input voltage
Ccoupling = 0.1 µF
1
Input resistance
Differential input capacitance
Input gain control
10
6
pF
–6
–3
dB
Input gain control ratio
3
%
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7.5 Timing Characteristics
over recommended operating conditions (unless otherwise noted)
7.5.1 Crystal and Input Clock
The TVP9900 can be used with an external crystal with a frequency of 25 MHz or with an external clock source
with a frequency of 4 MHz or 25 MHz. The on-chip oscillator in the TVP9900 is designed to work with an external
crystal with a frequency range of 15 MHz to 35 MHz. Therefore, if a clock frequency of 4 MHz is required, an
external clock source, not an external crystal, must be used. When an external clock source is used, the on-chip
oscillator simply functions as an input buffer.
Table 7-1. Crystal and Input Clock Timing
PARAMETER
Frequency, XTALIN (external crystal or clock source)
Cycle time, XTALIN (external crystal or clock source)(1)
Frequency, XTALIN (external clock source only)
Cycle time, XTALIN (external clock source only)(1)
Frequency stability
MIN
TYP
25
MAX
UNIT
MHz
ns
fXTALIN
tcyc1
fXTALIN
tcyc1
40
4
MHz
ns
250
–50
50
ppm
(1) Worst-case duty cycle is 45/55.
XTALIN
tcyc1
Figure 7-1. Crystal or Clock Timing Waveform
7.5.2 Device Reset
The power-on reset signal, RESETZ, is an active-low asynchronous reset that is used to initialize the device at
power-up. The RESETZ signal may be low during power-up but must remain active low for a minimum of 1 ms
after all power-supply voltages are stable at the recommended operating voltage. Internal circuits synchronize
the power-on reset with internal clocks; therefore, the RESETZ signal must remain active low for a minimum of
1 µs after the crystal oscillator and clocks are stable.
Table 7-2. Device Reset Timing
PARAMETER
MIN
TYP
MAX
UNIT
Pulse duration, RESETZ low after all power supplies are stable at the recommended
operating voltage and the crystal oscillator is stable
tw1(L)
1
ms
VDD (all supplies)
tW1(L)
RESESTZ
Figure 7-2. Device Reset Signal Timing Waveforms
54
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7.5.3 MPEG Interface
7.5.3.1 Parallel Mode (Data Only)
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in
Figure 7-3 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output
signals transitioning with respect to the falling edge of DCLK. In this mode, PACCLK is always active. If an error
occurs, the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes.
Table 7-3. Parallel Mode (Data Only) Timing
CL = 30 pF
PARAMETER
MIN
TYP
2.42408
3.37129
4.85133
50
MAX
UNIT
8 VSB mode
fDCLK
Frequency, DCLK
Duty cycle, DCLK
64 QAM mode
256 QAM mode
MHz
dcyc
tpd1
tpd2
tpd3
tpd4
tpd5
%
ns
ns
ns
ns
ns
Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high
Propagation delay time, DCLK falling (or rising) edge to BYTE_START low
Propagation delay time, DCLK falling (or rising) edge to DERROR high
Propagation delay time, DCLK falling (or rising) edge to DERROR low
–2
–2
–2
–2
–2
3
3
3
3
3
DCLK
tpd1
DATAOUT [7:0]
BYTE_START
Byte 0
Byte 1
Byte 186
Byte 187
Byte 0
tpd2
tpd3
PACCLK
DERROR
tpd4
tpd5
Figure 7-3. MPEG Interface – Parallel Mode (Data Only) Timing Waveforms
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7.5.3.2 Serial Mode (Data Only)
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in
Figure 7-4 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output
signals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cycles
corresponding to the eight bits of the first byte of data. In this mode, PACCLK is always active. If an error occurs,
the DERROR signal is active for the length of the entire packet. The packet length is 188 bytes.
Table 7-4. Serial Mode (Data Only) Timing
CL = 30 pF
PARAMETER
MIN
TYP
19.39266
26.97035
38.81070
50
MAX
UNIT
8 VSB mode
fDCLK
Frequency, DCLK
Duty cycle, DCLK
64 QAM mode
256 QAM mode
MHz
dcyc
tpd1
tpd2
tpd3
tpd4
tpd5
%
ns
ns
ns
ns
ns
Propagation delay time, DCLK falling (or rising) edge to SERDATAO valid
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high
Propagation delay time, DCLK falling (or rising) edge to BYTE_START low
Propagation delay time, DCLK falling (or rising) edge to DERROR high
Propagation delay time, DCLK falling (or rising) edge to DERROR low
–2
–2
–2
–2
–2
3
3
3
3
3
DCLK
tpd1
SERDATAO
D7
D0
D7
D0
D7
tpd2
tpd3
BYTE_START
PACCLK
tpd5
tpd4
DERROR
Figure 7-4. MPEG Interface – Serial Mode (Data Only) Timing Waveforms
56
Electrical Specifications
Submit Documentation Feedback
TVP9900
VSB/QAM Receiver
www.ti.com
SLEA064–MARCH 2007
7.5.3.3 Parallel Mode (Data With Redundancy)
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in
Figure 7-5 are shown with BYTE_START, PACCLK and DERROR as active high signals and with the output
signals transitioning with respect to the falling edge of DCLK. PACCLK is only active during the time period that
the 188 bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of the
entire packet.
Table 7-5. Parallel Mode (Data With Redundancy) Timing
CL = 30 pF
PARAMETER
MIN
TYP
2.68196
3.65821
5.26422
50
MAX
UNIT
8 VSB mode
fDCLK
Frequency, DCLK
Duty cycle, DCLK
64 QAM mode
256 QAM mode
MHz
dcyc
tpd1
tpd2
tpd3
tpd4
tpd5
tpd6
tpd7
%
ns
ns
ns
ns
ns
ns
ns
Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high
Propagation delay time, DCLK falling or rising edge to BYTE_START low
Propagation delay time, DCLK falling (or rising) edge to PACCLK high
Propagation delay time, DCLK falling (or rising) edge to PACCLK low
Propagation delay time, DCLK falling (or rising) edge to DERROR high
Propagation delay time, DCLK falling (or rising) edge to DERROR low
–2
–2
–2
–2
–2
–2
–2
3
3
3
3
3
3
3
DCLK
tpd1
DATAOUT [7:0]
BYTE_START
Byte 0
Byte 1
Byte 187
Byte 0
tpd2
tpd3
tpd5
tpd4
PACCLK
DERROR
tpd6
tpd7
Figure 7-5. MPEG Interface – Parallel Mode (Data With Redundancy) Timing Waveforms
Submit Documentation Feedback
Electrical Specifications
57
TVP9900
VSB/QAM Receiver
www.ti.com
SLEA064–MARCH 2007
7.5.3.4 Serial Mode (Data With Redundancy)
The polarity of DCLK, BYTE_START, PACCLK and DERROR are programmable. The timing waveforms in
Figure 7-6 are shown with BYTE_START, PACCLK, and DERROR as active-high signals and with the output
signals transitioning in respect to the falling edge of DCLK. BYTE_START is active for the eight clock cycles
corresponding to the eight bits of the first byte of data. PACCLK is only active during the time period that the 188
bytes of data are being transferred. If an error occurs, the DERROR signal is active for the length of the entire
packet.
Table 7-6. Serial Mode (Data With Redundancy) Timing
CL = 30 pF
PARAMETER
MIN
TYP
2.42408
3.37129
4.85133
50
MAX
UNIT
8 VSB mode
fDCLK
Frequency, DCLK
Duty cycle, DCLK
64 QAM mode
256 QAM mode
MHz
dcyc
tpd1
tpd2
tpd3
tpd4
tpd5
%
ns
ns
ns
ns
ns
Propagation delay time, DCLK falling (or rising) edge to DATAOUT [7:0] valid
Propagation delay time, DCLK falling (or rising) edge to BYTE_START high
Propagation delay time, DCLK falling (or rising) edge to BYTE_START low
Propagation delay time, DCLK falling (or rising) edge to DERROR high
Propagation delay time, DCLK falling (or rising) edge to DERROR low
3
3
3
3
3
DCLK
tpd1
SERDATAO
D7
D7
D0
D0
D7
tpd2
tpd3
BYTE_START
PACCLK
tpd5
tpd4
tpd6
tpd7
DERROR
Figure 7-6. MPEG Interface – Serial Mode (Data with Redundancy) Timing Waveforms
58
Electrical Specifications
Submit Documentation Feedback
TVP9900
VSB/QAM Receiver
www.ti.com
SLEA064–MARCH 2007
7.5.4 Host and Tuner I2C Interface
Host processor communication with the TVP9900 device is done via an I2C slave interface. The TVP9900 also
has an I2C master interface that is used by the TVP9900 to communicate with the system tuner. Both of these
I2C interfaces are designed to work for both standard and fast modes of operation. The timing parameters and
the timing waveforms below pertain to both I2C interfaces.
Table 7-7. Host and Tuner I 2C Interface Timing
STANDARD
MODE
FAST
MODE
PARAMETER
UNIT
MIN
0
MAX
MIN
MAX
fSCL
tW(H)
tW(L)
tr
Frequency, SCL
100
0
0.6
1.3
400
kHz
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
pF
Pulse duration, SCL high
Pulse duration, SCL low
Rise time, SCL and SDA
Fall time, SCL and SDA
Setup time, SDA to SCL
4
4.7
1000
300
300
300
tf
tsu1
th1
250
0
100
0
Hold time, SCL to SDA(1)
tbuf
tsu2
th2
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Load capacitance for each bus line
4.7
4.7
4
1.3
0.6
0.6
0.6
tsu3
CL
4
400
400
(1) The TVP9900 internally provides a minimum hold time of 300 ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu1
th1
SDA
Figure 7-7. I2C SCL and SDA Timing Waveforms
SCL
tsu2
tsu3
th2
tbuf
SDA
Start Condition
Stop Condition
Figure 7-8. I2C Start and Stop Conditions Timing Waveforms
Submit Documentation Feedback
Electrical Specifications
59
TVP9900
VSB/QAM Receiver
www.ti.com
SLEA064–MARCH 2007
8
Application Circuit
Q E R T N I / 7 O I P G
K C O L / 6 O I P G
D N G O I
3 _ 3 _ D D V O I
T U O C N Y S / 5 O I P G
4 O I P G
R O R R E D
N W O D R W P
0 A C 2 I
5 _ 1 _ D D V D
D N G D
L C S C 2 I
A D S C 2 I
3 _ 3 _ D D V O I
D N G O I
L C S N U T
A D S N U T
O I L T N C T N A
T U O C G A
3 L E S M T
2 L E S M T
5 _ 1 _ D D V D
D N G D
1 6
2 6
3 6
4 6
5 6
6 6
7 6
8 6
9 6
0 7
1 7
2 7
3 7
4 7
5 7
6 7
7 7
8 7
9 7
0 8
0 4
9 3
8 3
7 3
6 3
5 3
4 3
3 3
2 3
1 3
0 3
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
3 O I P G
5 _ 1 _ D D V D
D N G D
2 O I P G
1 O I P G
N I L T N C T N A / 0 O I P G
5 _ 1 _ D D V D
D N G D
D N G A
F E R _ D N G A
3 _ 3 _ F E R _ D D V A
S E R S A I
B
1 L E S M T
0 L E S M T
Z T E S E R
P A C F E R G B
B U S N
D A P R W P
2
1
60
Application Circuit
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Apr-2007
PACKAGING INFORMATION
Orderable Device
TVP9900PFP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PFP
80
96 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TVP9900PFPR
HTQFP
PFP
80
1000 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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