TVS1401 [TI]
14V 双向平缓钳位浪涌保护器件;
| 型号： | TVS1401 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14V 双向平缓钳位浪涌保护器件 |
| 文件： | 总21页 (文件大小：1397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVS1401
ZHCSIV0B –SEPTEMBER 2018 –REVISED NOVEMBER 2021
TVS1401 14V 双向平缓钳位浪涌保护器件
1 特性
3 说明
• 提供功能安全
TVS1401 器件可将高达 30A 的 IEC 61000-4-5 故障电
流进行分流，以保护系统免受高功率瞬态冲击或雷击。
该器件可通过 42Ω 阻抗进行耦合的方式承受 1kV 的
IEC 61000-4-5 开路电压，满足常见的工业信号线路
EMC 要求。TVS1401 使用反馈机制确保在故障期间发
挥精确的平缓钳位能力，使系统接触电压始终低于传统
TVS 二极管。精确的电压调节允许设计人员放心地选
择具有较低电压容差的系统组件，从而能够在不影响可
靠性的情况下降低系统成本和复杂度。TVS1401 具有
±14V 的工作范围，可在需要反向接线情形防护的系统
中运行。
– 可帮助进行功能安全系统设计的文档
• 保护特性符合针对工业信号线路的±1kV、42ΩIEC
61000-4-5 浪涌测试要求
• 双向极性可针对双极信号传输或误接线情形提供保
护
• 30A 8/20µs 浪涌电流下的钳位电压为20.5V
• 关断电压：±14V
• 3mm × 3mm 小型SON 封装
• 在125°C 时，可耐受超过5,000 次的30A 8/20µs
浪涌电流的重复冲击
• 强大的浪涌保护
此外，TVS1401 采用小型 SON 封装，专为空间受限
的应用而设计，与标准 SMA 和 SMB 封装相比，其尺
寸显著减小。低器件泄露电流和电容确保最大限度地降
低了对受保护线路的影响。为了确保在产品的整个寿命
期间提供可靠保护，TI 在125°C 的环境下对TVS1401
进行了 5,000 次重复浪涌冲击测试，但器件性能未发
生任何变化。
– IEC61000-4-5 (8/20µs)：30A
– IEC61643-321 (10/1000µs)：6A
• 低泄漏电流
– 27°C 下为1.1nA（典型值）
– 85°C 时的最大值为260nA
• 低电容：68pF
• 集成4 级IEC 61000-4-2 ESD 保护
器件信息(1)
2 应用
封装尺寸（标称值）
器件型号
TVS1401
封装
SON (8)
3.00mm × 3.00mm
• 工业传感器I/O
• 固态硬盘
• 电机驱动器
• 12V 电源线路
• 电器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 医疗设备
• 电网保护和控制
10
20
30
Time (ꢀs)
Traditional TVS
TI Flat-Clamp
对8/20µs 浪涌事件的电压钳位响应
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEQ2
TVS1401
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ZHCSIV0B –SEPTEMBER 2018 –REVISED NOVEMBER 2021
Table of Contents
9.3 Feature Description.....................................................8
9.4 Device Functional Modes............................................8
10 Application and Implementation................................10
10.1 Application Information........................................... 10
10.2 Typical Application.................................................. 10
11 Power Supply Recommendations..............................11
12 Layout...........................................................................12
12.1 Layout Guidelines................................................... 12
12.2 Layout Example...................................................... 12
13 Device and Documentation Support..........................13
13.1 Documentation Support.......................................... 13
13.2 接收文档更新通知................................................... 13
13.3 支持资源..................................................................13
13.4 Trademarks.............................................................13
13.5 Electrostatic Discharge Caution..............................13
13.6 术语表..................................................................... 13
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 5
8.1 Absolute Maximum Ratings........................................ 5
8.2 ESD Ratings - JEDEC................................................ 5
8.3 ESD Ratings - IEC...................................................... 5
8.4 Recommended Operating Conditions.........................5
8.5 Thermal Information....................................................5
8.6 Electrical Characteristics.............................................6
8.7 Typical Characteristics................................................7
9 Detailed Description........................................................8
9.1 Overview.....................................................................8
9.2 Functional Block Diagram...........................................8
Information.................................................................... 13
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2018) to Revision B (November 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更新了特性部分，以添加“提供功能安全型”文本............................................................................................1
Changes from Revision * (September 2018) to Revision A (December 2018)
Page
• 将“预告信息”更改为“量产数据”.................................................................................................................. 1
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5 说明（续）
TVS1401 是 TI 的平缓钳位系列浪涌器件中的一款产品。如需深入了解平缓钳位系列，请参阅《用于高效系统保
护的平缓钳位浪涌保护技术》白皮书。
6 Device Comparison Table
Leakage @
DEVICE
Vrwm
Vclamp at Ipp
Ipp (8/20 µs)
POLARITY
Package
Vrwm
0.07 nA
0.25 nA
2 nA
TVS0500
TVS0701
TVS1400
TVS1401
TVS1800
TVS1801
TVS2200
TVS2201
TVS2700
TVS2701
5
9.2 V
11 V
43 A
30 A
43 A
30 A
40 A
30 A
40 A
30 A
40 A
27 A
Unidirectional
Bidirectional
Unidirectional
Bidirectional
Unidirectional
Bidirectional
Unidirectional
Bidirectional
Unidirectional
Bidirectional
DRV (SON-6)
DRB (SON-8)
DRV (SON-6)
DRB (SON-8)
DRV (SON-6)
DRB (SON-8)
DRV (SON-6)
DRB (SON-8)
DRV (SON-6)
DRB (SON-8)
7
14
14
18
18
22
22
27
27
18.6 V
20.5 V
22.8 V
27.4 V
27.7 V
29.6 V
32.5 V
34 V
1.1 nA
0.3 nA
0.4 nA
3.2 nA
2 nA
1.7 nA
0.8 nA
DRV (SON-6), YZF
(WCSP)
TVS3300
TVS3301
33
33
38 V
40 V
35 A
27 A
19 nA
Unidirectional
Bidirectional
2.5 nA
DRB (SON-8)
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7 Pin Configuration and Functions
图7-1. DRB Package
8-Pin SON
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
FLOAT
DRB
Exposed Thermal Pad
5, 6, 7, 8
NC
GND
IN
Exposed Thermal Pad Must Be Floating
Ground
GND
IN
1, 2, 3, 4
Surge Protected Channel
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8 Specifications
8.1 Absolute Maximum Ratings
TA = 27°C (unless otherwise noted)(1)
MIN
MAX
±30
600
±6
UNIT
A
IEC 61000-4-5 Current (8/20 µs), TA < 125°C
IEC 61000-4-5 Power (8/20 µs)
IEC 61643-321 Current (10/1000 µs)
IEC 61643-321 Power (10/1000 µs)
IEC 61000-4-4 EFT Protection
DC Current
W
Maximum Surge
A
120
±80
45
W
EFT
IBR
A
mA
°C
°C
TA
Ambient Operating Temperature
Storage Temperature
-40
-65
125
125
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings - JEDEC
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 ESD Ratings - IEC
VALUE
UNIT
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
±8
V(ESD)
Electrostatic discharge
kV
±15
8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VRWM
Reverse Stand-Off Voltage
±14
V
8.5 Thermal Information
TVS1401
THERMAL METRIC(1)
DRB (SON)
8 PINS
52.0
UNIT
RqJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RqJC(top)
RqJB
56.1
24.9
YJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.1
YJB
24.8
RqJC(bot)
9.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
nA
Measured at VIN = ±VRWM, TA = 27°C
Measured at VIN = ±VRWM, TA = 85°C
IIN = ±1mA
1.1
30
ILEAK
VBR
Leakage Current
260
Break-down Voltage
Clamp Voltage
17.1
17.6
20.5
V
±Ipp IEC 61000-4-5 Surge (8/20 µs), VIN
0 V before surge, TA = 27°C
=
22.2
VCLAMP
V
±IPP IEC 61000-4-5 Surge (8/20 µs), VIN
=±VRWM before surge, TA = 125°C
23.55
Calculated from VCLAMP at .5*IPP and IPP
surge current, TA = 25°C
RDYN
CIN
8/20 µs surge dynamic resistance
Input pin capacitance
70
68
mΩ
VIN = VRWM, f = 1 MHz, 30 mVpp, IO to
GND
pF
0-±VRWM rising edge, sweep rise time and
measure slew rate when IPEAK = 1 mA, TA
= 27°C
2.5
1
SR
Maximum Slew Rate
V/µs
0-±VRWM rising edge, sweep rise time and
measure slew rate when IPEAK = 1 mA, TA
= 85°C
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8.7 Typical Characteristics
25
40
32
24
16
8
21
20.75
20.5
20.25
20
Voltage (V)
Current (A)
20
15
10
5
19.75
19.5
19.25
19
0
0
-5
-8
0.0001
0
2E-5
4E-5
6E-5
8E-5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Time (s)
TVS1
tvs1
图8-1. 8/20 µs Surge Response at 30 A
图8-2. 8/20 µs Surge Clamping Response at 30 A
120
105
90
75
60
45
30
15
0
80
60
40
20
0
0
2
4
6
8
10
12
14
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
VIN (V)
tvs1
tvs1
f = 1 MHz, 30 mVpp, IO to GND
图8-3. Capacitance vs Voltage Bias
图8-4. Leakage Current vs Temperature at ±14 V
18.5
18.25
18
8
7.5
7
6.5
6
5.5
5
-40èC
25èC
85èC
105èC
125èC
4.5
4
3.5
3
2.5
2
1.5
1
17.75
17.5
17.25
17
0.5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
0
0.5
1
1.5
Slew Rate (V/ms)
2
2.5
3
tvs1
D009
图8-5. Breakdown Voltage (1 mA) vs Temperature
图8-6. Dynamic Leakage vs Signal Slew Rate across
Temperature
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9 Detailed Description
9.1 Overview
The TVS1401 is a bidirectional precision clamp with two integrated FETs driven by a feedback loop to tightly
regulate the input voltage during an overvoltage event. This feedback loop leads to a very low dynamic
resistance, giving a flat clamping voltage during transient overvoltage events like a surge.
9.2 Functional Block Diagram
9.3 Feature Description
The TVS1401 is a precision clamp that handles ±30 A of IEC 61000-4-5 8/20 µs surge pulse. The flat clamping
feature helps keep the clamping voltage very low to keep the downstream circuits from being stressed. The flat
clamping feature can also help end-equipment designers save cost by opening up the possibility to use lower-
cost, lower voltage tolerant downstream ICs. This device provides a bidirectional operating range, with a
symmetrical VRWM of ±14 V, which is designed for applications that have bipolar input signals or that must
withstand reverse wiring conditions. The TVS1401 has minimal leakage at VRWM designed for applications
where low leakage and power dissipation is a necessity. Built-in IEC 61000-4-2 and IEC 61000-4-4 ratings make
it a robust protection solution for ESD and EFT events, and the TVS1401 wide ambient temperature range of –
40°C to +125°C enables usage in harsh industrial environments.
9.4 Device Functional Modes
9.4.1 Protection Specifications
The TVS1401 is specified according to both the IEC 61000-4-5 and IEC 61643-321 standards. This enables
usage in systems regardless of which standard is required by relevant product standards or best matches
measured fault conditions. The IEC 61000-4-5 standard requires protection against a pulse with a rise time of 8
µs and a half-length of 20 µs, while the IEC 61643-321 standard requires protection against a much longer pulse
with a rise time of 10 µs and a half-length of 1000 µs.
The positive and negative surges are imposed to the TVS1401 by a combination wave generator (CWG) with a
2-Ω coupling resistor at different peak voltage levels. For powered-on transient tests that need power supply
bias, inductances are used to decouple the transient stress and protect the power supply. The TVS1401 is post-
tested by assuring that there is no shift in device breakdown or leakage at VRWM
.
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In addition, the TVS1401 has been tested according to IEC 61000-4-5 to pass a ±1-kV surge test through a 42-
Ω coupling resistor and a 0.5-µF capacitor. This test is a common test requirement for industrial signal I/O lines
and the TVS1401 precision clamp can be used in applications that have that requirement.
The TVS1401 integrates IEC 61000-4-2 level 4 ESD Protection and 80 A of IEC 61000-4-4 EFT Protection.
These combine to ensure that the device can protect against most common transient test requirements.
For more information on TI's test methods for Surge, ESD, and EFT testing, refer to theTI's IEC 61000--4-x Tests
for TI's Protection Devices application report.
9.4.2 Reliability Testing
To ensure device reliability, the TVS1401 is characterized against 5,000 repetitive pulses of 25-A IEC 61000-4-5
8/20-µs surge pulses at 125°C. The test is performed with less than 10 seconds between each pulse at high
temperature to simulate worst-case scenarios for fault regulation. After each surge pulse, the TVS1401 clamping
voltage, breakdown voltage, and leakage are recorded to ensure that there is no variation or performance
degradation. By ensuring robust, reliable, high temperature protection, the TVS1401 enables fault protection in
applications that must withstand years of continuous operation with no performance change.
9.4.3 Zero Derating
Unlike traditional diodes, the TVS1401 has zero derating of maximum power dissipation and ensures robust
performance up to 125°C. Traditional TVS diodes lose up to 50% of their current carrying capability when at high
temperatures, so a surge pulse above 85°C ambient can cause failures that are not seen at room temperature.
The TVS1401 prevents this so the designer can see the surge protection regardless of temperature. Because of
this, Flat-Clamp devices can provide robust protection against surge pulses that occur at high ambient
temperatures, as shown in TI's TVS Surge Protection in High-Temperature Environments application report.
9.4.4 Bidirectional Operation
The TVS1401 is a bidirectional TVS with a symmetrical operating region. This allows for operation with positive
and negative voltages, rather than just positive voltages like the unidirectional TVS1400. This allows for single
chip protection for applications where the signal is expected to operate below 0 V or where there is a need to
withstand a large common-mode voltage. In addition, in many cases, there is a system requirement to be able to
withstand reverse wiring conditions, in many cases where a high voltage signal is accidentally applied to the
system ground and a ground is accidentally applied to the input terminal. This causes a large reverse voltage on
the TVS diode that the device must be able to withstand. The TVS1401 is designed to not break down or see
failures under reverse wiring conditions for applications that must withstand these miswiring issues.
Note
If the applied signal is not expected to go below 0 V, an unidirectional device will clamp much lower in
the reverse direction and should be used. In this case, the recommended device would be the
TVS1400.
9.4.5 Transient Performance
During large transient swings, the TVS1401 will begin clamping the input signal to protect downstream
conditions. While this prevents damage during fault conditions, it can cause leakage when the intended input
signal has a fast slew rate. To keep power dissipation low and remove the chance of signal distortion, TI
recommends that the designer keep the slew rate of any input signal on the TVS1401 below 2.5 V/µs at room
temperature and below 1 V/µs at 85°C as shown in 图 8-6. Faster slew rates will cause the device to clamp the
input signal and draw current through the device for a few microseconds, increasing the rise time of the signal.
This will not cause any harm to the system or to the device, however, it can cause device overheating if the fast
input voltage swings occur regularly.
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10 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TVS1401 can be used to protect any power, analog, or digital signal from transient fault conditions caused
by the environment or other electrical components.
10.2 Typical Application
图10-1. TVS1401 Application Schematic
10.2.1 Design Requirements
A typical operation for the TVS1401 would be protecting in a factory control application and protecting an analog
input to an ADC input similar to 图10-1. In this example, the TVS1401 is protecting the input to an ADS8689, an
ADC with an input voltage range of ±12.288 V and an absolute maximum input voltage range of ±20 V. Without
any input protection, this input voltage will rise to hundreds of volts for multiple microseconds, and violate the
absolute maximum input voltage and harm the device if a surge event is caused by lightning, coupling, ringing,
or any other fault condition. TI's Flat-Clamp technology provides surge protection diodes that can maximize the
useable voltage range at a safe level for the system.
10.2.2 Detailed Design Procedure
If the TVS1401 is in place to protect the device, the voltage will rise to the breakdown of the diode at 17.6 V
during a surge event. The TVS0701 will then turn on to shunt the surge current to ground. With the low dynamic
resistance of the TVS1401, large amounts of surge current will have minimal impact on the clamping voltage.
The dynamic resistance of the TVS1401 is around 70 mΩ, which means a 25-A surge current will cause a
voltage raise of 25 A × 70 mΩ = 1.75 V. Because the device turns on at 17.6 V, this means the ADC input will be
exposed to a maximum of 17.6 V + 1.75 V = 19.35 V during surge pulses, well within the ADS8689 absolute
maximum to ensure robust protection of the circuit. The same magnitude of voltage will be seen during a
negative pulse, still safely protecting the system.
In addition, the low leakage and capacitance of the TVS1401 assures low input distortion. At 14 V, giving margin
on the ±12.288 V range of the ADS8689, the device will see typical 1.1-nA leakage, which will have minimal
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effect on the overall system. The TVS1401 low capacitance of 68 pF will also cause less effect on signal integrity
compared to industry standard devices like the SMBJ14CA which has 1500 pF of capacitance and can cause up
to 3 dB of THD attenuation in measured systems.
Finally, the small size of the device also improves fault protection by lowering the effect of fault current coupling
onto neighboring traces. The small form factor of the TVS1401 allows the device to be placed extremely close to
the input connector, which lowers the length of the path fault current going through the system compared to
larger protection solutions.
10.2.3 Application Curves
When a surge is applied to a system with the TVS1401, the device will clamp the overvoltage to a safe level as
shown in 图10-2.
25
20
15
10
5
40
32
24
16
8
Voltage (V)
Current (A)
0
0
-5
-8
0.0001
0
2E-5
4E-5
6E-5
8E-5
Time (s)
TVS1
图10-2. TVS1401 Surge Clamping Response
11 Power Supply Recommendations
The TVS1401 is a clamping device so there is no need to power it. To ensure the device functions properly, do
not violate the recommended VIN voltage range (-14 V to 14 V).
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12 Layout
12.1 Layout Guidelines
The optimum placement is close to the connector. EMI during an ESD event can couple from the tested trace to
other nearby unprotected traces, which could result in system failures. The PCB designer must minimize the
possibility of EMI coupling by keeping all unprotected traces away from protected traces between the TVS and
the connector. Route the protected traces straight. Use rounded corners with the largest radii possible to
eliminate any sharp corners on the protected traces between the TVS1401 and the connector. Electric fields
tend to build up on corners, which could increase EMI coupling.
Ensure that the thermal pad on the layout is floating rather than grounded. Grounding the thermal pad will
impede the operating range of the TVS1401 and can cause failures when the applied voltage is negative. A
floating thermal pad allows the maximum operating range without sacrificing any transient performance.
12.2 Layout Example
图12-1. TVS1401 Layout
Copyright © 2022 Texas Instruments Incorporated
12
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Product Folder Links: TVS1401
TVS1401
www.ti.com.cn
ZHCSIV0B –SEPTEMBER 2018 –REVISED NOVEMBER 2021
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Flat-Clamp Surge Protection Technology for Efficient System Protection white paper
• Texas Instruments, TI's IEC 61000--4-x Tests for TI's Protection Devices application report
• Texas Instruments, TVS Surge Protection in High-Temperature Environments application report
• Texas Instruments, TVS1401 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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13
Product Folder Links: TVS1401
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TVS1401DRBR
ACTIVE
SON
DRB
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1PSP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TVS1401DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DRB
SPQ
Length (mm) Width (mm) Height (mm)
338.0 355.0 50.0
TVS1401DRBR
8
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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