TWL2214CAPFB_技术文档

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

D

Programmable Charging Current

features

Six Programmable Low-Dropout Linear

Voltage Regulators

D

Integrated, Single-Chip Solution for Battery

Charge Control and Power Supply

Management

Over 65-dB Power Supply Rejection Ratio

(PSRR) From 10 Hz to 10 kHz

D

Linear Charger for Single-Cell Li-Ion or

Li-Polymer Packs

System Over- and Under-Voltage Shutdown

Power On/Off and Reset Control Logic

Integrated Control over Precharge,

Constant-Current, and Constant-Voltage

Charging Phases

Three Individually Selectable LED Backlight

Drivers

D

Programmable Charge Termination by

Minimum Current and Time

D

Vibrator and Ringer Drivers

D

Internal 8-Bit Analog-to-Digital Converter

With Auxiliary Inputs

D

Battery Temperature Sensing

D

Pack Wake-Up and Damaged Cell Detect

Functions

2

D

I C Control Interface and Three-Wire SPI

Interface

D

Safety Charge Timers During Precharge

and Constant-Current Charging

48-Terminal Plastic TQFP (PFB) or

MicroStar Junior BGA (GQE) Package

description

The TWL2214CA device is a single-chip battery and power management solution for wireless handsets, pagers,

personal digital assistants (PDAs), and other battery-powered devices. For battery charging, the device

incorporates a linear charger for single-cell Li-Ion and lithium polymer battery packs. Prior to charging, the

TWL2214CA device initiates battery pack wake-up and damaged cell detect functions. For deeply discharged

batteries, the device performs precharge conditioning by trickle charge to a user-defined current setting. Once

an acceptable pack voltage is detected, the TWL2214CA device applies a constant-current fast charge at a

current level that is determined by the combination of an external sense resistor and user-programmable sense

voltage. When the battery reaches the selected charge regulation voltage, the TWL2214CA device maintains

regulation until charging is terminated by a minimum current or a timer. During the entire charge cycle, the

TWL2214CA device monitors temperature by external thermistor and suspends charging if temperature

exceeds a programmed range. Three programmable safety timers limit the precharge, constant current, and

total charge times.

For power management, the TWL2214CA device includes six low-dropout linear voltage regulators. One

regulator is driven from the device power-on/-off logic and incorporates a microcontroller reset function. Five

low-noise regulators include individually programmable output voltage and enable-disable. The TWL2214CA

device can be powered from a battery or from an ac adapter. When an adapter is present, it supplies power to

the device, allowing the system to function without a battery.

The TWL2214CA device also includes individually selectable drivers for three separate backlight LEDs, a ringer,

and a vibrator motor. An internal 8-bit analog-to-digital converter (ADC) is accessible from external terminals.

2

All TWL2214CA programming and status are accessed by the system microcontroller via the I C/SPI serial

interface.

The TWL2214CA device is packaged in the Texas Instruments 48-terminal plastic thin quad flatpack (TQFP)

(PFB) or the MicroStar Junior BGA (GQE) package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior BGA is a trademark of Texas Instruments Incorporated.

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

AVAILABLE OPTIONS

PACKAGE

OUTPUT VOLTAGE

REGULATOR 6

T

A

DEVICE NAME

INTERFACE

REGULATOR 1

2

I C

–40°C to 85°C

TWL2214CAPFBR

TQFP

2.8 V

3 V

2

I C/SPI

TWL2214CAGQER MicroStar Junior BGA

GQE PACKAGE

(BOTTOM VIEW)

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9

36 35 34 33 32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

17

16

15

14

13

TS

PWRKOUT

PWRKIN

PSH

37

ADCIN1

ADCIN2

CONT

38

39

40

41

42

43

44

45

DATA

CLK

CD2

DGND

VIOUT

V

REG5

V

PFB PACKAGE

(TOP VIEW)

DD4

V

REG4

BGRF

GND2

V

DD5

V

RINGOUT 46

REG3

V

RINGIN

GND3

47

48

DD3

V

REG2

1

2

3

4

5

6

7

8

9 10 11 12

DISSIPATION RATING TABLE

OPERATING FACTOR

T

= 25°C

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING

ABOVE 25°C

11.8 mW/°C

15.7 mW/°C

POWER RATING POWER RATING

GQE

PFB

1176 mW

647 mW

471 mW

1962 mW

1256 mW

1020 mW

2

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

block diagram

IRQ

Battery Charger Control

GND

REF

CT

AGND

V

DD1

V

REG1

GND

REG1

Reference System

BGRF

Reset

Control

XRST

CD1

PWRKOUT

PWRKIN

PSH

V

DD2

REG6

Power

On/Off

Control

REG6

CONT

CD2

V

DD3

REG2

REG3

REG4

REG5

CE

DATA

CLK

V

REG2

2

I C

DGND

V

REG3

DD4

REG4

LED

Driver

Ring

Driver

Vibrator

Driver

V

REG5

GND2

3

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

ADCIN1

GQE NO. PFB NO.

J8

J7

23

22

8

I

ADC input

ADCIN2

AGND

ADC input

C4, D3,

I/O

Regulator 1 ground

D4, E3, E4

BGRF

CD1

CD2

CE

J4

F1

A5

A8

B5

H6

17

9

I/O

Band gap output bypass capacitance

XRST output delay adjustment capacitance

Regulator 1 off delay adjustment capacitance

Clock enabled

I/O

42

I/O

I

2

CLK

41

21

I C/SPI bus serial clock input

CONT

Regulator 6 is always on after power up except when CONT = H; regulator 6 is

2

enabled through I C interface.

CT

B9

A6

A4

C8, G2

H4

B2

B1

C2

C1

B8

E9

B6

A7

B7

H9

A2

B3

C9

D2

H8

G8

D9

F8

35

40

43

12, 34

16

48

1

I/O

O

I

External oscillator timing cap

2

DATA

DGND

GND

I C/SPI bus serial address/data input output; this is a bidirectional terminal.

Digital ground

Ground

GND2

GND3

IL0

Ground for V

, V

, and V

REG5

REG2 REG3 REG4

Ground for vibrator, LED, and ringer

160-mA LED driver output

20-mA LED driver output

IL1

2

IL2

3

10-mA LED driver output

IRQ

36

31

39

38

37

25

47

46

33

4

Interrupt signal for external controller regarding to charger start/stop action

Current sense input for charger function

Power hold signal from controller

ISENSE

PSH

I

PWRKIN

PWRKOUT

REF

I

Power-up start

O

I/O

O

I/O

I

Power-up signal for CPU

Voltage reference during charge cycle, 3 V, I = 3 mA

O

RINGIN

RINGOUT

RPRE

SEL

Input for ring driver

Ring driver output

Precharge current sense resistor

Input for vibrator output voltage change

Battery temperature sense input voltage

Battery voltage sense input or output for precharge, wakeup

DC voltage input for charger

TS

24

26

32

28

5

I

V

I/O

I

BAT

CHG

DD

I

Device dc supply feedback for charger function

Device dc supply input and regulator 1 input

Input to regulator 6

D1

G1

J2

I

DD1

DD2

DD3

DD4

DD5

11

14

19

45

30

29

I

Input for regulators 2 and 3

J5

I

Input for regulators 4 and 5

A3

E8

F9

I

Input for vibrator, PN diode connection of ringer

Gate control of an external P-FET for charger regulation

Gate control of an external P-FET for battery blockage

VG

O

VG2

4

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

Terminal Functions (Continued)

TERMINAL

GQE NO. PFB NO.

I/O

DESCRIPTION

NAME

VG3

VIOUT

G9

B4

E2

H2

J3

27

44

6

O

I/O

O

Gate control of an external P-FET for charging action

Vibrator output

V

Regulator 1 output

REG1

REG2

REG3

REG4

REG5

REG6

13

15

18

20

10

7

O

Regulator 2 output

O

Regulator 3 output

H5

J6

O

Regulator 4 output

O

Regulator 5 output

F2

E1

O

Regulator 6 output

XRST

O

Reset output

detailed description

power-on/-off control

The timing of the delayed power-on reset is controlled by the power-on/-off control circuit. There are two different

conditions to power-on the device: manual power on and automatic power on.

manual power on

During the power-off state, after the power key is pressed, the PWRKIN signal becomes high and the output

of V (regulator 1 output) is enabled. When the V output reaches 90% of its nominal output voltage,

REG1

the TWL2214CA device starts the delayed reset process by charging the reset timing capacitor (CD1). When

the voltage of CD1 reaches 1.2 V, the XRST signal is released by the TWL2214CA device and pulled high by

an external pull-up resistor. The reset process is completed, and the external controller operates in normal

condition. While PWRKIN remains high, the power-on condition remains active. Before PWRKIN goes low, the

external controller must drive PSH high to retain power; otherwise, the TWL2214CA device starts the delay

power-off process by charging timing capacitor CD2. After the voltage of CD2 reaches 1.2 V and no valid PSH

signal is received, the device is powered off.

automatic power on

During the power-off state, after the adapter is attached, the output of V

is automatically enabled. When

REG1

V

reaches 90% of its nominal output voltage, the TWL2214CA device starts the delayed reset process by

REG1

charging the reset timing capacitor (CD1). When the voltage of the CD1 reaches 1.2 V, the XRST signal is

released by the TWL2214CA device and pulled high by an external pull-up resistor. The reset process is

completed and the external controller operates in normal condition. The external controller must drive PSH to

high in time to retain power; otherwise, the TWL2214CA device starts the delay power-off process by charging

timing capacitor CD2. After voltage of CD2 reaches 1.2 V and if no valid PSH signal is received, the device is

powered off.

During the on state, the device generates an output signal PWRKOUT with an inverted polarity to PWRKIN. An

external controller can use PWRKOUT to sense whether the power key has been pressed.

5

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

detailed description (continued)

Battery Attachment

VG3

VG2

V

DD

PWRKIN

PWRKOUT

0.9 V

OUT

V

REG1

CDI Delay

CPU senses this falling

edge and drives PSH to L

CD1

XRST

PSH

CD2

Power Off

Power On

Figure 1. Power-On/-Off Sequence

6

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

detailed description (continued)

Battery Attachment

VG3

VG2

V

DD

A

B

A

PWRKIN

PWRKOUT

V

CHG

Adapter Attachment

OUT

0.9 V

V

REG1

CDI Delay

CD1

XRST

PSH

CD2

A:V

B:V

= V

BAT

= 4.1 V or 4.2 V

DD

Auto power up with

adapter insertion

Figure 2. Adapter Powered (With Battery)

7

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

detailed description (continued)

VG3

VG2

V

DD

PWRKIN

PWRKOUT

V

CHG

Adapter Attachment

OUT

0.9 V

V

REG1

CDI Delay

CPU senses this falling

edge and drives PSH to L

CD1

XRST

PSH

CD2

Power down by

power key insertion

Auto power up with

adapter insertion

Figure 3. Adapter Powered (Without Battery)

reset controller

The reset controller performs two major functions: one is to control the timing of delayed power-on reset, and

the other is to monitor the V level.

REG1

The delay reset process is started when V

reaches 90% of its nominal output voltage level. The delay time

REG1

of the reset output (XRST) can be adjusted by an external timing capacitor (CD1).

During the system active state when V drops below 0.9 × V – hysteresis, XRST is driven low. If V

REG1

nominal

reaches 90% of its nominal output voltage level again, the delayed reset process is started over.

8

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

detailed description (continued)

V

REG1

Hysteresis

0.9 V

OUT

XRST

CD1 delay

PSH

CD1

CD2

To keep power-on condition PSH must be

high within maximum CD2 delay.

Figure 4. V

Monitoring of Reset Control

REG1

regulator 1

This regulator is automatically enabled after the power-on process is complete. It stays enabled until the

power-off condition occurs. Regulator 1 supplies power to the microprocessor. The nominal output voltage is

2.8 V and the maximum output current is 150 mA. Regulator 1 requires an output capacitor in the range of 4.7 µF

to10 µF with an ESR less than 6 Ω.

regulator 6

2

This regulator output voltage can be enabled by I C by attaching CONT (terminal 21 or H6) to V . Attaching

DD

CONT to GND makes this regulator automatically enabled with power on. The output voltage is programmed

2

by I C. The maximum output current of 100 mA requires an output capacitor in range of 4.7 µF to 10 µF, with

ESR in the range of 1 Ω to 6 Ω. The output voltage ranges from 2.5 V to 3 V.

regulators 2, 3, 4, and 5

2

Regulators 2, 3, 4, and 5 are output voltages programmed and enabled by I C. The output voltage ranges from

2.3 V to 3 V in 100-mV steps. The maximum output current for regulators 2 and 3 is 80 mA, for regulator 4 it

is 120 mA, and for regulator 5 it is 150 mA. The default output voltage for all regulators is 3 V. These regulators

have very low output noise (maximum 30 µV

an output capacitor in the range of 4.7 µF to 10 µF with an ESR less than 6 Ω.

); they are suitable for powering up the RF block, which requires

RMS

vibrator driver

The TWL2214CA device has incorporated a vibrator driver with selectable output voltage and current. This

2

integrated vibrator driver has the same features as the other LDO regulators. The vibrator is enabled by I C.

The output voltage can be selected by tying SEL (terminal 4 or D2) to V

output voltage is set to 3 V. If SEL is tied to GND, the output voltage is set to 1.3 V.

or GND. If SEL is tied to V , the

DD

LED driver

2

The TWL2214CA device provides the capability of driving three LEDs. These drivers, enabled by I C, can drive

currents of 160 mA, 20 mA, and 10 mA individually with a maximum voltage drop of 0.8 V.

ringer driver

2

The TWL2214CA device provides the capability of driving a ringer. It is enabled by I C and uses an N-channel

FET with a maximum resistance of 3 Ω.

9

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SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

dual-interface serial bus: DISB

2

The DISB is a three-wire interface bus that incorporates both Phillips I C and three-wire SPI. The SPI interface

used here is different from the standard SPI interface; it combines both transmit and receive channels into one

bidirectional port. It also incorporates the slave addressing topology to work like a bus and control many devices

at the same time. The interface does not have a selection pin to choose between the two protocols. It uses the

clock enable line to distinguish the communication format of the interface. When clock enable is high, the clock

2

and data lines work as a standard I C interface. However, on the falling edge of clock enable, the device expects

the SPI protocol defined in the following section. The protocol includes a slave address identifier that allows the

2

lines to be connected to many devices similar to that of I C serial bus. Speed also improves when eliminating

the master wait period to receive an acknowledge from the slave device.

battery charger control

This block provides the necessary signals to control the external circuits that perform the charger function. The

charging activities include battery pack wake-up, precharge, fast charge, and battery temperature monitoring.

This block also provides 2 ADC inputs for general measurement purposes. The input voltage level is from 0 V

to 2 V. This block also includes an oscillator generator circuit, which generates the clocks for the device. The

nominal frequency of the main clock is 500 kHz. It requires an external capacitor of 470 pF.

reference system

This block provides voltage reference and bias current for the internal circuitry.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 12 V

CHG

All other terminals relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V

Operating ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 150°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

STG

Soldering temperature (for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

4.5

MAX

6

UNIT

V

CHG

, V

3.3

4.3

V

DD1 DD2 DD3 DD4 DD5

High-level logic input, PWRKIN, SEL, CONT

Low-level logic input, PWRKIN, SEL, CONT

High-level logic input, PSH and CE

Low-level logic input, PSH and CE

Precharge current

0.7V

DD1

V

DD1

GND

0.7V

0.3V

V

DD1

V

REG1

GND

0.3V

REG1

V

100

mA

°C

Operating free-air temperature, T

–40

85

A

logic level output

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V

OH

V

OL

V

OL

V

OH

V

OL

of terminals PWRKOUT, IRQ, CE

I

= –2 mA

= 2 mA

0.8V

REG1

V

REG1

V

OH

OL

OH

OL

of terminals PWRKOUT, IRQ, CE

GND

0.22V

REG1

0.22V

REG1

of DATA

of XRST

= –2 mA (open drain with 100 kΩ internal pullup)

= 2 mA (open drain 100 kΩ internal pullup)

V

REG1

GND

0.22V

REG1

10

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ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

electrical characteristics, T = –25°C to 85°C (unless otherwise noted)

A

regulator 1 (C = 4.7 µF with ESR = 2 Ω)

O

PARAMETER

TEST CONDITIONS

MIN

3.3

TYP

MAX

4.3

UNIT

V

Input voltage

DD1

Output voltage

Output current

Short circuit

I

= I

MAX

2.68

2.8

2.91

150

550

80

V

REG1

O

I

V

= 3.8 V

mA

mV

dB

O

DD1

OS

DD1

Load regulation

Line regulation

Dropout voltage

Ripple rejection

Standby current

I

O

= 1 mA to I = 3.8 V

, V

MAX DD1

V

= 3.3 V to 4.3 V, I = I

O

20

DD1

MAX

I

O

= I

MAX

100

65

300

PSRR

f = 10 Hz to 10 kHz, V

= 3.8 V

= 1.5 mA (regulator 1 and internal bias circuitry are active)

O

DD1

I

105

120

µA

(Standby)

regulator 6 (C = 4.7 µF with ESR = 2 Ω)

O

2

This 100-mA LDO can be enabled with serial interface I C or by CONT (terminal 21 or H6). The output range

is from 2.5 V to 3 V.

PARAMETER

TEST CONDITIONS

MIN

3.3

2.88

0.96V

TYP

MAX

4.3

3.12

UNIT

V

Input voltage

DD2

CONT = Low

CONT = High (see Note 1 and function register 4)

3

V

Output voltage

REG6

V

p

1.04V

V

p

I

Output current

Short circuit

100

mA

mV

dB

µs

O

330

70

Load regulation

Line regulation

Dropout voltage

Ripple rejection

Turnon time

I

= 1 mA to I = 3.8 V

, V

O

MAX DD2

V

= 3.3 V to 4.3 V, I = I

O MAX

20

S

DD2

I

O

= I

MAX

100

65

300

PSRR

f = 10 Hz to 10 kHz, V

= 3.8 V

DD2

t

I

See Note 2

150

5

ON

Turnoff time

See Note 3

2

ms

µA

OFF

Quiescent current

I

O

= 1.5 mA

15

30

(Quiescent)

2

NOTES: 1. I C/SPI programmable, V is the programmed voltage. Refer to function registers 2 and 3 for programming information.

(p)

2. Output enable to output voltage = 0.9 × nominal value

3. Output disable to output voltage = 0.5 V

11

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

electrical characteristics, T = –25°C to 85°C (unless otherwise noted) (continued)

A

regulators 2, 3, 4, and 5 (C = 4.7 µF with ESR = 2 Ω)

O

Regulators 2, 3, 4, and 5 provide programmable output. The output range, 2.3 V to 3 V, can be programmed

in 100-mV steps.

PARAMETER

Input voltage

TEST CONDITIONS

MIN

3.3

0.96V

TYP

MAX

4.3

1.04V

UNIT

V

I

Output voltage

See Note 1

Regulator 2

Regulator 3

Regulator 4

Regulator 5

Regulator 2

Regulator 3

Regulator 4

Regulator 5

V

p

V

O

p

80

I

O

Output current

mA

120

150

300

400

500

70

Short-circuit current

Load regulation

mA

mV

Regulator 2, I = 1 mA to I

O

MAX

Regulator 4, I = 1 mA to I

O

50

MAX

Regulators 3 and 5, I = 1 mA to I

MAX

50

O

Line regulation

Dropout voltage

Ripple rejection

Output noise

V = 3.3 V to 4.3 V

20

mV

dB

I

V

I = I

O MAX

300

DROPOUT

PSRR

N

f = 10 Hz to 10 kHz, V

DD3

= V

DD4

= 3.8 V

65

45

f = 10 Hz to 100 kHz, I = I

, V = 3.3 V

MAX

µVrms

µs

O

I

t

I

Turnon time

See Note 2

80

5

ON

Turnoff time

No load, See Note 3

1

ms

OFF

Quiescent current

I

O

= 1 mA

120

150

µA

(Quiescent)

regulator 1 voltage DET

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

≤ V

–V

0

0.3

REG1

TH HY

V

Voltage at XRST (see Note 4)

V

O

≥ V

V

REG1

TH

REG1

100

Hysteresis voltage

80

120

1.25

1.3

mV

V

HY

Time delay voltage at CD1

Time delay current at CD1

1.15

0.7

1.2

1

µA

NOTE 4:

V

TH

is 90% of the nominal V

.

REG1

LED driver

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

160

20

UNIT

mA

µA

Output current at IL0

V

= 0.8 V

IL0

IL1

IL2

Output current at IL1

Output current at IL2

Leakage current

10

I

Off

1

LKG

12

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ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

electrical characteristics, T = –25°C to 85°C (unless otherwise noted) (continued)

A

vibrator driver

PARAMETER

Input voltage

TEST CONDITIONS

MIN

3.3

TYP

MAX

4.3

3.12

85

UNIT

V

DD5

Output voltage

Output current

Output voltage

Output current

Line regulation

Load regulation

Quiescent current

Current limit

SEL = H

SEL = L

2.88

3

V

O

I

O

mA

V

O

1.17

1.3

1.43

140

20

I

O

mA

mV

µA

mA

V

S

V

= 3.3 V to 4.3 V, I

= I

DD5

OUT

OUT MAX

I

= 1 mA to I , V = 3.8 V

MAX DD5

= 0

80

I

80

(Quiescent)

V

O

= 0, V

DD5

= 3.3 V to 4.3 V

490

L

ring driver

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ω

On resistance

Leakage current

I

= 100 mA at 25°C

3

1

OUT

Off

I

µΑ

LKG

battery charger control

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

input

4.2

4.059

4.158

6.5

V

CHG

V

= 4.1 V

4.1 4.141

4.2 4.242

BREG

V

System V

DD

V

DD1

= 4.2 V (see function control register)

BREG

Required 0.1-µF capacitor ESR of 2 Ω , load = 1 mA

maximum

2.91

3

3.09

REF

Set maximum current, 100 to 200, 20-mV steps with

I C, See CSV register

Current sense voltage

V

mV

(current sense)

SENSE

2

VGH

VGL

IGH = 0 mA

IGL = 0 mA

V

CHG

0

V

VG

IGH

149

214

178.5

218

197

226

IG

VG = 2 V

µA

V

IGL

VG2H

VG2L

IG2H

IG2L

VG3H

VG3L

IG3H

IG3L

IG2H = 0 mA

IG2L = 0 mA

V

BAT

0

VG2

IG2

VG3

IG3

VG2 = V

BAT

– 0.3 V

–2.8

–4.03 –4.65

mA

V

VG2 = 0.3 V

IG3H = 0 mA

IG3L = 0 mA

3.2

5.02

5.70

V

DD1

0

VG3 = V

DD1

–2.7

–3.87 –4.65

4.43 5.3

mA

VG3 = 0.3 V

2.95

13

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

electrical characteristics, T = –25°C to 85°C (unless otherwise noted) (continued)

A

battery charger control (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

†

V

= 4.1 V

4.059

4.158

4.1 4.141

4.2 4.242

1.9

BREG

V

BAT

regulation (CV)

V

= 4.2 V

BREG

Low voltage cutoff

High voltage cutoff

Fast charge voltage

Precharge voltage

Pack wake-up voltage

Operating current

4.45

3.2

V

BAT

(see Note 5)

1.9

2.05

2.2

4.214

4.30 4.386

20

I

mA

CC

†

V

is the regulated battery voltage programmed by setting bit 1 of CSV register.

BREG

V

PRE

NOTES: 5. Precharge current set by I

+

45

where V

+ 1.2 V " 10%

PRE

R

PR

ADC specification

PARAMETER

Resolution

TEST CONDITIONS

Output impedance <100 kΩ

MIN

TYP

MAX

UNIT

bit

8

Integral nonlinearity

Low-level input

Confirm monotonous (see Note 6)

ADC output = 00H

–1

0

1

LSB

V

0.1

2.1

High-level input

ADC output = FFH

1.9

2

3

V

Input capacitance

ADC CLK

pF

450

500

16

550

10

kHz

CLK

µs

AD conversion time, t

Power-up time

From the start of SETUP

C

From the ADEN up selection

2V

255

NOTE 6: LSB +

+ 7.8 mV

DISB interface

2

The TWL2214CA device supports both I C bus and SPI bus serial interfaces. The interface uses serial data

(DATA) and serial clock (CLK) to carry information between the devices. The CE terminal (A8) in the GQE

2

package selects I C or SPI. The device that initiates a transfer, generates clock signals, and terminates a

transfer is the master. The TWL2214CA device operates as a slave device. The slave address for this device

is fixed at E4h for write operations and E5h for read operations. The LSB of this slave address is simply an R/W

flag. DATA is a bidirectional line connected to V

via a 10-kΩ pullup resistor. Data can be transferred at a

REG1

2

rate up to 400K bits/s for I C and up to 2M bits/s for SPI with one clock pulse generated for each data bit

transferred. MSB is transferred first. When the bus is free, both DATA and CLK are high. Data transfer can only

be initiated when the bus is free. The bus must return to the free state when the transfer is complete. Failure

to return to the free state may cause an error.

14

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ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

SPI bus protocols

The TWL2214CA serial bus is SPI-compatible when a negative transition is generated on the CE input (A8) in

the GQE package.

2

Unlike I C, in this mode, the slave device does not send an acknowledge bit for all data received. The data frame

includes 2 start bits, 1 byte of slave address, 1 byte of register address, 1 byte of data, and half clock cycle of

th

hold time. The total frame length, therefore, includes 26 full clock cycles and the rising edge of the 27 clock

th

cycle. After the rising edge of the 27 clock cycle, CLK remains high.

The following requirements must be satisfied for the interface:

1. CE goes low after the falling edge of CLK and remains low for no longer than 35 clock cycles. The data line

2

must remain unchanged prior to the initial trailing edge of the CLK line. Failure to comply triggers the I C

start condition and the SPI interface fails.

2. Input data is sampled on the rising edge of the CLK when CE is set to low.

th

3. Input data is latched into the device on the last (26 ) rising edge of the CLK.

4. If CE goes high before completing the transmission, data is ignored and the register is not updated.

5. Output data is updated on the falling edge of the CLK when CE is set to low.

6. The first two bits in the data line are dead bits to allow enough time for the communication mode option

selection of the SPI.

7. During a read operation the direction of data line changes after the register address is received.

15

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

SPI bus protocols (continued)

t

CLK

t

SUCE

CLK

CE

t

or t

CE

CLKH

t

CLKL

CLK

DATA

SPI1

SPI0

CE

t

TD

t

HDIN

t

SUDIN

CLK

t

HCE

CE

DATA

DATA IN

CLK

t

HDO

CLK

DATA – MSB

DATA

DATA OUT

DATA

Figure 5. SPI Protocol Timing

CE

CLK

SPI[1–0] SA7 SA6 SA5 SA4 SA3 SA2 SA1 R/W A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

DATA

DISB_SPI

Format

Start when CE goes low

SPI[1–0]

Slave Address [7–0]

Register Address [7–0]

Data [7–0]

Ignore data while CE is low

Stop when CE goes high

One Cycle

Figure 6. SPI Read and Write

16

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ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

SPI timing requirements (see Figure 5)

PARAMETER

MIN

500

200

5

MAX

UNIT

ns

t

Clock period

CLK

CLKL

CLKH

TD

Clock low time

ns

Clock high time

ns

Interframe transfer delay

CE low transition period

Clock enable setup time

Clock enable hold time

Input data setup time

Input data hold time

Output data hold time

Clock or data rise time

Clock or data fall time

t

CLK

27

35

CE

CLK

ns

50

SUCE

HCE

SUDIN

HDIN

HDO

r

0

ns

50

t

–50

t

CLK

20

f

17

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

2

I C bus protocols

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are

reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable

whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a

start condition and terminated with a stop condition. When addressed, the TWL2214CA device generates an

acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra

clock pulse that is associated with the acknowledge bit. The TWL2214CA device must pull down the DATA line

during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the

acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock

pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end

of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In

this case, the slave TWL2214CA device must leave the data line high to enable the master to generate the stop

condition.

DATA

CLK

Data line

stable;

data valid

Change

of data

allowed

2

Figure 7. Bit Transfer on the I C Bus

18

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ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

2

I C bus protocols (continued)

CE

DATA

CLK

S

P

START Condition

STOP Condition

Figure 8. START and STOP Conditions

CE

CLK

DATA

Start

A6

A5

A4

A0 R/W ACK

R7

R6

R5

R0 ACK

0

D7

D6

D5

D0 ACK

0

Stop

Slave Address

Register Address

Data

NOTE: SLAVE = TWL2214CA

2

Figure 9. I C Bus Write to TWL2214CA Device

CE

CLK

A6 A5

A0 R/W ACK

R7 R6

R0 ACK

A6

A0 R/W ACK D7 D6

D0 ACK

DATA

Start

1

0

1

0

Slave

Drives

Stop

Master

Drives

ACK and Stop

Slave Address

Register Address

Slave Address

the Data

Repeated

Start

NOTE: SLAVE = TWL2214CA

2

Figure 10. I C Read From TWL2214CA Protocol A

19

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

2

I C bus protocols (continued)

CE

CLK

DATA

A0 R/W ACK D7

D0 ACK

A6 A5

A0 R/W ACK

R7 R6

R0 ACK

A6 A5

1

0

Start

Stop

Master

Drives

Stop Start

Slave

Drives

the Data

Slave Address

Register Address

Slave Address

ACK and Stop

NOTE: SLAVE = TWL2214CA

2

Figure 11. I C Read From TWL2214CA Protocol B

2

I C timing

DATA

t(

BUF)

t

h(STA)

t

(LOW)

t

f

r

CLK

t

su(STO)

h(STA)

(HIGH)

su(STA)

t

h(DATA)

su(DATA)

STO

STA

STO

MIN

MAX

UNIT

kHz

ns

Clock frequency, f

400

MAX

Clock high time, t

600

wH(HIGH)

Clock low time, t

1300

ns

wL(LOW)

DATA and CLK rise time, t

300

ns

R

DATA and CLK fall time, t

ns

F

Hold time (repeated) START condition (after this period the first clock pulse is generated), t

h(STA)

600

0

ns

Setup time for repeated START condition, t

h(DATA)

ns

Data input hold time, t

h(DATA)

ns

Data input setup time, t

su(DATA)

100

600

1300

ns

STOP condition setup time, t

su(STO)

ns

Bus free time, t

(BUF)

ns

2

Figure 12. I C Bus Timing Diagram

20

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ꢀ ꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢇ

ꢈꢉ ꢁ ꢊꢋ ꢌꢍꢈ ꢈꢂꢎ ꢏ ꢇꢐꢇꢑ ꢊꢏ ꢊꢐ ꢀ ꢒ ꢆ ꢇ ꢐꢓ

ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

DC Input

4.5 V to 6.0 V

Q1

R_SENSE1

0.2 Ω

ZXM64P02X

5

C1

0.1 µF

3

2

1

6

7

8

S

D

R1

1 MΩ

4

G

Q2:1

S 1

Q2:2

R2

100 kΩ

8 D

7 D

D

6

5

SI9934DY

4 G

SI9934DY

G 2

R3

1 kΩ

R4

1.2 kΩ

C3

RT1

3.74 kΩ

Battery Pack

NTC

C2

1 µF

470 pF

RT2

6.19 kΩ

C4

4.7 µF

D1

– Vibrator +

24

23

22

21

20

19

18

17

16

15

14

13

37

38

39

40

41

42

43

44

45

46

47

48

PWRKOUT

TS

ADCIN1

ADCIN2

CONT

To V

or GND

DD

PWRKIN

PSH

S1

DATA

CLK

CD2

V

REG5

U2

TWL2214CA

V

DD4

DGND

VIOUT

V

REG4

BGRF

R5

10 kΩ

V

DD5

C5

4.7 µF

GND2

RINGOUT

RINGIN

GND3

V

REG3

V

DD3

V

REG2

C13

0.001 µF

C6

R6

10 kΩ

C10

0.1 µF

C9

0.1 µF

4.7 µF

C12

C11

0.1 µF

4.7 µF

C8

0.1 µF

C7

4.7 µF

EXT_CONTROLLER

C14

IRQ

PWRKOUT

PSH

0.01 µF

DATA

CLK

RST

To V

or GND

DD

C17

0.1 µF

C18

0.1 µF

R7

R9

100 kΩ

C15

4.7 µF

C16

4.7 µF

To

V

DD

R8

V

DD

or

+

–

R10

Buzzer

GND

VREG1

C19

0.1 µF

Figure 13. Typical Application Circuit (PFB)

23

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

DC Input

4.5 V to 6.0 V

Q1

R_SENSE1

0.2 Ω

ZXM64P02X

5

C1

0.1 µF

3

2

1

6

7

8

S

D

R1

1 MΩ

4

G

Q2:1

S 1

Q2:2

R2

100 kΩ

8 D

7 D

D

6

5

SI9934DY

4 G

SI9934DY

G 2

R3

1 kΩ

R4

1.2 kΩ

C3

RT1

3.74 kΩ

Battery Pack

NTC

C2

1 µF

470 pF

RT2

6.19 kΩ

C4

4.7 µF

D1

– Vibrator +

H8

B7

A7

B6

A6

B5

A5

A4

B4

A3

B3

A2

B2

PWRKOUT

TS

ADCIN1

ADCIN2

CONT

To V

or GND

DD

J8

J7

H6

J6

J5

H5

J4

H4

J3

J2

H2

PWRKIN

PSH

S1

DATA

CLK

CD2

V

REG5

U2

TWL2214CA

V

DD4

DGND

VIOUT

V

REG4

BGRF

R5

V

DD5

C5

GND2

RINGOUT

RINGIN

GND3

V

10 kΩ

REG3

4.7 µF

V

DD3

V

REG2

C13

0.001 µF

C6

0.1 µF

R6

10 kΩ

C10

0.1 µF

C9

4.7 µF

C12

C11

0.1 µF

4.7 µF

C8

0.1 µF

C7

4.7 µF

EXT_CONTROLLER

C14

IRQ

PWRKOUT

PSH

0.01 µF

DATA

CLK

CE

RST

To V

or GND

DD

C17

0.1 µF

C18

0.1 µF

R7

R9

100 kΩ

C15

4.7 µF

C16

4.7 µF

To

V

DD

R8

V

DD

or

+

–

R10

Buzzer

GND

VREG1

C19

0.1 µF

Figure 14. Typical Application Circuit (GQE)

24

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ꢈꢉ ꢁ ꢊꢋ ꢌꢍꢈ ꢈꢂꢎ ꢏ ꢇꢐꢇꢑ ꢊꢏ ꢊꢐ ꢀ ꢒ ꢆ ꢇ ꢐꢓ

ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

device power supply control (V

)

DD1

The TWL2214CA device receives device power by regulating the V

input to 4.1 V or 4.2 V, whenever V

CHG

is available; otherwise, the device uses the V

2

input directly as device dc supply. The regulated voltage from

BAT

V

is programmable through the I C interface.

CHG

RS

V

CHG

+

V

BAT

VG3

VG

VG2

–

V

+

_

BG

DD

V

DD

Control

Logic

Decode

R1

R2

V

DD1

TWL2214CA

BG: Band Gap Voltage

R1: Fixed

R2: Programmable

Figure 15. Device Power Supply

Condition 1:

V

is on (VG = Active, VG2 = On, VG3 = Off)

CHG

+ 4.1 V or 4.2 V

DD1

The TWL2214CA device sets R2 value according to the programmed voltage level (4.1 V or 4.2 V).

Condition 2:

V

is off and V

applied (VG = High, VG2 = Off, VG3 = On)

CHG

BAT

+ VBAT

DD1

battery charger

The TWL2214CA device provides a charger function for single cell Li-Ion battery packs. The charging activity

starts with the battery pack wake-up cycle. If the wake-up cycle completes successfully, the charger starts the

precharge function and slowly charges the battery to 3.2 V. If the battery is charged to 3.2 V within the time limit,

the charger goes into the fast charge mode. The fast charge mode has two phases: 1) constant current (CC)

mode and 2) constant voltage (CV) mode. The charger starts CC mode with the maximal charging current until

the battery voltage reaches the regulated voltage level; the charger is then switched to CV mode. During the

CV mode, the TWL2214CA device monitors the charging current; once it is below the programmed termination

current level, the charger activity is terminated. The termination current level can be programmed at 10%, 20%,

30%, 40%, or 50% of the maximum charging current at the CC mode.

25

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ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

Non-Charging

Power Up

V

CHG

V

CHG

< 4.5 V or

> 6.5 V

Mode

4.5 V ≤ V

CHG

≤ 6.5 V

XRST = Low or CHGSTR = Low

Standby

XRST = High and CHGSTR = High

V

BAT

≥ 4.3 V

V

BAT

< 2.0 V or V > 4.45 V

BAT

Wake Up

V

BAT

ꢀ 3.2 V

V

BAT

< 3.2 V

V

BAT

< 3.2 V

Temperature

Out of Range

Time-Out or

> 4.45 V

Precharge

V

BAT

Temperature In Range

V

BAT

≥ 3.2 V

V

BAT

< 4.1 V or 4.2 V

Temperature Out of Range

Charge

Suspended

CC Time-Out or

> 4.45 V

Terminate

Charge

Fast-Charge

CC Mode

Temperature In Range

V

BAT

Temperature Out of Range

Temperature In Range

V

BAT

≥ 4.1 V or 4.2 V

V

BAT

> 4.45 V

Fast-Charge

CV Mode

Temperature Out of Range

I

> I

CHG TERMINATE

I

≤ I or

CHG TERMINATE

and not CV Time-Out

CV Time-Out

Charge

Complete

Figure 16. Charger State Diagram

26

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ꢈꢉ ꢁ ꢊꢋ ꢌꢍꢈ ꢈꢂꢎ ꢏ ꢇꢐꢇꢑ ꢊꢏ ꢊꢐ ꢀ ꢒ ꢆ ꢇ ꢐꢓ

ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

control register—FCR1 (1BH)

BIT

NAME

CHGSTR

DESCRIPTION

7

Set this bit to 1 to start the charger operation. This bit is cleared if the charger is terminated. (Refer to

status register table below for terminated conditions)

6

5

4

3

2

1

0

ADC ENABLE

ADC FUNCTION

ADBV

Set this bit to 1 to enable ADC operation, 0 to stop.

Set this bit to 1 to have ADC operate continuously. Set to 0 to have ADC to operate one cycle only.

Set this bit to 1 to enable the V

BAT

input channel to ADC. Clear this bit to 0 to disable the input channel.

VTS

Set this bit to 1 to enable the VTS input channel to ADC. Clear this bit to 0 to disable the input channel.

Set this bit to 1 to enable the ADCIN1 input channel.

ADCIN1

ADCIN2

IRQ

Set this bit to 1 to enable the ADCIN2 input channel.

Status of IRQ terminal (refer to IRQ operation section).

ADC has four input channels (ADBV, VTS, ADCIN1, and ADCIN2). Each channel can be enabled or disabled

individually. The selected channel must be enabled before ADC FUNCTION and ADC ENABLE bits are

enabled, the channel is included in the ADC operation.

IRQ control/status

The TWL2214CA device uses IRQ signal to inform the external controller about the exception condition of the

input and the charger status. Bit 0 reflects the state of the IRQ signal. IRQ occurs in the following five

V

CHG

conditions:

1.

2.

V

returns to operating range from nonoperating range.

goes out of range from operating range.

CHG

3. Battery error—occurs only during the charging cycle.

4. Battery temperature out of range—occurs only during the charging cycle. The charger is suspended

temporarily. IRQ is cleared when the temperature returns to normal and the charger resumes automatically.

5. Charge complete.

The controller must clear the IRQ signal by writing 0 to bit 0 in the interrupt service routine, except in the VBOT

condition. The controller may miss the next interrupt if it fails to write the 0. In the VBOT condition, the

TWL2214CA device clears the IRQ when the condition goes away.

27

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ꢈ ꢉꢁ ꢊꢋ ꢌꢍ ꢈꢈꢂꢎ ꢏꢇ ꢐꢇꢑ ꢊ ꢏꢊ ꢐꢀ ꢒ ꢆ ꢇꢐ ꢓ

ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

status register description—SR (1CH)

SR shows the status of the charger. The external controller reads the SR to track the state of the charging

condition.

BIT

7

NAME

Vext

DESCRIPTION

When Vext = 1, the V

CHG

input is in the operating range. Otherwise the V

is out of range.

CHG

6

BATERR

This bit is set to 1 indicating battery error. Four cases cause battery error: precharge timeout, constant-current mode

timeout, V < 2.9 V, or V > 4.45 V.

BAT BAT

5

VBOT

During the charging cycle, if the battery temperature exceeds or falls below the nominal range, this sets to 1. The

charger is suspended temporarily. VBOT is cleared when the temperature returns to nominal range and the charger

function resumes automatically.

4

3

CTERM

NOCHG

The charger is terminated normally because the charging current is below the preset termination current value.

No charge condition. This condition is detected only during the wake-up state of the charging function. After the

8-second wake-up period expires, if V

BAT

is above 4.3 V, the NOCHG flag is set. The cause of this is a missing or

completely charged battery. The TWL2214CA device does not deactivate the charger by setting CHGSTR = 0. The

external processor must turn off the CHGSTR bit by setting it to 0.

2

1

PCHG

CCTO

Set to 1 to indicate the charger is in precharge state.

Set to 1 to indicate the charging time has exceeded the time limit allowed during CC mode. This is a fatal error. The

TWL2214CA device clears CHGSTR bit, sets the BATERR flag, and makes IRQ go high to interrupt the external

controller.

0

TCTO

Set to 1 to indicate the charging time has exceeded the overall time limit allowed during CV mode. This is treated

as normal termination of the charger function. The TWL2214CA device clears bit 7 (CHGSTR) of the control register

and sets IRQ to 1 to interrupt the external controller.

28

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ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

IRQ

No

V

out of

Bound

CHG

VEXT=1

Yes

1

No

Yes

Display Error

Message

BATTERR=1

Yes

No

NOCHG=1

1

Yes

No

VBOT

Set CHGSTR

to 0

No

Yes

Return

CTERM

1

Yes

Charge

TCTO

Complete

No

1

Set IRQ1

to 0

Return

Figure 17. Charger State Diagram

29

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ꢈ ꢉꢁ ꢊꢋ ꢌꢍ ꢈꢈꢂꢎ ꢏꢇ ꢐꢇꢑ ꢊ ꢏꢊ ꢐꢀ ꢒ ꢆ ꢇꢐ ꢓ

ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

battery pack wake-up

Li-Ion cells can be easily damaged by overcharging or overdischarging. To prevent damage, a pack-protector

device is used within the battery pack. During the charging cycle, if the pack-protector senses an over-voltage

condition, it disconnects the pack from the charger to prevent further charging but allows discharging. During

the discharging cycle, if the protector senses an under-voltage condition, it disconnects the cell from the load

to prevent further discharging.

This phase of the charging cycle provides a wake-up capability for the battery pack with a pack-protector device.

At the start of the charge cycle, the TWL2214CA device provides a wake-up signal of 1 mA and 4.3 V to the

battery pack. At the end of the 8-second time limit, if the battery pack voltage remains at 4.3 V, a no-battery flag

is set in the status register to signal the condition that the charging path is open. If the battery voltage is below

2.5 V, a BATTERR flag is set in the status register to signal a bad battery cell. In either case, the charging activity

is halted.

V

CHG

_

+

V

DD1

1 mA

No Battery

_

+

BG

V

BAT

+

Wake-Up

Enable

Battery

R1

R2

–

Control

Logic

TWL2214CA

BG = 1.2 V

R1 + R2

BG ×

= 4.3 V

R2

Figure 18. Battery Pack Wake Up

precharge

The TWL2214CA device starts the precharge phase when the battery voltage is less than 3.2 V. The precharge

time is limited by the PTR timer. The precharge current level is set by an external resistor. The maximum

precharge current the charger can supply is 100 mA. Use the following equation to choose the external resistor

value.

V

PRE

R

+

45, V

+ 1.2V " 10%

PRE

PR

I

PRE

Where:

R

= External resistor

= Desired precharge current

= Voltage at RPRE terminal

PR

I

V

PRE

30

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ꢈꢉ ꢁ ꢊꢋ ꢌꢍꢈ ꢈꢂꢎ ꢏ ꢇꢐꢇꢑ ꢊꢏ ꢊꢐ ꢀ ꢒ ꢆ ꢇ ꢐꢓ

ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

Rsense

Active

VG

ON

VG2

OFF

DC Input

+

–

V

CHG

V

BAT

VG3

ISENSE

V

DD

Voltage and

Current Regulation

Logic

Constant

Current

Source

Switch

Control

RPRE

R

PR

Precharge Path

TWL2214CA

Figure 19. Precharge Functional Diagram

fast charge constant current (CC mode)

When the battery voltage is 3.2 V or higher, the TWL2214CA device starts the fast charge CC mode cycle. In

CC mode, the charger regulates the charging current to its maximum level. The maximum charging current

(I

) is determined by the external sense resistor, R

, and the voltage, V

. V

, is programmable

MAX

SENSE

SENSE SENSE

2

through the I C interface (refer to CSV register for programming information). The range of V

100 mV to 200 mV, in 20-mV steps. The CC mode charge time is limited by the CCTR timer.

is from

SENSE

V

SENSE

I

+

MAX

R

SENSE

fast charge constant current (CV mode)

When the cell reaches the constant voltage phase, the charger switches to the fast charge CV mode. The

charging current begins tapering down while the charging voltage is regulated at the programmed voltage level

(4.1 V or 4.2 V). The CV mode charging is limited by the TCTR timer.

Fast Charge Path (CC, CV)

Rsense

Active

ON

DC Input

+

V

CHG

V

BAT

ISENSE

VG

VG3

–

VG2

V

DD

Voltage and

Current Regulation

Logic

Switch

Control

TWL2214CA

Figure 20. Fast Charge Functional Diagram

31

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ꢈ ꢉꢁ ꢊꢋ ꢌꢍ ꢈꢈꢂꢎ ꢏꢇ ꢐꢇꢑ ꢊ ꢏꢊ ꢐꢀ ꢒ ꢆ ꢇꢐ ꢓ

ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

current termination

During the CV mode, the charge cycle is terminated when the charging current is under the programmed

terminated level or when the total charge timer (TCTR) times out. The terminated current level can be

programmed to 10%, 20%, 30%, 40%, or 50% of the charging current at CC mode.

temperature monitoring

The TWL2214CA device monitors the battery temperature throughout the charge cycle. The input for ADC

reference voltage is generated by a negative temperature coefficient (NTC) thermistor. The TWL2214CA device

compares the ADC input reference voltage to the programmed threshold voltages to determine if charging is

allowed. Three required thresholds are:

D

VBOTRH+ Voltage for over-temperature cutoff; charging is suspended.

VBOTRH– Voltage to resume charging function for over-temperature cutoff.

VBOTRL Voltage for low-temperature cutoff; charging is suspended.

Ts (V)

2 V

VBOTRL

VBOTRH–

VBOTRH+

0 V

Charge Condition

Enable

Disabled

Enabled

Disabled

Enabled

Figure 21. Temperature Monitoring

NOTE: The power-up default values are zero for these three thresholds. If the user opts not to use the temperature monitoring function during

the charge cycle, the TS terminal of the device must be tied to GND to avoid an error signal.

32

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ꢀ ꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢇ

ꢈꢉ ꢁ ꢊꢋ ꢌꢍꢈ ꢈꢂꢎ ꢏ ꢇꢐꢇꢑ ꢊꢏ ꢊꢐ ꢀ ꢒ ꢆ ꢇ ꢐꢓ

ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

APPLICATION INFORMATION

maximum time out

The TWL2214CA device provides three timers for maximal time allowed for charging. The time is programmable

2

through I C interface.

TIMER DESCRIPTION

RANGE

STEP

COMMENT

PTR–Precharge timer

0–136 min

4 min

During the precharge cycle, if the timer expires before the precharging activity is

complete, a BATT_ERR flag is set in the status register, and the charge is

terminated.

CCTR–CC charge timer

TCTR–total charge timer

0–274 min

0–15 hr

8 min

1 hr

During the CC mode cycle, if the timer expires before the CC activity is complete,

a BATT_ERR flag is set in the status register, and the charge is terminated.

Total charge time is defined as the total charge time of CC mode and CV mode.

TCTR time-out occurs only in the CV mode. If the timer expires before, the charge

is complete.

33

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ꢈ ꢉꢁ ꢊꢋ ꢌꢍ ꢈꢈꢂꢎ ꢏꢇ ꢐꢇꢑ ꢊ ꢏꢊ ꢐꢀ ꢒ ꢆ ꢇꢐ ꢓ

ꢂ ꢔ ꢕꢒ ꢖ ꢗ ꢘ ꢇꢀ ꢀ ꢊꢋꢎ ꢆꢙ ꢇꢋꢑ ꢊ ꢆꢉ ꢐꢀ ꢋꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

MECHANICAL DATA

GQE (S-PBGA-N80)

PLASTIC BALL GRID ARRAY

5,10

SQ

4,00 TYP

4,90

0,50

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9

0,68

0,62

1,00 MAX

Seating Plane

0,08

0,35

0,25

0,05

M

0,21

0,11

4200461/C 10/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. MicroStar Junior BGA configuration

D. Falls within JEDEC MO-225

MicroStar Junior is a trademark of Texas Instruments.

34

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ꢀ ꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢇ

ꢈꢉ ꢁ ꢊꢋ ꢌꢍꢈ ꢈꢂꢎ ꢏ ꢇꢐꢇꢑ ꢊꢏ ꢊꢐ ꢀ ꢒ ꢆ ꢇ ꢐꢓ

ꢂ ꢔꢕꢒ ꢖꢗ ꢘꢇꢀ ꢀꢊ ꢋꢎ ꢆꢙꢇ ꢋꢑ ꢊ ꢆ ꢉꢐ ꢀꢋ ꢉ ꢂ

SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–ā7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

35

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IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

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parameters of each product is not necessarily performed.

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Post Office Box 655303

Dallas, Texas 75265


型号：	TWL2214CAPFB
厂家：	TEXAS INSTRUMENTS
描述：	1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48, PLASTIC, TQFP-48
文件：	总36页 (文件大小：503K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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