TXS0108EQPWRQ1 [TI]
面向漏极开路和推挽应用的 8 位双向电压电平转换器 | PW | 20 | -40 to 125;
| 型号： | TXS0108EQPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 面向漏极开路和推挽应用的 8 位双向电压电平转换器 | PW | 20 | -40 to 125 光电二极管 接口集成电路 转换器 电平转换器 |
| 文件： | 总29页 (文件大小：1094K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
TXS0108E-Q1面向开漏和推挽应用的
8 位双向电压电平转换 转换器
1 特性
3 说明
1
•
符合汽车类应用的 AEC-Q100 标准
这款 8 位非反向转换器使用两个独立的可配置电源
轨。A 端口跟踪 VCCA 引脚的电源电压。VCCA 引脚可
接受 1.4V 到 3.6V 范围内的任意电源电压。B 端口跟
踪 VCCB 引脚的电源电压。VCCB 引脚可接受 1.65V 到
5.5V 范围内的任意电源电压。这两个输入电源引脚可
实现 1.5V、1.8V、2.5V、3.3V 和 5V 电压节点之间的
任意低压双向转换。
–
–
器件温度等级 1：-40°C 至 125°C
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
–
器件组件充电模式 (CDM) ESD 分类等级 C6
•
•
无需方向控制信号
最大数据速率
–
–
110Mbps（推挽）
1.2Mbps（开漏）
输出使能 (OE) 输入为低电平时，所有输出均将置于高
阻抗 (Hi-Z) 状态。
•
A 端口 1.4V 至 3.6V；B 端口 1.65V 至 5.5V (VCCA
≤ VCCB
为确保输出在上电或断电期间处于 Hi-Z 状态，需通过
一个下拉电阻将 OE 接至 GND。该电阻的最小值取决
于驱动器的拉电流能力。
)
•
•
无需电源排序 - VCCA 或 VCCB 均可优先斜升
锁断性能超过 100mA，符合
JESD 78 II 类规范的要求
.
•
静电放电 (ESD) 保护性能超过 JESD 22 规范的要
求（A 端口）
器件信息(1)
–
–
2000V 人体放电模式 (A114-B)
1000V 充电器件模型 (C101)
器件型号
封装
封装尺寸（标称值）
TXS0108E-Q1
TSSOP (20)
6.50mm x 6.40mm
•
IEC 61000-4-2 ESD（B 端口）
(1) 如需了解所有可用封装，请参见数据表末尾的可订购产品附
录。
–
–
±8kV 接触放电
±6kV 气隙放电
.
.
2 应用
•
汽车
简化应用
1.8 V
3.3 V
0.1 mF
0.1 mF
VCCA
VCCB
OE
1.8-V
System
3.3-V
System
Controller
Controller
A1
A2
A3
A4
A5
A6
A7
A8
TXS0108E-Q1
B1
B2
B3
B4
B5
B6
B7
B8
Data
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCES861
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
目录
7.1 Load Circuits ........................................................... 13
7.2 Voltage Waveforms................................................. 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions ...................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics .......................................... 6
6.6 Timing Requirements: VCCA = 1.5 V ± 0.1 V ............ 6
6.7 Timing Requirements: VCCA = 1.8 V ± 0.15 V .......... 7
6.8 Timing Requirements: VCCA = 2.5 V ± 0.2 V ............ 7
6.9 Timing Requirements: VCCA = 3.3 V ± 0.3 V ............ 7
6.10 Switching Characteristics: VCCA = 1.5 V ± 0.1 V .... 8
6.11 Switching Characteristics: VCCA = 1.8 V ± 0.15 V .. 9
6.12 Switching Characteristics: VCCA = 2.5 V ± 0.2 V .. 10
6.13 Switching Characteristics: VCCA = 3.3 V ± 0.3 V .. 11
6.14 Typical Characteristics.......................................... 12
Parameter Measurement Information ................ 13
8
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 器件和文档支持 ..................................................... 21
12.1 社区资源................................................................ 21
12.2 商标....................................................................... 21
12.3 静电放电警告......................................................... 21
12.4 Glossary................................................................ 21
13 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
Changes from Original (June 2015) to Revision A
Page
•
已更改引脚功能 ...................................................................................................................................................................... 1
2
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
5 Pin Configuration and Functions
PW PACKAGE
20-PIN TSSOP
(TOP VIEW)
A1
B1
20
1
2
3
4
5
6
7
8
9
10
V
VCCB
19
18
17
16
15
14
13
12
11
CCA
A2
A3
A4
A5
A6
A7
A8
OE
B2
B3
B4
B5
B6
B7
B8
GND
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
A1
NO.
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
Input/output 1. Referenced to VCCA
A2
3
Input/output 2. Referenced to VCCA
Input/output 3. Referenced to VCCA
Input/output 4. Referenced to VCCA
Input/output 5. Referenced to VCCA
Input/output 6. Referenced to VCCA
Input/output 7. Referenced to VCCA
Input/output 8. Referenced to VCCA
Input/output 1. Referenced to VCCB
Input/output 2. Referenced to VCCB
Input/output 3. Referenced to VCCB
Input/output 4. Referenced to VCCB
Input/output 5. Referenced to VCCB
Input/output 6. Referenced to VCCB
Input/output 7. Referenced to VCCB
Input/output 8. Referenced to VCCB
Ground
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
B1
20
18
17
16
15
14
13
12
11
10
2
B2
B3
B4
B5
B6
B7
B8
GND
OE
VCCA
VCCB
I
3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
I
A-port supply voltage. 1.5 V ≤ VCCA ≤ 3.6 V, VCCA ≤ VCCB
.
19
I
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V.
(1) I = Input, O = Output, I/O = Bi-directional, G = Ground
Copyright © 2015–2016, Texas Instruments Incorporated
3
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCCA
4.6
5.5
Supply voltage
VCCB
V
A port
B port
A port
B port
A port
B port
VI < 0
VO < 0
4.6
VI
Input voltage(2)
V
V
V
6.5
4.6
Voltage range applied to any output
VO
VO
in the high-impedance or power-off state(2)
6.5
VCCA + 0.5
VCCB + 0.5
–50
Voltage range applied to any output in the high or low state(2) (3)
IIK
IOK
IO
Input clamp current
mA
mA
mA
mA
°C
Output clamp current
–50
Continuous output current
Continuous current through VCCA, VCCB, or GND
Storage temperature
–50
–100
–65
50
100
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative Voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)
VCCA (V)
VCCB (V)
MIN
MAX
3.6
UNIT
VCCA
1.4
Supply voltage(3)
VCCB
V
1.65
5.5
1.4 to 1.95
A-Port I/Os
VCCI – 0.2
VCCI
1.95 to 3.6
VCCI – 0.4
VCCI
High-level input
voltage
VIH
V
V
B-Port I/Os
OE
VCCI – 0.4
VCCI
1.4 to 3.6
VCCA × 0.65
5.5
1.4 to 1.95
1.95 to 3.6
0
0
0
0
0.15
A-Port I/Os
1.65 to 5.5
0.15
Low-level input
voltage
VIL
B-Port I/Os
0.15
1.4 to 3.6
OE
VCCA × 0.35
A-Port I/Os Push-pull
B-Port I/Os Push-pull
Control input
Input transition rise or
fall rate
Δt/Δv
1.4 to 3.6
10
ns/V
°C
TA
Operating free-air temperature
–40
125
(1) VCCI is the VCC associated with the data input port.
(2) VCCO is the VCC associated with the output port.
(3) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
6.4 Thermal Information
TXS0108E-Q1
PW (TSSOP)
20 PINS
101.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
35.9
52.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.3
ψJB
51.9
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015–2016, Texas Instruments Incorporated
5
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
6.5 Electrical Characteristics(1)(2)(3)
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
TA = –40°C to 125°C
TEST
CONDITIONS
PARAMETER
VCCA (V)
VCCB (V)
UNIT
MIN
TYP
MAX
MIN
MAX
IOH = –20 μA,
VIB ≥ VCCB – 0.4 V
VOHA
1.4 to 3.6
1.65 to 5.5
VCCA × 0.67
V
IOL = 180 μA, VIB ≤ 0.15 V
IOL = 220 μA, VIB ≤ 0.15 V
IOL = 300 μA, VIB ≤ 0.15 V
IOL = 400 μA, VIB ≤ 0.15 V
1.4
1.65
2.3
3
0.4
0.4
VOLA
VOHB
VOLB
1.65 to 5.5
1.65 to 5.5
V
V
V
0.4
0.55
IOH = –20 μA,
VIA ≥ VCCA – 0.2 V
1.4 to 3.6
VCCB × 0.67
IOL = 220 μA, VIA ≤ 0.15 V
IOL = 300 μA, VIA ≤ 0.15 V
IOL = 400 μA, VIA ≤ 0.15 V
IOL = 620 μA, VIA ≤ 0.15 V
VI = VCCI or GND
1.65
0.4
0.4
2.3
1.4 to 3.6
3
0.55
0.55
2
4.5
II
OE
1.4
1.4
1.65 to 5.5
–1
–1
1
1
μA
μA
A or
B port
IOZ
1.65 to 5.5
–2
2
1.4 to 3.6
2.3 to 5.5
2
2
ICCA
VI = VO = Open, IO = 0
VI = VO = Open, IO = 0
3.6
0
5.5
μA
μA
0
1.4 to 3.6
3.6
–1
6
2.3 to 5.5
0
ICCB
–1
1.5
0
5.5
VI = VCCI or GND,
IO = 0
ICCA + ICCB
ICCZA
ICCZB
Ci
1.4 to 3.6
1.4 to 3.6
2.3 to 5.5
8
2
6
μA
μA
VI = VO = Open,
IO = 0, OE = GND
1.65 to 5.5
VI = VO = Open,
IO = 0, OE = GND
1.4 to 3.6
3.3
1.65 to 5.5
3.3
μA
OE
4.5
6
6.75
7.6
pF
A port
B port
Cio
3.3
3.3
pF
5.5
6.9
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
(3) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.
6.6 Timing Requirements: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
VCC B = 1.8 V VCC B = 2.5 V
± 0.15 V ± 0.2 V
VCC B= 3.3 V
± 0.3 V
VCC B= 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
60
MIN
MAX
60
Data rate
Push-pull
40
60
Mbps
ns
Open-drain
Push-pull
0.8
0.8
1
1
tw
25
16.7
16.7
16.7
Pulse duration
Data inputs
Open-drain
1250
1250
1000
1000
6
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
6.7 Timing Requirements: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCC B = 1.8 V
± 0.15 V
VCC B = 2.5 V
± 0.2 V
VCC B= 3.3 V
± 0.3 V
VCC B= 5 V
± 0.5 V
UNIT
MIN
MAX
MIN MAX
65
MIN MAX
70
MIN
MAX
Push-pull
45
70
1
Data rate
Mbps
ns
Open-drain
Push-pull
0.8
0.8
0.8
22.2
15.3
15.3
15.3
tw Pulse duration
Data inputs
Open-drain
1250
1250
1250
1000
6.8 Timing Requirements: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
80
MIN
MAX
MIN
MAX
100
1
Push-pull
95
Data rate
Mbps
ns
Open-drain
Push-pull
0.8
0.8
12.5
10.5
10
tw
Pulse duration
Data inputs
Open-drain
1250
1250
1000
6.9 Timing Requirements: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCCB = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
110
1.2
Push-pull
100
0.8
Data rate
Mbps
ns
Open-drain
Push-pull
10
9.1
tw
Pulse duration
Data inputs
Open-drain
1250
833
Copyright © 2015–2016, Texas Instruments Incorporated
7
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
6.10 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
TEST
CONDITIO
N
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
PARA
METER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
(DRIVING)
Push-pull
11
14.4
12
9.2
12.8
10
8.6
12.2
9.8
473
11
8.6
12
tPHL
tPLH
tPHL
tPLH
Open-drain
Push-pull
2.5
0.9
3.4
2
0.9
2.6
2
1
1.9
1.5
2
A
B
B
A
ns
9.7
384
12
Open-drain
Push-pull
720
12.7
13.2
9.5
554
11.1
9.6
6.2
603
480
400
9.8
716
7.4
756
7.7
8.2
5.5
8.6
1
Open-drain
Push-pull
2.3
8.5
5.1
519
480
400
9
7.5
4.2
407
480
400
8.9
481
5
ns
Open-drain
745
480
400
13.1
982
11.4
1020
9.9
ten
OE
OE
A or B
A or B
ns
ns
Push-pull
tdis
Push-pull
3
220
2.6
220
2.3
2.4
2
2.4
180
1.6
150
1.7
1.8
1.3
1.3
2
140
1
2
100
0.7
40
1.7
1.5
1
trA
trB
tfA
A-port rise time
B-port rise time
A-port fall time
B-port fall time
ns
ns
Open-drain
Push-pull
592
6
Open-drain
Push-pull
100
1.6
1.7
1
653
6.8
9
370
6
Open-drain
Push-pull
10
9.15
3.1
7.7
1
ns
ns
8.7
3.8
9.6
1
tfB
Open-drain
2
11.5
1
1
1
tSK(O)
Channel-to-channel skew Push-pull
8
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
6.11 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
TO
TEST
PARA-
METER
FROM
(INPUT)
(OUTPUT CONDITION
UNIT
)
(DRIVING)
MIN
MAX
8.2
MIN
1.7
0.2
2
MAX
6.4
9.9
5.6
584
8
MIN
1.6
0.3
1.9
MAX
5.7
9.3
6.5
466
7.4
7.3
5.8
459
100
410
7.8
508
5.3
546
6.8
6.8
3.9
9.6
MIN
1.5
0.3
1.8
MAX
5.6
8.9
6.3
346
7
Push-pull
tPHL
Open-drain
Push-pull
2.1
11.4
9
A
B
B
ns
tPLH
tPHL
tPLH
Open-drain
Push-pull
0.15
3.19
729
9.8
Open-drain
Push-pull
12.1
10.2
733
100
410
11.9
996
10.5
1001
8.8
8.5
7
6.2
5
A
ns
Open-drain
578
100
410
8.6
691
7.4
677
7.1
7.2
5.4
10.7
323
100
410
7.4
365
4.7
323
6.06
6.1
3
ten
OE
OE
A or B
A or B
ns
ns
Push-pull
tdis
Push-pull
2.7
250
2.5
250
2.1
2.2
2
2
200
1.7
170
1.6
1.7
1.3
1
1.9
150
1.1
120
1.4
1.4
0.9
1
1.8
110
60
trA
trB
tfA
A-port rise time
ns
ns
Open-drain
Push-pull
B-port rise time
A-port fall time
B-port fall time
Open-drain
Push-pull
32
1.4
1.2
0.7
0.6
Open-drain
Push-pull
9
ns
ns
8.3
tfB
Open-drain
2
10.5
7.8
Channel-to-channel
skew
tSK(O)
Push-pull
1
1
1
1
Copyright © 2015–2016, Texas Instruments Incorporated
9
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
6.12 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
TEST
CONDITION
(DRIVING)
PARA-
METER
FROM
(INPUT) (OUTPUT)
TO
UNIT
MAX
MIN
MAX
5
MIN
MAX
4
MIN
Push-pull
3.7
tPHL
Open-drain
Push-pull
6.2
5.2
5
6.3
4.3
17.5
4.7
6
5.8
ns
A
B
3.9
tPLH
tPHL
tPLH
Open-drain
Push-pull
15.5
4.2
5.4
7.3
5.9
5
Open-drain
Push-pull
4.9
ns
B
A
4.4
5
3.5
Open-drain
5
ten
OE
A or B
100
400
7.3
692
6.5
693
5.7
5.6
5.4
14.2
100
400
6.4
529
5.1
483
4.7
4.7
4.1
19.4
100
400
5.8
377
4.32
304
3.8
4.2
3
ns
ns
Push-pull
tdis
OE
A or B
Push-pull
1.89
110.00
1.70
1.6
157
1.3
140
1.2
1.2
0.9
0.5
1.5
116
0.9
77
trA
trB
tfA
A-port rise time
B-port rise time
A-port fall time
B-port fall time
ns
ns
Open-drain
Push-pull
Open-drain
Push-pull
107.00
1.50
1.3
1.1
0.7
0.4
Open-drain
Push-pull
1.50
ns
ns
1.40
tfB
Open-drain
0.40
3
Channel-to-channel
skew
tSK(O)
Push-pull
1
1
1
10
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
6.13 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
TEST
CONDITION
(DRIVING)
PARAME
TER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
MIN
MAX
3.8
5.3
3.9
5
MIN
MAX
3.28
4.8
3.5
12.5
3.8
4.5
4.3
5
Push-pull
tPHL
tPLH
tPHL
tPLH
Open-drain
Push-pull
A
B
B
A
ns
Open-drain
Push-pull
4.2
5.5
4.32
5
Open-drain
Push-pull
ns
Open-drain
ten
OE
OE
A or B
A or B
100
400
5.7
446
5
100
400
5
ns
ns
Push-pull
tdis
Push-pull
Open-drain
Push-pull
Open-drain
Push-pull
Open-drain
Push-pull
Open-drain
Push-pull
1.5
129
1.35
129
1.4
1.4
99.6
1
trA
trB
tfA
A-port rise time
B-port rise time
A-port fall time
B-port fall time
ns
ns
337
4.24
290
3.5
3.7
3.1
3.1
1
427
4.5
4.4
4.2
4.2
1
77
1.3
1.2
1.1
1.1
1.4
ns
ns
1.3
tfB
1.3
tSK(O)
Channel-to-channel skew
Copyright © 2015–2016, Texas Instruments Incorporated
11
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
6.14 Typical Characteristics
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = œ 40°C
TA = 25°C
TA = 125°C
TA = œ 40°C
TA = 25°C
TA = 125°C
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Low-Level Current (µA)
Low-Level Current (µA)
D001
D001
VCCA = 2.3 V
VCCB = 2.7 V
VIL(A) = 0.15 V
VCCA = 3 V
VCCB = 5.5 V
VIL(A) = 0.15 V
Figure 1. Low-Level Output Voltage (VOL(Bx)
vs Low-Level Current (IOL(Bx)
)
Figure 2. Low-Level Output Voltage (VOL(Bx)
vs Low-Level Current (IOL(Bx)
)
)
)
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = œ 40°C
TA = 25°C
TA = 125°C
TA = œ 40°C
TA = 25°C
TA = 125°C
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Low-Level Current (µA)
Low-Level Current (µA)
D001
D001
VCCA = 1.65 V
VCCB = 1.95 V
VIL(A) = 0.15 V
VCCA = 1.65 V
VCCB = 5.5 V
VIL(A) = 0.15 V
Figure 3. Low-Level Output Voltage (VOL(Bx)
vs Low-Level Current (IOL(Bx)
)
Figure 4. Low-Level Output Voltage (VOL(Bx)
vs Low-Level Current (IOL(Bx)
)
)
)
12
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
7 Parameter Measurement Information
7.1 Load Circuits
Figure 5 shows the push-pull driver circuit used for measuring data rate, pulse duration, propagation delay,
output rise-time and fall-time. Figure 6 shows the open-drain driver circuit used for measuring data rate, pulse
duration, propagation delay, output rise-time and fall-time.
VCCI
VCCI
VCCO
VCCO
DUT
DUT
IN
IN
OUT
OUT
1 Mꢀ
15 pF
15 pF
1 Mꢀ
Figure 5. Data Rate, Pulse Duration, Propagation
Delay, Output Rise-Time and Fall-Time
Measurement Using a Push-Pull Driver
Figure 6. Data Rate (10 pF), Pulse Duration (10 pF),
Propagation Delay, Output Rise-Time and Fall-
Time Measurement Using an Open-Drain Driver
2 × VCCO
Open
S1
50 kꢀ
From Output
Under Test
15 pF
50 kꢀ
TEST
S1
tPZL / tPLZ
2 × VCCO
Open
(tdis
)
tPHZ / tPZH
(ten)
Figure 7. Load Circuit for Enable-Time and Disable-Time Measurement
1. tPLZ and tPHZ are the same as tdis
.
2. tPZL and tPZH are the same as ten.
3. VCCI is the VCC associated with the input port.
4. VCCO is the VCC associated with the output port.
Copyright © 2015–2016, Texas Instruments Incorporated
13
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
7.2 Voltage Waveforms
V
CCI
t
W .
Input
V
CCI
/2
V
CCI
/2
0 V
V
CCI
Input
V
/V
V
/V
OHA OHB
OHA OHB
t
t
PLH
PHL
0 V
V
OH
0.9
0.1
V
CCO
Output
V /2
CCO
V
CCO
/2
V
CCO
V
OL
t
f
t
r
Figure 8. Pulse Duration (Push-Pull)
Figure 9. Propagation Delay Times
•
•
CL includes probe and jig capacitance.
Waveform 1 in Figure 10 is for an output with internal such that the output is high, except when OE is high (see
Figure 7). Waveform 2 in Figure 10 is for an output with conditions such that the output is low, except when OE is
high.
•
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, dv/dt
≥ 1 V/ns.
•
•
•
•
•
•
The outputs are measured one at a time, with one transition per measurement.
tPLZ and tPHZ are the same as tdis
.
tPZL and tPZH are the same as ten
.
tPLH and tPHL are the same as tpd
.
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
VCCA
VCCA / 2
VCCA / 2
OE input
0 V
tPLZ
tPZL
VOH
Output
Waveform 1
S1 at 2 × VCCO
VCCO / 2
V
× 0.2
CCO
VOL
(see Note 2)
tPHZ
tPZH
VCCO
Output
Waveform 2
S1 at GND
V
× 0.9
OH
VCCO / 2
(see Note 2)
0 V
Figure 10. Enable and Disable Times
14
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
8 Detailed Description
8.1 Overview
The TXS0108E-Q1 device is a directionless voltage-level translator specifically designed for translating logic
voltage levels. The A-port accepts I/O voltages ranging from 1.4 V to 3.6 V. The B-port accepts I/O voltages from
1.65 V to 5.5 V. The device uses pass gate architecture with edge rate accelerators (one shots) to improve the
overall data rate. The pull-up resistors, commonly used in open-drain applications, have been conveniently
integrated so that an external resistor is not needed. While this device is designed for open-drain applications,
the device can also translate push-pull CMOS logic outputs.
8.2 Functional Block Diagram
VCCA
VCCB
OE
A1
One-Shot
Accelerator
One-Shot
Accelerator
Gate Bias
RPUA
RPUB
B1
B2
One-Shot
Accelerator
One-Shot
Accelerator
Gate Bias
RPUA
RPUB
A2
A3
B3
A4
A5
A6
B4
B5
B6
One-Shot
Accelerator
One-Shot
Accelerator
Gate Bias
RPUA
RPUB
A7
B7
One-Shot
Accelerator
One-Shot
Accelerator
Gate Bias
RPUA
RPUB
A8
B8
Each A-port I/O has a pull-up resistor (RPUA) to VCCA and each B-port I/O has a pull-up resistor (RPUB) to VCCB
.
RPUA and RPUB have a value of 40 kΩ when the output is driving low. RPUA and RPUB have a value of 4 kΩ when
the output is driving high. RPUA and RPUB are disabled when OE = Low.
8.3 Feature Description
8.3.1 Architecture
Figure 11 describes semi-buffered architecture design this application requires for both push-pull and open-drain
mode. This application uses edge-rate accelerator circuitry (for both the high-to-low and low-to-high edges), a
high-on-resistance N-channel pass-gate transistor (on the order of 300 Ω to 500 Ω) and pull-up resistors (to
provide DC-bias and drive capabilities) to meet these requirements. This design needs no direction-control signal
(to control the direction of data flow from A to B or from B to A). The resulting implementation supports both low-
speed open-drain operation as well as high-speed push-pull operation.
Copyright © 2015–2016, Texas Instruments Incorporated
15
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Feature Description (continued)
VCC
A
VCCB
One-Shot
Accelerator
OS3
P2
N2
RPUB
RPUA
Translator
T1
One-Shot
Accelerator
OS4
A
Bias
B
R1
R2
Npass
P1
N1
One-Shot
Accelerator
OS1
Translator
T2
One-Shot
Accelerator
OS2
Figure 11. Architecture of a TXS0108E-Q1 Cell
When transmitting data from A-ports to B-ports, during a rising edge the one-shot circuit (OS3) turns on the
PMOS transistor (P2) for a short-duration which reduces the low-to-high transition time. Similarly, during a falling
edge, when transmitting data from A to B, the one-shot circuit (OS4) turns on the N-channel MOSFET transistor
(N2) for a short-duration which speeds up the high-to-low transition. The B-port edge-rate accelerator consists of
one-shot circuits OS3 and OS4. Transistors P2 and N2 and serves to rapidly force the B port high or low when a
corresponding transition is detected on the A port.
When transmitting data from B- to A-ports, during a rising edge the one-shot circuit (OS1) turns on the PMOS
transistor (P1) for a short-duration which reduces the low-to-high transition time. Similarly, during a falling edge,
when transmitting data from B to A, the one-shot circuit (OS2) turns on NMOS transistor (N1) for a short-duration
and this speeds up the high-to-low transition. The A-port edge-rate accelerator consists of one-shots OS1 and
OS2, transistors P1 and N1 components and form the edge-rate accelerator and serves to rapidly force the A
port high or low when a corresponding transition is detected on the B port.
8.3.2 Input Driver Requirements
The continuous DC-current sinking capability is determined by the external system-level open-drain (or push-pull)
drivers that are interfaced to the TXS0108E-Q1 I/O pins. Because the high bandwidth of these bidirectional I/O
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a
modest DC-current sourcing capability of hundreds of micro-amperes, as determined by the internal pull-up
resistors.
The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving
TXS0108E-Q1 data I/Os, as well as the capacitive loading on the data lines.
Similarly, the tPHL and maximum data rates also depend on the output impedance of the external driver. The
values for tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the
external driver is less than 50 Ω.
16
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
Feature Description (continued)
8.3.3 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper one-shot triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The one-shot circuits have been designed to
stay on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The one-shot duration has been set to best optimize trade-offs between dynamic
ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to
the capacitance of the TXS0108E-Q1 output. Therefore, TI recommends that this lumped-load capacitance is
considered in order to avoid one-shot retriggering, bus contention, output signal oscillations, or other adverse
system-level affects.
8.3.4 Enable and Disable
The TXS0108E-Q1 has an OE pin input that is used to disable the device by setting the OE pin low, which
places all I/Os in the Hi-Z state. The disable time (tdis) indicates the delay between the time when the OE pin
goes low and when the outputs actually get disabled (Hi-Z). The enable time (ten) indicates the amount of time
the design must allow for the one-shot circuitry to become operational after the OE pin goes high.
8.3.5 Pull-up or Pull-down Resistors on I/O Lines
The TXS0108E-Q1 has the smart pull-up resistors dynamically change value based on whether a low or a high is
being passed through the I/O line. Each A-port I/O has a pull-up resistor (RPUA) to VCCA and each B-port I/O has
a pull-up resistor (RPUB) to VCCB. RPUA and RPUB have a value of 40 kΩ when the output is driving low. RPUA and
RPUB have a value of 4 kΩ when the output is driving high. RPUA and RPUB are disabled when OE = Low. This
feature provides lower static power consumption (when the I/Os are passing a low), and supports lower VOL
values for the same size pass-gate transistor, and helps improve simultaneous switching performance.
8.4 Device Functional Modes
The TXS0108E-Q1 device has two functional modes, enabled and disabled. To disable the device set the OE pin
input low, which places all I/Os in a high impedance state. Setting the OE pin input high enables the device.
Copyright © 2015–2016, Texas Instruments Incorporated
17
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TXS0108E-Q1 can be used in level-translation applications for interfacing devices or systems operating at
different interface voltages with one another. The device is ideal for use in applications where an open-drain
driver is connected to the data I/Os. The device is appropriate for applications where a push-pull driver is
connected to the data I/Os, but the TXB0104 device, (SCES650) 4-Bit Bidirectional Voltage-Level Translator
might be a better option for such push-pull applications. The device is a semi-buffered auto-direction-sensing
voltage translator design is optimized for translation applications (for example, MMC Card Interfaces) that require
the system to start out in a low-speed open-drain mode and then switch to a higher speed push-pull mode.
9.2 Typical Application
1.8 V
3.3 V
0.1 mF
0.1 mF
VCCA
VCCB
OE
1.8-V
System
3.3-V
System
Controller
Controller
A1
A2
A3
A4
A5
A6
A7
A8
TXS0108E-Q1
B1
B2
B3
B4
B5
B6
B7
B8
Data
GND
Figure 12. Typical Application Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1. Ensure that VCCA ≤ VCCB
.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
1.4 V to 3.6 V
Output voltage range
1.65 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Input voltage range
–
Use the supply voltage of the device that is driving the TXS0108E-Q1 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
18
Copyright © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
•
Output voltage range
–
Use the supply voltage of the device that the TXS0108E-Q1 device is driving to determine the output
voltage range.
–
The TXS0108E-Q1 device has smart internal pull-up resistors. External pull-up resistors can be added to
reduce the total RC of a signal trace if necessary.
•
An external pull-down resistor decreases the output VOH and VOL. Use Equation 1 to calculate the VOH as a
result of an external pull-down resistor.
VOH = VCCx × RPD / (RPD + 4 kΩ)
(1)
9.2.3 Application Curves
VCCA = 1.8 V
VCCB = 3.3 V
Figure 13. Level-Translation of a 2.5-MHz Signal
Copyright © 2015–2016, Texas Instruments Incorporated
19
TXS0108E-Q1
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
www.ti.com.cn
10 Power Supply Recommendations
During operation, ensure that VCCA ≤ VCCB at all times. The sequencing of each power supply will not damage the
device during the power up operation, so either power supply can be ramped up first. The output-enable (OE)
input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the
high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the
OE input pin must be tied to GND through a pull-down resistor and must not be enabled until VCCA and VCCB are
fully ramped and stable. The minimum value of the pull-down resistor to ground is determined by the current-
sourcing capability of the driver.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
•
Bypass capacitors should be used on power supplies. Place the capacitors as close as possible to the VCCA,
VCCB pin and GND pin.
•
•
Short trace lengths should be used to avoid excessive loading.
PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the
source driver.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane (Inner Layer)
TXS0108E-Q1PWR
To Controller
1
2
3
4
20
19
18
17
A1
B1
To system
Bypass capacitor
0.1 µF
0.1 µF
0.1 µF
Bypass capacitor
0.1 µF
VCCA
VCCB
To system
To system
To Controller
A2
A3
B2
B3
To Controller
5
6
16
15
14
13
12
11
A4
A5
B4
B5
To system
To system
To system
To Controller
To Controller
To Controller
7
A6
A7
A8
OE
B6
B7
8
9
B8
To system
To system
10
GND
To Controller
To Controller
Keep OE low until VCCA and VCCB are powered up
Figure 14. Layout Example
20
版权 © 2015–2016, Texas Instruments Incorporated
TXS0108E-Q1
www.ti.com.cn
ZHCSDZ8A –JUNE 2015–REVISED FEBRUARY 2016
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2016, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TXS0108EQPWRQ1
ACTIVE
TSSOP
PW
20
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
YF08EQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TXS0108EQPWRQ1
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 20
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TXS0108EQPWRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TXS0108ERGYR
8-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS
TI
TXS0108EZXYR
8-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS
TI
TXS0108E_10
8-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS
TI
TXS0108E_101
8-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS
TI
TXS0206
MMC, SD CARD, Memory Stick™ VOLTAGE-TRANSLATION TRANSCEIVER WITH ESD PROTECTION AND EMI FILTERING
TI
TXS0206-29
MMC, SD CARD, Memory Stick™ VOLTAGE-TRANSLATION TRANSCEIVER AND LDO VOLTAGE REGULATOR WITH ESD PROTECTION AND EMI FILTERING
TI
TXS0206-29YFPR
MMC, SD CARD, Memory Stick™ VOLTAGE-TRANSLATION TRANSCEIVER AND LDO VOLTAGE REGULATOR WITH ESD PROTECTION AND EMI FILTERING
TI
TXS0206-29_0912
MMC, SD CARD, Memory Stick™ VOLTAGE-TRANSLATION TRANSCEIVER AND LDO VOLTAGE REGULATOR WITH ESD PROTECTION AND EMI FILTERING
TI
©2020 ICPDF网 联系我们和版权申明