UC1527B [TI]
Regulating Pulse Width Modulators; 调节脉冲宽度调制器
| 型号： | UC1527B |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Regulating Pulse Width Modulators |
| 文件： | 总14页 (文件大小：651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
available
Regulating Pulse Width Modulators
FEATURES
DESCRIPTION
• 8 to 35V Operation
The UC1525B/1527B series of pulse width modulator integrated circuits
are designed to offer improved performance and lowered external parts
count when used in designing all types of switching power supplies. The
on-chip +5.1V buried zener reference is trimmed to ±0.75% and the input
common-mode range of the error amplifier includes the reference voltage,
eliminating external resistors. A sync input to the oscillator allows multiple
units to be slaved or a single unit to be synchronized to an external system
clock. A single resistor between the CT and the discharge terminals provide
a wide range of dead time adjustment. These devices also feature built-in
soft-start circuitry with only an external timing capacitor required. A shut-
down terminal controls both the soft-start circuitry and the output stages,
providing instantaneous turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shutdown commands. These
functions are also controlled by an undervoltage lockout which keeps the
outputs off and the soft-start capacitor discharged for sub-normal input volt-
ages. This lockout circuitry includes approximately 500mV of hysteresis for
jitter-free operation. Another feature of these PWM circuits is a latch follow-
ing the comparator. Once a PWM pulse has been terminated for any rea-
son, the outputs will remain off for the duration of the period. The latch is
reset with each clock pulse. The output stages are totem-pole designs ca-
pable of sourcing or sinking in excess of 200mA. The UC1525B output
stage features NOR logic, giving a LOW output for an OFF state. The
UC1527B utilizes OR logic which results in a HIGH output level when OFF.
• 5.1V Buried Zener Reference
Trimmed to ±0.75%
• 100Hz to 500kHz Oscillator Range
• Separate Oscillator Sync Terminal
• Adjustable Deadtime Control
• Internal Soft-Start
• Pulse-by-Pulse Shutdown
• Input Undervoltage Lockout with
Hysteresis
• Latching PWM to Prevent Multiple
Pulses
• Dual Source/Sink Output Drivers
• Low Cross Conduction Output Stage
• Tighter Reference Specifications
BLOCK DIAGRAM
UDG-95055
SLUS376 JULY 1995
UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(Note 1)
Supply Voltage, (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V
Collector Supply Voltage (VC). . . . . . . . . . . . . . . . . . . . . . +40V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +5.5V
Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VIN
Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA
Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Power Dissipation at TA = +25°C. . . . . . . . . . . . . . . . . 1000mW
Power Dissipation at TC = +25°C . . . . . . . . . . . . . . . . 2000mW
Operating Junction Temperature . . . . . . . . . . –55°C to +150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V
Collector Supply Voltage (VC) . . . . . . . . . . . . . . +4.5V to +35V
Sink/Source Load Current (steady state) . . . . . . . . 0 to 100mA
Sink/Source Load Current (peak) . . . . . . . . . . . . . . 0 to 400mA
Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillator Frequency Range. . . . . . . . . . . . . . 100Hz to 400kHz
Oscillator Timing Resistor . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ
Oscillator Timing Capacitor . . . . . . . . . . . . . . 0.001µF to 0.1µF
Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . 0Ω to 500Ω
Note 1: Range over which the device is functional and parame-
ter limits are guaranteed.
All currents are positive into, negative out of the specified ter-
minal. Consult Packaging Section of Databook for thermal limi-
tations and considerations of packages.
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
J or N, DW Packages
LCC-20, PLCC-20 (Top View)
L, Q Packages
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the
UC1525B and UC1527B; –40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; +VIN =
20V, TA = TJ.
UC1525B/UC2525B
UC1527B/UC2527B
UC3525B
UC3527B
PARAMETER
Reference Section
TEST CONDITIONS
TJ = 25°C
MIN
TYP
MAX
MIN
TYP
MAX UNITS
Output Voltage
5.062 5.10 5.138 5.036 5.10 5.164
V
Line Regulation
VIN = 8V to 35V
5
7
10
5
7
10
15
mV
mV
mV
V
Load Regulation
IL = 0mA to 20mA
15
Temperature Stability (Note 2)
Total Output Variation
Short Circuit Current
Output Noise Voltage (Note 2)
Long Term Stability (Note 2)
Over Operating Range
Line, Load, and Temperature 5.036
VREF = 0, TJ =25°C
10
50
10
50
5.164 5.024
5.176
100
80
40
3
100
200
10
80
40
3
mA
10Hz ≤ f ≤10kHz, TJ = 25°C
TJ = 125°C, 1000 Hrs.
200 µVrms
10 mV
2
UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the
UC1525B and UC1527B; –40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; +VIN =
20V, TA = TJ.
UC1525B/UC2525B
UC1527B/UC2527B
UC3525B
UC3527B
PARAMETER
Oscillator Section (Note 3)
Initial Accuracy (Notes 2 & 3)
Voltage Stability (Notes 2 & 3)
Temperature Stability (Note 2)
Minimum Frequency
TEST CONDITIONS
TJ = 25°C
MIN
TYP
MAX
MIN
TYP
MAX UNITS
±2
±0.3
±3
±6
±1
±2
±1
±3
±6
±2
%
%
VIN = 8V to 35V
Over Operating Range
RT = 200kW, CT = 0.1mF
RT = 2kW, CT = 470pF
IRT = 2mA
±6
±6
%
120
120
Hz
kHz
mA
V
Maximum Frequency
400
1.7
3.0
0.3
1.2
400
1.7
3.0
0.3
1.2
Current Mirror
2.0
3.5
0.5
2.0
1.0
2.2
2.0
3.5
0.5
2.0
1.0
2.2
Clock Amplitude (Notes 2 & 3)
Clock Width (Notes 2 & 3)
Sync Threshold
TJ = 25°C
1.0
2.8
2.5
1.0
2.8
2.5
ms
V
Sync Input Current
Sync Voltage = 3.5V
mA
Error Amplifier Section (VCM = 5.1V)
Input Offset Voltage
0.5
1
5
10
1
2
1
10
10
1
mV
mA
mA
dB
MHz
V
Input Bias Current
Input Offset Current
DC Open Loop Gain
RL ³ 10 MegW
60
1
75
2
60
1
75
2
Gain-Bandwidth Product (Note 2)
Output Low Level
AV = 0dB, TJ = 25°C
0.2
5.6
75
60
0.5
0.2
5.6
75
60
0.5
Output High Level
3.8
60
50
3.8
60
50
V
Common Mode Rejection
Supply Voltage Rejection
PWM Comparator
VCM = 1.5V to 5.2V
VIN = 8V to 35V
dB
dB
Minimum Duty Cycle
0
0
%
%
V
Maximum Duty Cycle (Note 3)
Input Threshold (Note 3)
Input Threshold (Note 3)
Input Bias Current (Note 2)
Shutdown Section
45
49
0.9
45
49
0.9
Zero Duty Cycle
0.7
0.7
Maximum Duty Cycle
3.3
3.6
1.0
3.3
3.6
1.0
V
0.05
0.05
mA
Soft Start Current
VSHUTDOWN = 0V, VSOFTSTART 25
= 0V
50
80
25
50
80
mA
Soft Start Low Level
Shutdown Threshold
VSHUTDOWN = 2.5V
0.4
0.8
0.7
1.0
0.4
0.8
0.7
1.0
V
V
To outputs, VSOFTSTART
5.1V, TJ =25°C
=
0.6
0.6
Shutdown Input Current
Shutdown Delay (Note 2)
VSHUTDOWN = 2.5V
0.4
0.2
1.0
0.5
0.4
0.2
1.0
0.5
mA
V
SHUTDOWN = 2.5V, TJ = 25°C
ms
Output Drivers (Each Output) (Vc = 20V)
Output Low Level
ISINK = 20mA
SINK = 100mA
ISOURCE = 20mA
SOURCE = 100mA
COMP and VSOFTSTART
0.2
1.0
19
18
7
0.4
2.0
0.2
1.0
19
18
7
0.4
2.0
V
V
V
V
V
I
Output HIgh Level
18
17
6
18
17
6
I
Undervoltage Lockout
Collector Leakage
V
=
8
8
High
VC = 35V
200
200
mA
3
UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the
UC1525B and UC1527B; –40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; +VIN =
20V, TA = TJ.
UC1525B/UC2525B
UC1527B/UC2527B
UC3525B
UC3527B
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX UNITS
Output Drivers (Each Output) (VC = 20V) (cont.)
Rise Time (Note 2)
Fall Time (Note 2)
CL = 1nF, TJ = 25°C
100
50
600
300
100
50
600
300
ns
ns
nc
CL = 1nF, TJ = 25°C
Per cycle, TJ = 25°C
Cross conduction charge
Total Standby Current
Supply Current
30
30
VIN = 35V
14
20
14
20
mA
Note 2: Ensured by design. Not 100% tested in production.
Note 3: Tested at fosc= 40kHz (RT = 3.6KW, CT = 0.01mF, RD = 0W). Approximate oscillator frequency is defined by:
1
f =
CT • 0.7 •R + 3RD
(
)
T
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
UC1525B Output Circuit (1/2 Circuit Shown)
UC1525B Output Saturation Characteristics
UDG-95056
UDG-95057
UDG-95059
In conventional push-pull bipolar designs, forward base
drive is controlled by R1-R3. Rapid turn-off times for the
power devices are achieved with speed-up capacitors C,
and C2.
UDG-95058
For single-ended supplies, the driver outputs are
grounded. The VC terminal is switched to ground by the to-
tem-pole source transistors on alternate oscillator cycles.
4
UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
UDG-95060
UDG-95061
The low source impedance of the output drivers provides
rapid charging of power FET input capacitance while mini-
mizing external components.
Low power transformers can be driven directly by the
UC1525B. Automatic reset occurs during dead time, when
both ends of the primary winding are switched to ground.
PRINCIPLES OF OPERATION AND TYPICAL
CHARACTERISTICS
Shutdown Options (See Block Diagram)
plying a positive signal on Pin 10 performs two functions:
the PWM latch is immediately set providing the fastest
turn-off signal to the external soft-start capacitor. If the
shutdown command is short, the PWM signal is termi-
nated without significant discharge of the soft-start ca-
Since both the compensation and soft-start terminals
(Pins 9 and 8) have current source pull-ups, either can
readily accept a pull-down signal which only has to sink a
maximum of 100µA to turn off the outputs. This is subject
to the added requirement of discharging whatever exter-
nal capacitance may be attached to these pins.
pacitor, thus, allowing, for example,
a convenient
implementation of pulse-by-pulse current limiting.
Holding Pin 10 high for a longer duration, however, will
ultimately discharge this external capacitor, recycling
slow turn-on upon release.
An alternate approach is the use of the shutdown cir-
cuitry of Pin 10 which has been improved to enhance the
available shutdown options. Activating this circuit by ap-
UC1525B Oscillator Schematic
UDG-95062
5
UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
Oscillator Charge Time vs. TRand C
Oscillator Discharge Time vs.DRand C
T
T
UDG-95064
UDG-95063
UC1525B Error Amplifier
Error Amplifier Open-Loop Frequency Response
UDG-95065
UDG-95066
6
UC1525B UC1527B
UC2525B UC2527B
UC3525B UC3527B
LAB TEST FIXTURE
UDG-95067
7
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
LCCC
CDIP
CDIP
CDIP
CDIP
LCCC
SOIC
Drawing
5962-8951105EA
5962-8951105V2A
5962-8951105VEA
UC1525BJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
FK
J
16
20
16
16
16
16
20
16
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
Call TI
J
A42 SNPB
A42 SNPB
Call TI
UC1525BJ883B
UC1525BJQMLV
UC1525BLQMLV
UC2525BDWTR
J
J
FK
DW
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2525BDWTRG4
UC3525BDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
PDIP
DW
DW
DW
DW
N
16
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3525BDWTR
UC3525BDWTRG4
UC3525BN
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC3525BNG4
UC3527BN
N
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
N
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC3527BNG4
N
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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