UC1725_12 [TI]
Isolated High Side FET Driver;
| 型号： | UC1725_12 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Isolated High Side FET Driver |
| 文件： | 总5页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1725
UC2725
UC3725
Isolated High Side FET Driver
FEATURES
DESCRIPTION
•
Receives Both Power and Signal Across The UC1725 and its companion chip, the UC1724, provide all the nec-
the Isolation Boundary
essary features to drive an isolated MOSFET transistor from a TTL in-
put signal. A unique modulation scheme is used to transmit both power
and signals across an isolation boundary with a minimum of external
components.
•
•
•
9 to 15 Volt High Level Gate Drive
Under-voltage Lockout
Protection circuitry, including under-voltage lockout, over-current shut-
down, and gate voltage clamping provide fault protection for the MOS-
FET. High level gate drive is guaranteed to be greater than 9 volts and
less than 15 volts under all conditions.
Programmable Over-current Shutdown
and Restart
•
Output Enable Function
Uses include isolated off-line full bridge and half bridge drives for driv-
ing motors, switches, and any other load requiring full electrical isola-
tion.
The UC1725 is characterized for operation over the full military tem-
perature range of -55°C to +125°C while the UC2725 and UC3725 are
characterized for -25°C to +85°C and 0°C to +70°C respectively.
BLOCK DIAGRAM
UDG-92051-1
1/94
UC1725
UC2725
UC3725
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (pin 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Power inputs (pins 7 & 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Output current, source or sink (pin 2)
DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5 us) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A
Enable and Current limit inputs (pins 4 & 6). . . . . . . . -0.3 to 6V
Power Dissipation at TA ≤ 25°C (DIL-8) . . . . . . . . . . . . . . . . 1W
Power Dissipation at TA ≤ 25°C (SO-14) . . . . . . . . . . . . 725mW
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C
PACKAGE PIN FUNCTION
PLCC-20 (Top View)
Q Package
FUNCTION
PIN
N/C
1
ISENSE
N/C
Timing
Enable
N/C
Input A
N/C
Input B
Gnd
2
3-5
6
7
8-9
11
12-14
15
16
Note 1: Unless otherwise indicated, voltages are referenced to
ground and currents are positive into, negative out of, the speci-
fied terminals (pin numbers refer to DIL-8 package).
Note 2: See Unitrode Integrated Circuits databook for
information regarding thermal specifications and limitations of
packages.
VCC
17
N/C
Output
18-19
20
DIL-8 (Top View)
J Or N Package
SOIC-16 (Top View)
DW Package
DIL-16 (Top View)
JE Or NE Package
(Unless otherwise stated, these specifications apply for -55°C≤TA≤+125°C for
UC1725; -25°C≤TA≤+85°C for UC2725; 0°C≤TA≤+70°C for UC3725; VCC (pin 3) =
0 to 15V, RT=10k, CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
ELECTRICAL CHARACTERISTICS:
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
POWER INPUT SECTION (PINS 7 & 8)
Forward Diode Drop, Schottky Rectifier
IF = 50ma
.55
1.1
.7
V
V
IF = 500ma
1.5
CURRENT LIMIT SECTION (PIN 4)
Input bias current
VPIN4 = OV
-1
-10
0.6
µA
V
Threshold voltage
0.4
0.5
100
Delay to outputs
VPIN4 = 0 to 1V
250
ns
TIMING SECTION (PIN 5)
Output Off Time
27
6.3
1.9
30
7.0
2.0
33
7.7
2.3
µs
V
Upper Mono Threshold
Lower Mono Threshold
HYSTERESIS AMPLIFIER (PINS 7 & 8)
Input Open Circuit Voltage
Input Impedance
V
Inputs (pins 7 & 8), Open Circuited, TA= 25°C
TA = 25°C
7.0
23
Vcc/2
28
8.0
33
V
kΩ
V
Hysteresis
26.5 2 Vcc 30.5
*
Delay to Outputs
VPIN7 - VPIN8 = VCC + 1V
100
300
ns
2
UC1725
UC2725
UC3725
(Unless otherwise stated, these specifications apply for -55°C≤TA≤+125°C for UC1725;
-25°C≤TA≤+85°C for UC2725; 0°C≤TA≤+70°C for UC3725; VCC (pin 3) = 0 to 15V, Rt=10k,
CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
ELECTRICAL
CHARACTERISTICS (cont.)
PARAMETER
ENABLE SECTION (PIN 6)
High Level Input Voltage
Low Level Input Voltage
Input Bias Current
TEST CONDITIONS
MIN
TYP MAX UNITS
2.1
1.4
1.4
V
V
.8
-250
-500
µA
OUTPUT SECTION
Output Low Level
IOUT = 20mA
IOUT = 200mA
IOUT = -20mA
0.35
0.6
0.5
2.5
V
V
Output High Level
13
12
13.5
13.4
14
V
IOUT = -200mA
VCC = 30V, Iout = -20mA
CT = 1nf
V
15
60
V
Rise/Fall Time
30
ns
UNDER VOLTAGE LOCKOUT
UVLO Low Saturation
Start-up Threshold
20mA, VCC = 8V
0.8
12
1.5
V
V
V
11.2
.75
12.6
1.12
Threshold Hysteresis
TOTAL STANDBY CURRENT
Supply Current
1.0
12
16
ma
APPLICATION AND OPERATION INFORMATION
INPUTS: Figure 1 shows the rectification and detection
scheme used in the UC1725 to derive both power and
signal information from the input waveform. Vcc is gener-
ated by peak detecting the input signal via the internal
bridge rectifier and storing on a small external capacitor,
C1. Note that this capacitor is also used to bypass high
pulse currents in the output stage, and therefore should
be placed direclty between pins 1 and 3 using minimal
lead lengths.
add a damping resistor across the transformer secondary
to minimize ringing and eliminate false triggering of the
hysteresis amplifier as shown in Figure 3.
UDG-92048
FIGURE 2 - Input Waveform (DIL-8 Pin 7 - Pin 8)
UDG-92047
FIGURE 1 - Input Stage
Signal detection is performed by the internal hysteresis
comparator which senses the polarity of the input signal
as shown in Figure 2. This is accomplished by setting
(resetting) the comparator only if the input signal ex-
ceeds Vcc (-Vcc). In some cases it may be necessary to
UDG-92049
FIGURE 3 - Signal Detection
3
UC1725
UC2725
UC3725
capacitor and resistor as shown in Figure 4. This, in turn,
controls the output off time according to the formula:
TOFF= 1.28 • RC.
If current limit feature is not required, simply ground pin 4
and leave pin 5 open.
OUTPUT: Gate drive to the power FET is provided by a
totem pole output stage capable of sourcing and sinking
currents in excess of 1 amp. The undervoltage lockout
circuit guarantees that the high level output will never be
less than 9 volts. In addition, during undervoltage lock-
out, the output stage will actively sink current to eliminate
the need for an external gate to source resistor. High
level output is also clamped to 15 volts. Under high ca-
pacitive loading however, the output may overshoot 2 to
3 volts, due to the drivers’ inabitlity to switch from full to
zero output current instantaneously. In a practical circuit
this is not normally a concern. A few ohms of series gate
resistance is normally required to prevent parasitic oscil-
lations, and will also eliminate overshoot at the gate.
UDG-92050
FIGURE 4 - Current Limit
CURRENT LIMIT AND TIMING: Current sensing and
shutdown can be implemented directly at the output us-
ing the scheme shown in Figure 4. Alternatively, a current
transformer can be used in place of RSENSE. A small RC
filter in series with the input (pin 4) is generally needed to
eliminate the leading edge current spike caused by
parasitic circuit capacitances being charged during turn
on. Due to the speed of the current sense circuit, it is
very important to ground CF directly to Gnd as shown to
eliminate false triggering of the one shot caused by
ground drops.
ENABLE: An enable pin is provided as a fast, digital in-
put that can be used in a number of applications to di-
rectly switch the output. Figure 6 shows a simple means
of providing a fast, high voltage translation by using a
small signal, high voltage transistor in a cascode configu-
ration. Note that the UC1725 is still used to provide
power, drive and protection circuitry for the power FET.
One shot timing is easily programmed using an external
UDG-92052
UDG-92053
FIGURE 6 - Using Enable Pin as a High Speed Input
Path
FIGURE 5 - Output Circuit
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
4
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明