UC1823A-SP_技术文档

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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

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FEATURES

DESCRIPTION

D

Improved Versions of the UC3823/UC3825

PWMs

The UC3823A and UC3823B and the UC3825A and

UC3825B family of PWM controllers are improved

versions of the standard UC3823 and UC3825 family.

Performance enhancements have been made to several

of the circuit blocks. Error amplifier gain bandwidth product

is 12 MHz, while input offset voltage is 2 mV. Current limit

threshold is assured to a tolerance of 5%. Oscillator

discharge current is specified at 10 mA for accurate dead

time control. Frequency accuracy is improved to 6%.

Startup supply current, typically 100 µA, is ideal for off-line

applications. The output drivers are redesigned to actively

sink current during UVLO at no expense to the startup

current specification. In addition each output is capable of

2-A peak currents during transitions.

Compatible with Voltage-Mode or

Current-Mode Control Methods

Practical Operation at Switching Frequencies

to 1 MHz

D

50-ns Propagation Delay to Output

D

High-Current Dual Totem Pole Outputs

(2-A Peak)

D

Trimmed Oscillator Discharge Current

Low 100-µA Startup Current

Pulse-by-Pulse Current Limiting Comparator

Latched Overcurrent Comparator With Full

Cycle Restart

BLOCK DIAGRAM

CLK/LEB 4

(60%)

13 VC

RT

CT

5

6

7

3

2

1

11 OUTA

*

OSC

R

S

T

RAMP

EAOUT

NI

D

1.25 V

E/A

14 OUTB

12 PGND

PWM

LATCH

PWM COMPARATOR

9 mA

INV

SOFT−START COMPLETE

RESTART

CURRENT

LIMIT

5 V

250mA

DELAY

LATCH

SS

8

1.0 V

1.2 V

0.2 V

OVER CURRENT

ILIM 9

S

R

S

D

RESTART

DELAY

R

FAULT LATCH

UVLO

VCC 15

GND 10

”B” 16V/10V

”A” 9.2V/8.4V

INTERNAL

BIAS

VREF

5.1 V

ON/OFF

4 V

V

GOOD

REF

16 5.1 VREF

UDG−02091

* On the UC1823A version, toggles Q and Q are always low.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2004, Texas Instruments Incorporated

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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a

high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full

discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state.

In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency

does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the

functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.

The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A

and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A

and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current

limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions

have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications.

Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for

detailed technical and applications information.

ORDERING INFORMATION

UVLO

9.2 V / 8.4 V

16 V / 10 V

MAXIMUM

DUTY CYCLE

T

A

(1)

SOIC−16

(1)

PLCC−20

(1)

PLCC−20

PDIP−16

(N)

SOIC−16

(DW)

PDIP−16

(N)

(DW)

(Q)

< 100%

< 50%

< 100%

< 50%

UC2823ADW

UC2825ADW

UC3823ADW

UC3825ADW

UC2823AN

UC2825AN

UC3823AN

UC3825AN

UC2823AQ

UC2825AQ

UC3823AQ

UC3825AQ

UC2823BDW

UC2825BDW

UC3823BDW

UC3825BDW

UC2823BN

UC2825BN

UC3823BN

UC3825BN

−

−40°C to 85°C

−0°C to 70°C

−

UC3825BQ

(1)

The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000

devices per reel for the Q package and 2000 devices per reel for the DW package.

UVLO

9.2 V / 8.4 V

MAXIMUM

DUTY CYCLE

T

A

CDIP−16

(J)

LCCC−20

(L)

< 100%

< 50%

UC1823AJ, UC1823AJ883B, UC1823AJQMLV

UC1825AJ, UC1825AJ883B, UC1825AJQMLV

UC1823AL, UC1823AL883B

−55°C to 125°C

UC1825AL, UC1825AL883B, UC1825ALQMLV

PIN ASSIGNMENTS

Q OR L PACKAGES

(TOP VIEW)

DW, J, OR N PACKAGES

(TOP VIEW)

INV

NI

EAOUT

CLK/LEB

RT

VREF

VCC

OUTB

VC

1

2

3

4

5

6

7

8

16

15

14

13

12

3

2

1

20 19

18

OUTB

VC

EAOUT

CLK/LEB

NC

4

5

6

7

8

17

16

15

PGND

NC

PGND

CT

11 OUTA

RT

10

9

RAMP

SS

GND

ILIM

14 OUTA

9 10 11 12 13

CT

NC = no connection

2

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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

TERMINAL FUNCTIONS

TERMINAL

NO.

I/O

DESCRIPTION

NAME

J or DW

Q or L

CLK/LEB

CT

4

5

O

I

Output of the internal oscillator

Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should

be connected to the device ground using minimal trace length.

6

8

EAOUT

GND

ILIM

3

10

9

4

O

−

I

Output of the error amplifier for compensation

Analog ground return pin

13

12

2

Input to the current limit comparator

INV

1

I

Inverting input to the error amplifier

NI

2

3

I

Non-inverting input to the error amplifier

High current totem pole output A of the on-chip drive stage.

High current totem pole output B of the on-chip drive stage.

Ground return pin for the output driver stage

OUTA

OUTB

PGND

11

14

12

14

18

15

O

−

Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode

operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak

current mode operation, this serves as the slope compensation input.

RAMP

7

9

I

RT

SS

5

8

7

I

Timing resistor connection pin for oscillator frequency programming

Soft-start input pin which also doubles as the maximum duty cycle clamp.

10

Power supply pin for the output stage. This pin should be bypassed with a 0.1-µF monolithic ceramic

low ESL capacitor with minimal trace lengths.

VC

13

15

16

17

19

20

−

Power supply pin for the device. This pin should be bypassed with a 0.1-µF monolithic ceramic low

ESL capacitor with minimal trace lengths

VCC

VREF

5.1-V reference. For stability, the reference should be bypassed with a 0.1-µF monolithic ceramic

low ESL capacitor and minimal trace length to the ground plane.

O

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNIT

22 V

V

IN

Supply voltage,

VC, VCC

I

Source or sink current, DC

Source or sink current, pulse (0.5 µs)

OUTA, OUTB

INV, NI, RAMP

ILIM, SS

PGND

0.5 A

O

2.2 A

O

−0.3 V to 7 V

−0.3 V to 6 V

0.2 V

Analog inputs

Power ground

I

Clock output current

Error amplifier output current

Soft-start sink current

Oscillator charging current

CLK/LEB

EAOUT

−5 mA

CLK

O(EA)

SS

5 mA

SS

20 mA

RT

−5 mA

OSC

T

Operating virtual junction temperature range

Storage temperature

−55°C to 150°C

−65°C to 150°C

−55C°C to 150°C

−65°C to 150°C

300°C

J

T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

Storage temperature

t

STG

Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

3

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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS

T

R

= −55°C to 125°C for the UC1823A/UC1825A, T = −40°C to 85°C for the UC2823x/UC2825x, T = 0°C to 70°C for the UC3823x/UC3825x,

A A

A

T

= 3.65 kΩ, C = 1 nF, V = 12 V, T = T (unless otherwise noted)

T

CC A J

PARAMETER

REF

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE, V

V

Ouput voltage range

Line regulation

T = 25°C,

I = 1 mA

O

5.05

5.1

2

5.15

15

V

O

J

12 V ≤ VCC ≤ 20 V

mV

V

Load regulation

1 mA ≤ I ≤ 10 mA

5

20

O

Total output variation

Temperature stability

Output noise voltage

Line, load, temperature

5.03

30

5.17

(1)

T

(min)

< T < T

(max)

0.2

50

5

0.4 mV/°C

µV

A

10 Hz < f < 10 kHz

RMS

(1)

Long term stability

T = 125°C, 1000 hours

J

25

90

mV

mA

Short circuit current

OSCILLATOR

VREF = 0 V

60

T = 25°C

375

0.9

400

1

425

1.1

kHz

MHz

kHz

J

(1)

Initial accuracy

f

OSC

R

T

= 6.6 kΩ, C = 220 pF, T = 25°C

T A

Line, temperature

= 6.6 kΩ, C = 220 pF,

350

0.85

450

1.15

1%

(1)

Total variation

R

T

MHz

T

Voltage stability

12 V < VCC < 20 V

< T < T

(max)

(1)

Temperature stability

T

(min)

+/−

3.7

5%

4

A

High-level output voltage, clock

Low-level output voltage, clock

Ramp peak

0

0.2

3

2.6

0.7

1.6

9

2.8

1

V

Ramp valley

1.25

2

Ramp valley-to-peak

Oscillator discharge current

1.8

10

I

OSC

R

T

= OPEN,

V

CT

= 2 V

11

mA

ERROR AMPLIFIER

Input offset voltage

2

0.6

0.1

95

10

3

mV

Input bias current

Input offset current

µA

1

Open loop gain

1 V < V < 4 V

60

75

85

1

O

CMRR Common mode rejection ratio

1.5 V < V

< 5.5 V

< 20 V

95

dB

CM

PSRR

Power supply rejection ratio

Output sink current

12 V < V

CC

110

2.5

−1.3

4.7

0.5

12

I

V

= 1 V

O(sink)

EAOUT

mA

V

Output source current

High-level output voltage

Low-level output voltage

Gain bandwidth product

V

= 4 V

−0.5

4.5

0

O(src)

I

= −0.5 mA

= −1 mA

5

1

f = 200 kHz

6

Mhz

(1)

Slew rate

6

9

V/µs

(1)

Ensured by design. Not production tested.

4

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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS

T

R

= −55°C to 125°C for the UC1823A/UC1825A, T = −40°C to 85°C for the UC2823x/UC2825x, T = 0°C to 70°C for the UC3823x/UC3825x,

A A

A

T

= 3.65 kΩ, C = 1 nF, V = 12 V, T = T (unless otherwise noted)

T

CC A J

PWM COMPARATOR

I

Bias current, RAMP

V

= 0 V

−1

−8

µA

BIAS

RAMP

Minimum duty cycle

0%

Maximum duty cycle

Leading edge blanking time

85%

300

8.5

t

R

= 2 kΩ,

C

= 470 pF

375

10.0

1.25

50

450

11.5

1.4

ns

kΩ

V

LEB

R

Leading edge blanking resistance

V

= 3 V

LEB

CLK/LEB

V

Zero dc threshold voltage, EAOUT

Delay-to-output time

= 0 V

1.10

ZDC

RAMP

t

= 2.1 V,

V = 0 V to 2 V step

ILIM

80

ns

DELAY

EAOUT

CURRENT LIMIT / START SEQUENCE / FAULT

I

Soft-start charge current

Full soft-start threshold voltage

Restart discharge current

Restart threshold voltage

ILIM bias current

V

= 2.5 V

8

4.3

14

5

20

µA

V

SS

V

SS

DSCH

SS

I

= 2.5 V

SS

100

250

0.3

350

0.5

µA

V

= 0 V to 2 V step

15

µA

BIAS

CL

ILIM

Current limit threshold voltage

Overcurrent threshold voltage

0.95

1.14

1

1.2

50

1.05

1.26

80

V

(1)

Delay-to-output time, ILIM

t

d

V

ILIM

ns

OUTPUT

I

= 20 mA

= 200 mA

= 20 mA

= 200 mA

0.25

1.2

1.9

2

0.4

2.2

2.9

3

OUT

Low-level output saturation voltage

High-level output saturation voltage

V

t

r,

t

f

(1)

Rise/fall time

C

L

= 1 nF

20

45

ns

UNDERVOLTAGE LOCKOUT (UVLO)

Start threshold voltage

Stop threshold voltage

OVLO hysteresis

UC2823B, UC2825B, UC3825B, UC3825B

16

9.2

10

0.8

6

17

UC1823A, UC1825A, UC2823A, UC2825A

UC3825A, UC3825A

8.4

9

9.6

UC2823B, UC2825B, UC3825B, UC3825B

V

UC1823A, UC1825A, UC2823A, UC2825A

UC3825A, UC3825A

0.4

5

1.2

7

UC2823B, UC2825B, UC3825B, UC3825B

SUPPLY CURRENT

I

Startup current

Input current

VC = VCC = V

TH

= −0.5 V

100

28

300

36

µA

su

mA

CC

(1)

Ensured by design. Not production tested.

5

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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

APPLICATION INFORMATION

The oscillator of the UC3823A, UC3823B, UC3825A, and UC3825B is a saw tooth. The rising edge is governed by a current

controlled by the RT pin and value of capacitance at the CT pin (C ). The falling edge of the sawtooth sets dead time for

CT

the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based

on the desired frequency (RT) and D . The design equations are:

MAX

ǒ_{1.6 D}_MAXǓ

3 V

R +

C +

T

_{10 mA}ǒ_{1 * D}_MAXǓ

ǒ_{R f}Ǔ

T

(

)

(1)

Recommended values for R range from 1 kΩ to 100 kΩ. Control of D

less than 70% is not recommended.

T

MAX

UDG−95102

Figure 1. Oscillator

OSCILLATOR FREQUENCY

vs

MAXIMUM DUTY CYCLE

vs

TIMING RESISTANCE

100

95

10 M

1 M

90

85

80

100 k

10 k

75

70

10 k

1 k

10 k

100 k

1 k

100 k

R

T

− Timing Resistance − W

R − Timing Resistance − W

T

Figure 3

Figure 2

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SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

LEADING EDGE BLANKING

The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The

UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less

than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle, one output is off.

Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%.

To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator.

On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM

comparator, current limit comparator, or the overcurrent comparator.

Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse.

Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the

pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not

require any filtering as result of leading edge blanking.

To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and

the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy,

an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%.

The design equation is:

ǒ Ǔ

+ 0.5 R ø 10 kW C

t

LEB

(2)

Values of R less than 2 kΩ should not be used.

Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold,

the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults

without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this

reason, some noise filtering may be required on the ILIM pin.

UDG−95105

Figure 4. Leading Edge Blanking Operational Waveforms

7

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ꢂ ꢃꢄ ꢅ ꢆ ꢇ

ꢅꢃ ꢄꢅ ꢆ ꢇ

ꢄꢃ ꢄꢉ ꢆ ꢇ

ꢀ

ꢁ

ꢄ

ꢅ

ꢄ

ꢃ

ꢄ

ꢅ

ꢉ

ꢆ

ꢈ

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ꢀ

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ꢃ

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www.ti.com

SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

UVLO, SOFT-START AND FAULT MANAGEMENT

Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier

output is also forced low. While the internal 9-µA source charges the SS pin, the error amplifier output follows until closed

loop regulation takes over.

Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then discharged

by a 250-µA current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is below 1.2 V. At

this point the fault latch resets and the chip executes a soft-start.

Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not

discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions.

UDG−95106

Figure 5. Soft-Start and Fault Waveforms

ACTIVE LOW OUTPUTS DURING UVLO

The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate.

UDG−95108

UDG−95106

Figure 6. Output Voltage vs Output Current

Figure 7. Output V and I During UVLO

8

ꢀꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢀꢁꢄ ꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢄ ꢃꢄ ꢅꢈ ꢇ

ꢀꢁꢅ ꢃ ꢄ ꢅ ꢆꢇ ꢀꢁꢅ ꢃ ꢄ ꢅ ꢈꢇ ꢀ ꢁꢂ ꢃꢄ ꢉꢆ ꢇ

www.ti.com

ꢀꢁꢄ ꢃ ꢄ ꢉ ꢆꢇ ꢀꢁꢄ ꢃ ꢄ ꢉ ꢈꢇ ꢀꢁꢅ ꢃ ꢄ ꢉ ꢆꢇ ꢀ ꢁꢅ ꢃꢄ ꢉꢈ

SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

CONTROL METHODS

Current Mode

Voltage Mode

UDG−95110

UDG−95109

.

Figure 8. Control Methods

SYNCHRONIZATION

The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free

running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width

should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin

can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no longer accepts an incoming

synchronizing signal.

UDG−95111

UDG−95113

Figure 9. General Oscillator Synchronization

Figure 10. Two Unit Interface

UDG−95112

Figure 11. Operational Waveforms

9

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ꢀ ꢁ

ꢂ ꢃꢄ ꢅ ꢆ ꢇ

ꢅꢃ ꢄꢅ ꢆ ꢇ

ꢄꢃ ꢄꢉ ꢆ ꢇ

ꢀ

ꢁ

ꢄ

ꢅ

ꢄ

ꢃ

ꢄ

ꢅ

ꢉ

ꢆ

ꢈ

ꢇ

ꢀ

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ꢄ

ꢂ

ꢅ

ꢃ

ꢄ

ꢅ

ꢉ

ꢈ

ꢆ

ꢇ

ꢀꢁ

ꢅ

ꢃꢄ

ꢉ

ꢈ

www.ti.com

SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

HIGH CURRENT OUTPUTS

Each totem pole output of the UC3823A and UC3823AB, UC3825A, and UC3825B can deliver a 2-A peak current into a

capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC)

and power ground (PGND) pins help decouple the device’s analog circuitry from the high-power gate drive noise. The use

of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and PGND

are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive

load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. DO NOT

USE standard silicon diodes.

Although they are single-ended devices, two output drivers are available on the UC3823A and UC3823B devices. These

can be paralleled by the use of a 0.5 Ω (noninductive) resistor connected in series with each output for a combined peak

current of 4 A.

UDG−95114

Figure 12. Power MOSFET Drive Circuit

GROUND PLANES

Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the

chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents

associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can

be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high

di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high

frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection

for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode

to both VCC and PGND. Nothing else should be connected to power ground.

VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low

ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should likewise be

bypassed to the signal ground plane.

10

ꢀꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢀꢁꢄ ꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢄ ꢃꢄ ꢅꢈ ꢇ

ꢀꢁꢅ ꢃ ꢄ ꢅ ꢆꢇ ꢀꢁꢅ ꢃ ꢄ ꢅ ꢈꢇ ꢀ ꢁꢂ ꢃꢄ ꢉꢆ ꢇ

www.ti.com

ꢀꢁꢄ ꢃ ꢄ ꢉ ꢆꢇ ꢀꢁꢄ ꢃ ꢄ ꢉ ꢈꢇ ꢀꢁꢅ ꢃ ꢄ ꢉ ꢆꢇ ꢀ ꢁꢅ ꢃꢄ ꢉꢈ

SLUS334C − AUGUST 1995 − REVISED AUGUST 2004

UDG−95115

Figure 13. Ground Planes Diagram

OPEN LOOP TEST CIRCUIT

This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any

wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly

recommended.

UDG−95116

Figure 14. Open Loop Test Circuit Schematic

11

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

LCCC

CDIP

TO-92

LCCC

CDIP

LCCC

CDIP

LCCC

CDIP

LCCC

TO-92

LCCC

CDIP

Drawing

5962-87681022A

5962-8768102EA

5962-8768102V2A

5962-8768102VEA

5962-8768102XA

5962-8768103XA

5962-89905022A

5962-8990502EA

5962-8990502VEA

UC1823AJ

ACTIVE

FK

J

20

16

20

16

28

20

16

20

16

20

16

20

28

20

16

20

28

16

1

TBD

POST-PLATE Level-NC-NC-NC

A42 SNPB

Call TI

Level-NC-NC-NC

Call TI

ACTIVE

FK

J

ACTIVE

Call TI

OBSOLETE

ACTIVE

LP

FK

J

Call TI

1

POST-PLATE Level-NC-NC-NC

ACTIVE

A42 SNPB

Call TI

Level-NC-NC-NC

Call TI

ACTIVE

J

ACTIVE

J

A42 SNPB

Call TI

UC1823AJ883B

UC1823AJQMLV

UC1823AL

ACTIVE

J

ACTIVE

J

ACTIVE

FK

J

1

POST-PLATE Level-NC-NC-NC

UC1823AL883B

UC1823BJ

ACTIVE

OBSOLETE

ACTIVE

Call TI

UC1823BJ883B

UC1823BL

J

Call TI

FK

J

Call TI

UC1823BL883B

UC1825AJ

Call TI

1

A42 SNPB

Call TI

Level-NC-NC-NC

Call TI

UC1825AJ883B

UC1825AJQMLV

UC1825AL

ACTIVE

J

ACTIVE

J

ACTIVE

FK

LP

FK

J

1

POST-PLATE Level-NC-NC-NC

UC1825AL883B

UC1825ALP883B

UC1825ALQMLV

UC1825BJ

ACTIVE

OBSOLETE

ACTIVE

Call TI

OBSOLETE

UC1825BJ883B

UC1825BL/81047

UC1825BL883B

UC1825BLP883B

UC2823ADW

J

OBSOLETE TO/SOT

L

OBSOLETE

ACTIVE

LCCC

TO-92

SOIC

FK

LP

DW

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2823ADWTR

ACTIVE

SOIC

DW

16

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2823ADWTRG4

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2823AJ

UC2823AN

ACTIVE

CDIP

PDIP

J

16

1

TBD

A42 SNPB

Level-NC-NC-NC

N

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC2823ANG4

UC2823AQ

ACTIVE

PDIP

PLCC

SOIC

N

16

20

16

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

FN

DW

46 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

UC2823BDW

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

no Sb/Br)

UC2823BDWG4

ACTIVE

SOIC

DW

16

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2823BJ

UC2823BN

OBSOLETE

ACTIVE

CDIP

PDIP

J

16

TBD

Call TI

N

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC2823BNG4

UC2825ADW

ACTIVE

PDIP

SOIC

PDIP

PLCC

SOIC

N

16

20

16

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

DW

N

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2825ADWG4

UC2825ADWTR

UC2825ADWTRG4

UC2825AN

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC2825ANG4

UC2825AQ

N

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

FN

DW

46 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

UC2825BDW

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2825BDWTR

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC2825BJ

UC2825BN

OBSOLETE

ACTIVE

CDIP

PDIP

J

16

TBD

Call TI

N

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC2825BNG4

UC3823ADW

ACTIVE

PDIP

SOIC

PDIP

SOIC

PDIP

N

16

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

DW

N

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC3823ADWG4

UC3823ADWTR

UC3823ADWTRG4

UC3823AN

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC3823ANG4

UC3823BDW

N

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

DW

N

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC3823BDWTR

UC3823BDWTRG4

UC3823BN

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

Orderable Device

UC3825ADW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

16

20

16

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC3825ADWTR

UC3825ADWTRG4

UC3825AN

SOIC

PDIP

PLCC

SOIC

PDIP

DW

N

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

UC3825AQ

FN

DW

N

46 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

UC3825AQTR

UC3825BDW

1000 Green (RoHS &

no Sb/Br)

CU SN

Level-2-260C-1 YEAR

40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UC3825BDWTR

UC3825BDWTRG4

UC3825BN

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-NC-NC-NC

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 3

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Use of such information may require a license from a third party under the patents or other intellectual property

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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amplifier.ti.com

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Digital Control

Military

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www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265


型号：	UC1823A-SP
厂家：	TEXAS INSTRUMENTS
描述：	耐辐射 QMLV、30V 输入、2A 双路输出 1MHz PWM 控制器、100% 占空比开关控制器开关式稳压器开关式控制器电源电路开关式稳压器或控制器
文件：	总15页 (文件大小：302K)
中文：	中文翻译
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UC1823AQTR

UC1823A_10

UC1823B