UC1823J

更新时间:2024-09-18 02:59:08
品牌:TI
描述:

UC1823J 概述

PWM控制器 开关式稳压器或控制器

UC1823J 规格参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.11其他特性:CAN ALSO BE CONFIGURED IN CURRENT MODE
模拟集成电路 - 其他类型:SWITCHING CONTROLLER控制模式:VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:30 V
最小输入电压:10 V标称输入电压:15 V
JESD-30 代码:R-GDIP-T16长度:19.56 mm
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
最大输出电流:2 A最大输出电压:5.15 V
最小输出电压:5.05 V标称输出电压:5.1 V
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Switching Regulator or Controllers最大供电电流 (Isup):33 mA
标称供电电压 (Vsup):15 V表面贴装:NO
切换器配置:BUCK-BOOST最大切换频率:1000 kHz
技术:BIPOLAR温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.92 mmBase Number Matches:1

UC1823J 数据手册

通过下载UC1823J数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。

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UC1823  
UC2823  
UC3823  
High Speed PWM Controller  
FEATURES  
DESCRIPTION  
Compatible with Voltage or Current-Mode  
Topologies  
The UC1823 family of PWM control ICs is optimized for high fre-  
quency switched mode power supply applications. Particular care  
was given to minimizing propagation delays through the compara-  
tors and logic circuitry while maximizing bandwidth and slew rate  
of the error amplifier. This controller is designed for use in either  
current-mode or voltage-mode systems with the capability for input  
voltage feed-forward.  
Practical Operation @ Switching  
Frequencies to 1.0MHz  
50ns Propagation Delay to Output  
High Current Totem Pole Output (1.5A peak)  
Wide Bandwidth Error Amplifier  
Protection circuitry includes a current limit comparator, a TTL com-  
patible shutdown port, and a soft start pin which will double as a  
maximum duty cycle clamp. The logic is fully latched to provide jit-  
ter free operation and prohibit multiple pulses at the output. An un-  
der-voltage lockout section with 800mV of hysteresis assures low  
start up current. During under-voltage lockout, the output is high im-  
pedance. The current limit reference (pin 11) is a DC input voltage to  
the current limit comparator. Consult specifications for details.  
Fully Latched Logic with Double Pulse  
Suppression  
Pulse-by-Pulse Current Limiting  
Soft Start/Max. Duty Cycle Control  
Under-Voltage Lockout with Hysteresis  
Low Start Up Current (1.1mA)  
These devices feature a totem pole output designed to source and  
sink high peak currents from capacitive loads, such as the gate of  
a power MOSFET. The on state is defined as a high level.  
Trimmed Bandgap Reference (5.1V ±1%)  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage (Pins 15, 13) . . . . . . . . . . . . . . . . . . . . . . . . 30V Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA  
Output Current, Source or Sink (Pin14) Power Dissipation at TA = 60 °C . . . . . . . . . . . . . . . . . . . . . 1W  
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C  
Pulse (0.5µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C  
Analog Inputs (Pins 1, 2, 7, 8, 9, 11) . . . . . . . . . . . -0.3V to +6V Note: All voltages are with respect to ground, Pin 10.  
Currents are positive into the specified terminal.  
Consult Packaging Section of Databook for thermal  
limitations and considerations of packages.  
Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA  
Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA  
Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA  
BLOCK DIAGRAM  
3/97  
1
UC1823  
UC2823  
UC3823  
CONNECTION DIAGRAMS  
DIL-16, SOIC-16 (TOP VIEW)  
J or N, DW Package  
PLCC-20, LCC-20 (TOP VIEW)  
Q, L Package  
PACKAGE PIN FUNCTION  
FUNCTION  
N/C  
PIN  
1
Inv.  
2
N.I.  
3
E/A Out  
Clock  
N/C  
4
5
6
RT  
7
CT  
8
Ramp  
Soft start  
N/C  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
ILIM/S.D.  
Ground  
ILIM REF  
PWR Gnd  
N/C  
VC  
OUT  
VCC  
VREF 5.1V  
ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT = 3.65k, CT =  
1nF, VCC = 15V, 0°C < TA < +70°C for the UC3823, -25°C < TA < +85°C for  
the UC2823, and -55°C < TA < +125°C for the UC1823, TA = TJ.  
UC1823  
UC2823  
UC3823  
UNITS  
PARAMETER  
Reference Section  
TEST CONDITIONS  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
Output Voltage  
Line Regulation  
TJ = 25°C, lO = 1mA  
5.05  
5.10  
2
5.15  
20  
5.00  
5.10  
2
5.20  
20  
V
10 < VCC < 30V  
1 < IO < 10mA  
mV  
mV  
Load Regulation  
5
20  
5
20  
Temperature Stability*  
Total Output Variation*  
Output Noise Voltage*  
Long Term Stability*  
Short Circuit Current  
Oscillator Section  
Initial Accuracy*  
TMIN < TA < TMAX  
Line, Load, Temp.  
10Hz < f < 10kHz  
TJ = 125°C, 1000 hrs.  
VREF=0V  
0.2  
0.4  
5.20  
0.2  
0.4 mV/°C  
5.00  
4.95  
5.25  
50  
5
50  
5
µV  
25  
25  
mV  
mA  
-15  
-50  
-100  
-15  
-50  
-100  
TJ=25°C  
360  
400  
0.2  
5
440  
2
360  
400  
0.2  
5
440  
2
kHz  
%
%
kHz  
V
Voltage Stability*  
Temperature Stability*  
Total Variation*  
10 < VCC < 30V  
TMIN <TA < TMAX  
Line, Temp.  
340  
3.9  
460  
340  
3.9  
460  
Clock Out High  
4.5  
2.3  
2.8  
1.0  
1.8  
4.5  
2.3  
2.8  
1.0  
1.8  
Clock Out Low  
2.9  
3.0  
2.9  
3.0  
V
Ramp Peak*  
2.6  
0.7  
1.6  
2.6  
0.7  
1.6  
V
Ramp Valley*  
1.25  
2.0  
1.25  
2.0  
V
Ramp Valley to Peak*  
V
* These parameters are guaranteed by design but not 100% tested in production.  
2
UC1823  
UC2823  
UC3823  
ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT = 3.65k, CT = 1nF, VCC  
= 15V, 0°C < TA < +70°C for the UC3823, -25°C < TA < +85°C for the  
UC2823, and -55°C < TA < +125°C for the UC1823, TA = TJ.  
UC1823  
UC2823  
UC3823  
TYP  
UNITS  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
MIN  
MAX  
Error Amplifier Section  
Input Offset Voltage  
Input Bias Current  
Input Offset Current  
Open Loop Gain  
10  
3
15  
3
mV  
µA  
0.6  
0.1  
95  
0.6  
0.1  
95  
1
1
µA  
1 < VO < 4V  
60  
75  
85  
1
60  
75  
85  
1
dB  
CMRR  
1.5 < VCM < 5.5V  
10 < VCC < 30V  
VPIN 3 =1V  
95  
95  
dB  
PSRR  
110  
2.5  
-1.3  
4.7  
0.5  
5.5  
12  
110  
2.5  
-1.3  
4.7  
0.5  
5.5  
12  
dB  
Output Sink Current  
Output Source Current  
Output High Voltage  
Output Low Voltage  
Unity Gain Bandwidth*  
Slew Rate*  
mA  
mA  
V
VPIN 3 = 4V  
-0.5  
4.0  
0
-0.5  
4.0  
0
IPIN 3 = 0.5mA  
IPIN 3 = 1mA  
5.0  
1.0  
5.0  
1.0  
V
3
3
MHz  
V/µS  
6
6
PWM Comparator Section  
Pin 7 Bias Current  
Duty Cycle Range  
Pin 3 Zero D.C. Threshold  
Delay to Output*  
VPIN 7 = 0V  
VPIN 7 = 0V  
-1  
-5  
-1  
-5  
µA  
%
V
0
80  
0
85  
1.1  
1.25  
50  
1.1  
1.25  
50  
80  
20  
80  
20  
ns  
Soft-Start Section  
Charge Current  
V
PIN 8 = 0.5V  
3
1
9
3
1
9
µA  
Discharge Current  
Current Limit/Shutdown Section  
Pin 9 Bias Current  
Current Limit Offset  
VPIN 8 = 1V  
mA  
0 < VPIN 9 < 4V  
VPIN 11 = 1.1V  
±10  
15  
±10  
15  
µA  
mV  
V
Current Limit Common Mode  
Range (VPIN 11)  
1.0  
1.25  
1.0  
1.25  
Shutdown Threshold  
Delay to Output*  
1.25  
1.40  
50  
1.55  
80  
1.25  
1.40  
50  
1.55  
80  
V
ns  
Output Section  
Output Low Level  
IOUT = 20mA  
IOUT = 200mA  
IOUT = 20mA  
IOUT = 200mA  
VC = 30V  
0.25  
1.2  
0.40  
2.2  
0.25  
1.2  
0.40  
2.2  
V
V
Output High Level  
13.0  
12.0  
13.5  
13.0  
100  
30  
13.0  
12.0  
13.5  
13.0  
100  
30  
V
V
Collector Leakage  
Rise/Fall Time*  
500  
60  
500  
60  
µA  
ns  
CL = 1nF  
Under-Voltage Lockout Section  
Start Threshold  
8.8  
0.4  
9.2  
0.8  
9.6  
1.2  
8.8  
0.4  
9.2  
0.8  
9.6  
1.2  
V
V
UVLO Hysteresis  
Supply Current  
Start Up Current  
ICC  
VCC = 8V  
1.1  
22  
2.5  
33  
1.1  
22  
2.5  
33  
mA  
mA  
VPIN 1, VPIN 7, VPIN 9 =0V, VPIN 2 = 1V  
* These parameters are guaranteed by design but not 100% tested in production.  
3
UC1823  
UC2823  
UC3823  
UC1823 PRINTED CIRCUIT BOARD LAYOUT  
CONSIDERATIONS  
High speed circuits demand careful attention to layout  
and component placement. To assure proper perform-  
ance of the UC1823, follow these rules. 1) Use a ground  
plane. 2) Damp or clamp parasitic inductive kick energy  
from the gate of driven MOSFET. Don’t allow the output  
pins to ring below ground. A series gate resistor or a  
shunt 1 Amp Schottky diode at the output pin will serve  
this purpose. 3) Bypass VCC, VC, and VREF. Use 0.1µF  
monolithic ceramic capacitors with low equivalent series  
inductance. Allow less than 1 cm of total lead length for  
each capacitor between the bypassed pin and the ground  
plane. 4) Treat the timing capacitor, CT, like a bypass ca-  
pacitor.  
ERROR AMPLIFIER CIRCUIT  
Simplified Schematic  
Unity Gain Slew Rate  
Open Loop Frequency Response  
PWM APPLICATIONS  
Conventional (Voltage Mode)  
Current-Mode  
* A small filter may be required to suppress switch  
4
UC1823  
UC2823  
UC3823  
OSCILLATOR CIRCUIT  
SYNCHRONIZED OPERATION  
Two Units in Close Proximity  
Generalized Synchronization  
5
UC1823  
UC2823  
UC3823  
CONSTANT VOLT-SECOND CLAMP CIRCUIT  
The circuit shown here will achieve a constant  
volt-second product clamp over varying input  
voltages. The ramp generator components, RT and CR  
are chosen so that the ramp at Pin 9 crosses the 1V  
threshold at the same time the desired maximum  
volt-second product is reached. The delay through the  
inverter must be such that the ramp capacitor can be  
completely discharged during the minimum deadtime.  
OUTPUT SECTION  
FEED FORWARD TECHNIQUE FOR OFF-LINE VOLTAGE MODE APPLICATION  
UNITRODE CORPORATION  
7 CONTINENTAL BLVD. MERRIMACK, NH 03054  
TEL. (603) 424-2410 FAX (603) 424-3460  
6
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1999, Texas Instruments Incorporated  

UC1823J 替代型号

型号 制造商 描述 替代类型 文档
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