UC182DWTR [TI]

UC182DWTR;


型号：	UC182DWTR
厂家：	TEXAS INSTRUMENTS
描述：	UC182DWTR
文件：	总9页 (文件大小：474K)
中文：	中文翻译
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UC1861-1868

UC2861-2868

UC3861-3868

Resonant-Mode Power Supply Controllers

FEATURES

DESCRIPTION

• Controls Zero Current Switched (ZCS) The UC1861-1868 family of ICs is optimized for the control of Zero Cur-

or Zero Voltage Switched (ZVS)

Quasi-Resonant Converters

rent Switched and Zero Voltage Switched quasi-resonant converters. Dif-

ferences between members of this device family result from the various

combinations of UVLO thresholds and output options. Additionally, the

one-shot pulse steering logic is configured to program either on-time for

ZCS systems (UC1865-1868), or off-time for ZVS applications (UC1861-

1864).

• Zero-Crossing Terminated One-Shot

Timer

• Precision 1%, Soft-Started 5V

Reference

The primary control blocks implemented include an error amplifier to com-

pensate the overall system loop and to drive a voltage controlled oscillator

(VCO), featuring programmable minimum and maximum frequencies. Trig-

gered by the VCO, the one-shot generates pulses of a programmed maxi-

mum width, which can be modulated by the Zero Detection comparator.

This circuit facilitates “true” zero current or voltage switching over various

line, load, and temperature changes, and is also able to accommodate the

resonant components' initial tolerances.

• Programmable Restart Delay

Following Fault

• Voltage-Controlled Oscillator (VCO)

with Programmable Minimum and

Maximum Frequencies from 10kHz to

1MHz

• Low Start-Up Current (150µA typical)

• Dual 1 Amp Peak FET Drivers

Under-Voltage Lockout is incorporated to facilitate safe starts upon

power-up. The supply current during the under-voltage lockout period is

typically less than 150µA, and the outputs are actively forced to the low

• UVLO Option for Off-Line or DC/DC

Applications

state.

(continued)

Device

UVLO

1861

1862

1863

36014

1864

36014

1865

1866

1867

36014

1868

36014

16.5/10.5

Alternating

Off Time

16.5/10.5

Parallel

Off Time

16.5/10.5

Alternating

On Time

16.5/10.5

Parallel

On Time

Outputs

“Fixed”

Alternating

Off Time

Parallel

Off Time

Alternating

On Time

Parallel

On Time

BLOCK DIAGRAM

UDG-92018

Pin numbers refer to the J and N packages.

10/98

UC1861-1868

UC2861-2868

UC3861-3868

DESCRIPTION (cont.)

UVLO thresholds for the UC1861/62/65/66 are 16.5V start delay, and the internal system reference.

(ON) and 10.5V (OFF), whereas the UC1863/64/67/68

Each device features dual 1 Amp peak totem pole output

drivers for direct interface to power MOSFETS. The out-

puts are programmed to alternate in the

UC1861/63/65/67 devices. The UC1862/64/66/68 out-

puts operate in unison alllowing a 2 Amp peak current.

thresholds are 8V (ON) and 7V (OFF). After V

ex-

ceeds the UVLO threshold, a 5V generator is enabled

which provides bias for the internal circuits and up to

10mA for external usage.

A Fault comparator serves to detect fault conditions and

set a latch while forcing the output drivers low. The Soft-

Ref pin serves three functions: providing soft start, re-

CONNNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V

Output Current

Source or Sink (Pins 11 & 14) . . . . . . . . . . . . . . . . . . . . . 0.5A

DC Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5A

Power Ground Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2V

Inputs (Pins 2, 3, 10, & 15) . . . . . . . . . . . . . . . . . . . . –0.4 to 7V

Error Amp Output Current . . . . . . . . . . . . . . . . . . . . . . . . 2mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Junction Temperature (Operating). . . . . . . . . . . . . . . . . . 150°C

Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C

PLCC-20 & LCC-20 (Top View)

Q & L Package

PACKAGE PIN FUNCTION

FUNCTION

Soft Ref

INV

E/A Out

Sig Gnd

Range

RMIN

CVCO

Zero

A Out

Pwr Gnd

VCC

All voltages are with respect to signal ground and all currents

are positive into the specified terminal. Pin numbers refer to

the J and N packages. Consult Unitrode Integrated Circuits da-

tabook for information regarding thermal specifications and

limitations of packages.

DIL-16, SOIC-16 (Top View)

J or N, DW Packages

B Out

UC1861-1868

UC2861-2868

UC3861-3868

ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for –55°C≤TA≤125°C for the

UC186x, –25°C≤TA≤85°C for the UC286x, and 0°C≤TA≤70°C for the UC386x, VCC=12V, CVCO=1nF, Range=7.15k, RMIN=86.6k,

C=200pF, R=4.02k, and Csr=0.1µF. TA=TJ .

PARAMETER

5V Generator

TEST CONDITIONS

MIN

TYP MAX UNITS

Output Voltage

Short Circuit Current

Soft-Reference

12V ≤ Vcc ≤ 20V, –10mA ≤ IO ≤ 0mA

4.8

5.0

5.2

VO = 0V

–150

–15

Restart Delay Current

Soft Start Current

Reference Voltage

V = 2V

µA

V = 2V

–650 –500 –350

TJ = 25°C, IO = 0A

12V ≤ VCC ≤ 20V, –200µA ≤ IO ≤ 200µA

12V ≤ VCC ≤ 20V

–200µA ≤ IO ≤ 200µA

4.95

4.85

5.00

5.05

5.15

Line Regulation

Load Regulation

Error Amplifier (Note 3)

Input Offset Voltage

Input Bias Current

VCM = 5V, Vo = 2V, IO = 0A

VCM = 0V

–10

–2.0

µA

–0.3

100

Voltage Gain

Vcm = 5V, 0.5V ≤ VO ≤ 3.7V, IO = 0A

Vcm = 5V, VO = 2V, 12V ≤ VCC ≤ 20V

Power Supply Rejection Ratio

Error Amplifier (Note 3) (cont.)

Common Mode Rejection Ratio

VOUT Low

0V ≤ Vcm ≤ 6V, VO = 2V

VID = –100mV, IO = 200µA

VID = 100mV, IO = –200µA

(Note 4)

100

0.17

4.2

0.25

VOUT High

3.9

0.5

Unity Gain Bandwidth

Voltage Controlled Oscillator

Maximum Frequency

0.8

MHz

VID (Error Amp) = 100mV, TJ = 25°C

VID (Error Amp) = 100mV

450

425

500

550

575

kHz

Minimum Frequency

VID (Error Amp) = –100mV, TJ = 25°C

VID (Error Amp) = –100mV

One Shot

Zero Comparator Vth

Propagation Delay

Maximum Pulse Width

Maximum to Minimum Pulse

Width Ratio

0.45

0.50

120

0.55

200

(Note 4)

VZERO = 1V

850

2.5

1000 1150

VZERO = 0V UCx861 – UCx864

VZERO = 0V UCx865 – UCx868. –55°C to +85°C

VZERO = 0V UCx865 – UCx868, +125°C

5.5

3.8

Output Stage

Rise and Fall Time

Output Low Saturation

CLOAD = 1nF (Note 4)

IO = 20mA

0.2

0.5

1.7

0.8

0.5

2.2

2.5

1.5

IO = 200mA

Output High Saturation

UVLO Low Saturation

Fault Comparator

Fault Comparator Vth

Delay to Output

IO = –200mA, down from Vcc

IO = 20mA

2.85

3.00

100

3.15

200

(Note 4) (Note 5)

UC1861-1868

UC2861-2868

UC3861-3868

ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for –55°C≤TA≤125°C for the

UC186x, –25°C≤TA≤85°C for the UC286x, and 0°C≤TA≤70°C for the UC386x, VCC=12V, CVCO=1nF, Range=7.15k, RMIN=86.6k,

C=200pF, R=4.02k, and Csr=0.1µF. TA=TJ .

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNITS

UVLO

Vcc Turn-on Threshold

Vcc Turn-off Threshold

UCx861, UCx862, UCx865, UCx866

UCx863, UCx864, UCx867, UCx868

UCx861, UCx862, UCx865, UCx866

UCx863, UCx864, UCx867, UCx868

VCC = VCC(on) – 0.3V

16.5

8.0

9.5

10.5

7.0

11.5

Icc Start

Icc Run

150

300

µA

VID = 100mV

Note 1: Currents are defined as positive into the pin.

Note 2: Pulse measurement techniques are used to insure that TJ = TA.

Note 3: VID = V(NI) – V(INV).

Note 4: This parameter is not 100% tested in production but guaranteed by design.

Note 5: Vi = 0 to 4V

tr(Vi) 10ns

tpd = t(Vo = 6V) – t(Vi = 3V)

APPLICATION INFORMATION

UVLO & 5V GENERATOR (See Figure 1): When power The fault pin is input to a high speed comparator with a

is applied to the chip and Vcc is less than the upper threshold of 3V. In the event of a detected fault, the fault

latch is set and the outputs are driven low. If Soft-Ref is

above 4V, the delay latch is set. Restart delay is timed as

Soft-Ref is discharged by 20µA. When Soft-Ref is fully

discharged, the fault latch is reset if the fault input signal

is low. The Fault pin can be used as a system shutdown

pin.

UVLO threshold, Icc will be less than 300µA, the 5V gen-

erator will be off, and the outputs will be actively held low.

When Vcc exceeds the upper UVLO threshold, the 5V

generator turns on. Until the 5V pin exceeds 4.9V, the

outputs will still remain low.

The 5V pin should be bypassed to signal ground with a

0.1µF capacitor. The capacitor should have low equiva-

lent series resistance and inductance.

If a fault is detected during soft-start, the fault latch is set

and the outputs are driven low. The delay latch will re-

main reset until Soft-Ref charges to 4V. This sets the de-

lay latch, and restart delay is timed. Note that restart

delay for a single fault event is longer than for recurring

faults since Soft-Ref must be discharged from 5V instead

of 4V.

FAULT AND SOFT-REFERENCE (See Figure 1): The

Soft-Ref pin serves three functions: system reference, re-

start delay, and soft-start. Designed to source or sink

200µA, this pin should be used as the input reference for

the error amplifier circuit. This pin requires a bypass ca-

pacitor of at least 0.1µF. This yields a minimum soft-start

time of 1ms.

The restart delay to soft-start time ratio is 24:1 for a fault

occurring during normal operation and 19:1 for faults oc-

curring during soft-start. Shorter ratios can be pro-

grammed down to a limit of approximately 3:1 by the

addition of a 20kΩ or larger resistor from Soft-Ref to

ground.

Under-Voltage Lockout sets both the fault and restart de-

lay latches. This holds the outputs low and discharges

the Soft-Ref pin. After UVLO, the fault latch is reset by

the low voltage on the Soft-Ref pin. The reset fault latch

resets the delay latch and Soft-Ref charges via the 0.5mA

current source.

A 100kΩ resistor from Soft-Ref to 5V will have the effect

of permanent shut down after a fault since the internal

20µA current source can't pull Soft-Ref low. This feature

can be used to require recycling Vcc after a fault. Care

must be taken to insure Soft-Ref is indeed low at start up,

or the fault latch will never be reset.

UC1861-1868

UC2861-2868

UC3861-3868

APPLICATION INFORMATION

UDG-92020

UDG-92021-1

Figure 1. UVLO, 5V, fault and soft-ref.

UDG-92022-1

UDG-92023-1

Figure 2. Error Amp, Voltage Controlled Oscillator, and One Shot

UC1861-1868

UC2861-2868

UC3861-3868

APPLICATION INFORMATION

Minimum oscillator frequency is set by Rmin and Cvco. The Error Amplifier directly controls the oscillator fre-

The minimum frequency is approximately given by the quency. E/A output low corresponds to minimum fre-

equation:

quency and output high corresponds to maximum

frequency. At the end of each oscillator cycle, the RC pin

is discharged to one diode drop above ground. At the be-

ginning of the oscillator cycle, V(RC) is less than Vth1

and so the output of the zero detect comparator is ig-

nored. After V(RC) exceeds Vth1, the one shot pulse will

be terminated as soon as the zero pin falls below 0.5V or

V(RC) exceeds Vth2. The minimum one shot pulse width

is approximately given by the equation:

4.3

F_MIN

R_MIN• C_VCO

Maximum oscillator frequency is set by Rmin, Range &

Cvco. The maximum frequency is approximately given by

the equation:

3.3

F_MAX

(R_MIN/ / Range )• C_VCO

Tpw(min) 0.3

The maximum pulse width is approximately given by:

Tpw(max) 1.2 C.

STEERING LOGIC

UDG-92014

UDG-92013

The steering logic is configured on the UC1861,63 to result in

dual non-overlapping square waves at outputs A & B. This is

suited to drive dual switch ZVS systems.

The steering logic is configured on the UC1862,64 to result in

inverted pulse trains occurring identically at both output pins.

This is suited to drive single switch ZVS systems. Both outputs

are available to drive the same MOSFET gate. It is advisable

to join the pins with 0.5 ohm resistors.

UDG-92015

The steering logic is configured on the UC1865,67 to result in

alternating pulse trains at outputs A & B. This is suited to drive

dual switch ZCS systems.

UDG-92016

The steering logic is configured on the UC1866,68 to result in

non-inverted pulse trains occurring identically at both output

pins. This is suited to drive single switch ZCS systems. Both

outputs are available to drive the same MOSFET gate. It is ad-

visable to join the pins with 0.5 ohm resistors.

UC1861-1868

UC2861-2868

UC3861-3868

APPLICATION INFORMATION (cont.)

UDG-92017

Figure 3. Current waveforms.

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TEL. (603) 424-2410 • FAX (603) 424-3460

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UC182DWTR [TI]

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