UC1843AMDREPG4 [TI]
Enhanced Product Current-Mode Pwm Controller 8-SOIC -55 to 125;
| 型号： | UC1843AMDREPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Enhanced Product Current-Mode Pwm Controller 8-SOIC -55 to 125 开关 光电二极管 |
| 文件： | 总15页 (文件大小：1004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
D
D
D
D
D
D
D
D
D
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Under-Voltage Lockout With Hysteresis
Double Pulse Suppression
Site
D
D
D
D
D
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
High Current Totem Pole Output
Internally Trimmed Bandgap Reference
500 kHz Operation
Enhanced Product Change Notification
†
Qualification Pedigree
Low R Error Amp
O
Optimized for Off-line and DC-to-DC
Converters
D PACKAGE
(TOP VIEW)
D
Low Start Up Current (<0.5 mA)
D
Trimmed Oscillator Discharge Current
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
COMP
VFB
ISENSE
RT/CT
VREF
VCC
OUTPUT
GND
1
2
3
4
8
7
6
5
description
The UC1842A/3A/4A/5A family of control ICs is a pin-for-pin compatible improved version of the UC3842/3/4/5
family. Providing the necessary features to control current mode switched mode power supplies, this family has
the following improved features. Start up current is guaranteed to be less than 0.5 mA. Oscillator discharge is
trimmed to 8.3 mA. During under voltage lockout, the output stage can sink at least 10 mA at less than 1.2 V
for V over 5 V.
CC
The difference between members of this family are shown in the table below.
PART NUMBER
UC1842A
UVLO ON
16 V
UVLO OFF
10 V
MAXIMUM DUTY CYCLE
<100%
<100%
<50%
UC1843A
8.5 V
7.9 V
UC1844A
16 V
10 V
UC1845A
8.5 V
7.9 V
<50%
‡
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
‡
T
PACKAGE
A
PART NUMBER
UC1842AMDREP
UC1843AMDREP
UC1844AMDREP
UC1845AMDREP
−55°C to 125°C
−55°C to 125°C
−55°C to 125°C
−55°C to 125°C
SOP − D
SOP − D
SOP − D
SOP − D
Tape and reel
Tape and reel
Tape and reel
Tape and reel
1842AME
1843AME
1844AME
1845AME
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
block diagram
NOTES: 1. Toggle flip flop used only in 1844A and 1845A.
Ordering Information
184
4
M
UC
A
D
R
EP
ENHANCED PLASTIC INDICATOR
TAPE and REEL INDICATOR
PACKAGE
D
= Plastic SOIC
MILITARY TEMPERATURE RANGE INDICATOR
IMPROVED PERFORMANCE INDICATOR
PRODUCT OPTION
2 through 5
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†‡
V
V
voltage (low impedance source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
CC
voltage (I mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . self limiting
CC
CC
Output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
O
Output energy (capacitive load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 μJ
Analog Inputs (pins 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.3 V
Error Amp Output Sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Power Dissipation at T < 25_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
A
Package thermal impedance, θ (see Note 1): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
JA
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
stg
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C
J
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260_C
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals.
NOTE 1: Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER
Reference Section
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output voltage
4.95
5
6
6
5.05
20
V
T = 25_C, I = 1 mA
J
O
Line regulation voltage
Load regulation voltage
Temperature stability
Total output variation voltage
V
IN
= 12 V to 25 V
mV
mV
I
O
= 1 mA to 20 mA
25
See Notes NO TAG and NO TAG
Line, Load, Temp.
0.2
0.4 mV/_C
5.1
4.9
V
f = 10 Hz to 10 kHz,
See Note NO TAG
Output noise voltage
T = 25_C
J
50
μV
Long term stability
Output short-circuit current
Oscillator Section
Initial accuracy
1000 hours, See Note 2
T = 125_C
5
25
mV
mA
A
−30
−100
−180
See Note NO TAG
T = 25_C
J
47
52
0.2%
5%
57
kHz
Voltage stability
V
CC
= 12 V to 25 V
1%
Temperature stability
Amplitude peak-to-peak
T = MIN to MAX, See Note 2
A
V pin 4, See Note 2
1.7
V
T = 25_C
7.8
7.5
8.3
8.8
8.8
J
Discharge current
V pin 4 = 2 V, See Note 3
mA
T = Full range
J
NOTES: 1. Adjust V above the start threshold before setting at 15 V.
CC
2. Not production tested.
3. This parameter is measured with R = 10 kΩ to V
. This contributes approximately 300 μA of current to the measurement. The
REF
T
total current flowing into the R
pin will be approximately 300 μA higher than the measured value.
T/C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER
Error Amplifier Section
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input voltage
COMP = 2.5 V
2.45
2.5
2.55
V
μA
dB
MHz
dB
mA
mA
V
Input bias current
Open loop voltage gain (A
Unity gain bandwidth
PSRR
−0.3
90
1
−1
V
O
= 2 V to 4 V
65
0.7
60
VOL)
See Note 2
= 12 V to 25 V
T = 25_C
J
V
CC
70
6
Output sink current
Output source current
FB = 2.7 V, COMP = 1.1 V
FB = 2.3 V, COMP = 5 V
2
−0.5
5
−0.8
6
V
OUT
V
OUT
high
low
FB = 2.3 V, R = 15 kΩ to GND
L
FB = 2.7 V, R = 15 kΩ to V
0.7
1.1
V
L
REF
Current Sense Section
Gain
See Note 3 and Note 4
COMP = 5 V, See Note 3
2.85
0.9
3
1
3.15
1.1
V/V
V
Maximum input signal
PSRR
V
CC
= 12 V to 25 V, See Note 3
70
dB
μA
ns
Input bias current
Delay to output
Output Section (OUT)
−2
150
−10
I
= 0 V to 2 V, See Note 2
300
SENSE
I
I
I
I
= 20 mA
0.1
15
0.4
2.2
OUT
OUT
OUT
OUT
Low-level output voltage
High-level output voltage
V
V
= 200 mA
= −20 mA
13
12
13.5
13.5
50
= −200 mA
Rise time
C = 1 nF, See Note 2
T = 25_C
J
150
150
1.2
ns
ns
V
L
J
Fall time
C = 1 nF, See Note 2
T = 25_C
50
L
UVLO saturation
V
= 5 V, I
= 10 mA
0.7
CC
OUT
Undervoltage Lockout Section
UC1842A,
UC1844A
15
7.8
9
16
8.4
10
17
9
Start threshold
V
V
UC1843A,
UC1845A
UC1842A,
UC1844A
11
8.2
Minimum operation voltage after turn on
UC1843A,
UC1845A
7
7.6
NOTES: 1. Adjust V above the start threshold before setting at 15 V.
CC
2. Not production tested.
3. Parameter measured at trip point of latch with V at 0 V.
FB
4. Gain is defined by:
; 0 v V
v 0.8 V.
DV
SENSE
COMP
A =
DV
SENSE
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM Section
UC1842A, UC1843A
UC1844A, UC1845A
94%
47%
96%
100%
50%
0%
Maximum duty cycle
48%
Minimum duty cycle
Total Standby Current
Start-up current
0.3
11
0.5
17
mA
mA
V
Operating supply current
FB = 0 V, SENSE = 0 V
= 25 mA
V
CC
internal zener voltage
I
30
34
CC
NOTES: 1. Adjust V above the start threshold before setting at 15 V.
CC
PARAMETER MEASUREMENT INFORMATION
Error Amp can source and sink up to 0.5 mA and sink up to 2 mA.
Figure 1. Error Amp Configuration
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
PARAMETER MEASUREMENT INFORMATION
During UVLO, the Output is low.
Figure 2. Under Voltage Lockout
Peak Current (Is) is determined by the following formula:
1V
RS
IsmaxȀ
A small RC filter may be required to suppress switch transients.
Figure 3. Current Sense Circuit
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
PARAMETER MEASUREMENT INFORMATION
Error Amplifier Open-Loop Frequency Response
Output Saturation Characteristics
Figure 5
Figure 4
APPLICATION INFORMATION
Oscillator Frequency vs Timing Resistance
Maximum Duty Cycle vs Timing Resistor
Figure 6. Oscillator
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
APPLICATION INFORMATION
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Figure 7. Open-Loop Laboratory Text Fixture
A fraction of the oscillator ramp can be resistively summed
with the current sense signal to provide slope compensation
for converters requiring duty cycles over 50%.
Note that capacitor, C, forms a filter with R2 to suppress the
leading edge switch spikes.
Figure 8. Slope Compression
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
APPLICATION INFORMATION
Power Supply Specifications
1. Input Voltage
2. Line Isolation
95VAC to 130VAC (50 Hz/60 Hz)
3750 V
3. Switching Frequency 40 kHz
4. Efficiency, Full Load
5. Output Voltage:
70%
A. +5V, 5%; 1A to 4A Load
B. +12V, 3%; 0.1A to 0.3A Load Ripple voltage: 100 mV P-P Max
C. −12V, 3%; 0.1A to 0.3A Load Ripple voltage: 100 mV P-P Max
Figure 9. Off-Line Flyback Regulator
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2014
PACKAGING INFORMATION
Orderable Device
UC1842AMDREP
UC1843AMDREP
UC1843AMDREPG4
UC1844AMDREP
UC1845AMDREP
UC1845AMDREPG4
V62/03625-01YE
V62/03625-02YE
V62/03625-03YE
V62/03625-04YE
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1842AME
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
D
D
D
D
D
2500
2500
2500
2500
2500
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
1843AME
1843AME
1844AME
1845AE
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1845AE
Green (RoHS
& no Sb/Br)
1842AME
1843AME
1844AME
1845AE
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2014
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP :
Catalog: UC1842A, UC1843A, UC1844A, UC1845A
•
Space: UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC1842AMDREP
UC1843AMDREP
UC1844AMDREP
UC1845AMDREP
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC1842AMDREP
UC1843AMDREP
UC1844AMDREP
UC1845AMDREP
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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