UC1860 [TI]
Resonant Mode Power Supply Controller; 谐振模式电源控制器
| 型号： | UC1860 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Resonant Mode Power Supply Controller |
| 文件： | 总9页 (文件大小：586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1860
UC2860
UC3860
Resonant Mode Power Supply Controller
FEATURES
DESCRIPTION
•
3MHz VFO Linear over 100:1 Range
The UC1860 family of control ICs is a versatile system for resonant mode
power supply control. This device easily implements frequency modulated
fixed-on-time control schemes as well as a number of other power supply
control schemes with its various dedicated and programmable features.
•
5MHz Error Amplifier with Controlled
Output Swing
•
Programmable One Shot Timer—
Down to 100ns
The UC1860 includes a precision voltage reference, a wide-bandwidth er-
ror amplifier, a variable frequency oscillator operable to beyond 3MHz, an
oscillator-triggered one-shot, dual high-current totem-pole output drivers,
and a programmable toggle flip-flop. The output mode is easily pro-
grammed for various sequences such as A, off, B, off; A & B, off; or A, B,
off. The error amplifier contains precision output clamps that allow pro-
gramming of minimum and maximum frequency.
•
•
•
•
•
•
Precision 5V Reference
Dual 2A Peak Totem Pole Outputs
Programmable Output Sequence
Programmable Under Voltage Lockout
Very Low Start Up Current
The device also contains an uncommitted comparator, a fast comparator
for fault sensing, programmable soft start circuitry, and a programmable
restart delay. Hic-up style response to faults is easily achieved. In addi-
tion, the UC1860 contains programmable under voltage lockout circuitry
that forces the output stages low and minimizes supply current during
start-up conditions.
Programmable Fault Management &
Restart Delay
•
Uncommitted Comparator
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (pin 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Comparator Output Voltage (pin 15) . . . . . . . . . . . . . . . . . . 15V
Output Current, Source or Sink (pins 17 & 20) Soft Start or Restart Delay Sink Current (pins 22 & 23) . . . 5mA
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A Power Dissipation at TA = 50°C (DIP) . . . . . . . . . . . . . . . 1.25W
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0A Power Dissipation at TA = 50°C (PLCC) . . . . . . . . . . . . . . . . 1W
Power Ground Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . 300°C
Inputs (pins 1, 2, 3, 4, 8, 9, 11, 12,
Note: All voltages are with respect to signal ground and all
currents are positive into the specified terminal.
Pin numbers refer to the DIP.
13, 14, 21, 22, 23 & 24) . . . . . . . . . . . . . . . . . . . . . . -0.4 to 6V
Error Amp Output Current, Source or Sink (pin 5). . . . . . . . 2mA
IVFO Current (pin 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
Comparator Output Current (pin 15) . . . . . . . . . . . . . . . . . . 5mA
Refer to Packaging Section of Databook for thermal
limitations and considerations of packages.
BLOCK DIAGRAM
10/93
UC1860
UC2860
UC3860
CONNECTION DIAGRAM
PIN PACKAGE FUNCTION
PLCC-28, LCC-28
(TOP VIEW)
Q or L Package
DIL - 24 (TOP VIEW)
J or N Package
FUNCTION
S GND
PIN
1
IVFO
2
CVFO
3
RC
4
VREF
5
CMP IN (-)
CMP IN (+)
TRIG
6
7
8
OSC DSBL
CMP OUT
N/C
9
10
11, 12
13
14
15
16
17
18, 19
20
21
22
23
24
25
26
27
28
OUT A
PGND
N/C
VCC
OUT B
N/C
MODE
SFT STRT
RST DLY
UVLO
FLT (-)
FLT (+)
EA IN (+)
EA IN (-)
EA OUT
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, all specifications apply for -55°C ≤ TA ≤ 125°C for the
UC1860, -25°C ≤ TA ≤ 85°C for the UC2860, 0 ≤ TA ≤ 70°C for the UC3860, VCC =
12V, CVFO = 330pF, IVFO = 0.5mA, C = 330pF, and R = 2.7k, TA = TJ.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Section
Output Voltage
TA = 25°C, IO = 0
IO = 0, Over Temp
4.95
4.93
5.00
5.05
5.07
15
V
V
Line Regulation
Load Regulation
10 ≤ VCC ≤ 20V
0≤ IO ≤ 10mA
10Hz ≤ f ≤ 10kHz
VREF = 0V
2
2
mV
25
mV
Output Noise Voltage*
Short Circuit Current
Error Amplifier Section
Input Offset Voltage
Input Bias Current
Open Loop Gain
50
µVRMS
mA
-150
-15
2.8 ≤ VCM ≤ 4.5V
1
50
80
100
0
8
mV
nA
500
dVO = 1.5V
60
70
-8
dB
PSRR
10 ≤ VCC ≤ 20V
-0.1 ≤ IO ≤ 0.1mA
-0.5 ≤ IO ≤ 0.5mA
RIN = 2k
dB
Output Low (VO-VIVFO)
Output High (VO-VIVFO)
Unity Gain Bandwidth*
Oscillator Section
Nominal Frequency*
8
mV
V
1.9
4
2
2.1
5
MHz
1.0
2
1.5
3
2.0
4
MHz
dF/dIOSC*
100 ≤ IVFO ≤ 500µA
GHz/A
*Guaranteed by design but not 100% tested.
2
UC1860
UC2860
UC3860
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications apply for -55°C ≤ TA ≤ 125°C for the
UC1860, -25° ≤ TA ≤ 85°C for the UC2860, 0 ≤ TA ≤ 70°C for the UC3860, VCC =
12V, CVFO = 330pF, IVFO = 0.5mA, C = 330pF, and R = 2.7k, TA = TJ.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator Section (cont’d)
Trig in Threshold
1.0
0.7
0.3
5
1.4
0.9
0.5
12
3
1.8
1.1
0.7
25
V
V
V
Trig in Open Circuit Voltage
Trig in Delta (VTH-VOC)
Trig in Input Resistance
Minimum Trig in Pulse Width*
Osc. Disable Threshold
One Shot Timer
dV TRIG = VOC to VTH
kΩ
ns
V
10
1.0
1.4
1.8
On Time*
150
2.8
35
200
3.7
70
250
4.6
ns
MHz
ns
Clamp Frequency*
Dead Time*
IVFO = 1.5mA
IVFO =1.5mA
100
Output Stage
Output Low Saturation
20mA
0.2
0.5
1.5
1.7
15
0.4
2.2
2.0
2.5
30
V
V
200mA
-20mA
Output High Saturation
V
-200mA
CLOAD = 1nF
20mA
V
Rise/Fall Time*
ns
V
UVLO Low Saturation
0.8
1.5
0.4
Output Mode Low Input
Output Mode High Input
Under Voltage Lockout Section
VCC Comparator Threshold
V
V
2.0
On
16
9.5
3.6
0.2
10
17.3
10.5
4.2
0.4
23
18.5
12
V
V
Off
UVLO Comparator Threshold
On
4.8
0.6
50
V
Hysteresis
V
UVLO Input Resistance
VREF Comparator Threshold
Supply Current
ICC
UVLO = 4/VCC = 8
VCC = UVLO = VREF
kΩ
V
4.5
4.9
VCC = 12V, VOSC DSBL = 3V
UVLO pin open
30
40
mA
mA
ISTART
0.3
0.5
VCC = VCC (on) -0.3V
Fault Comparator
Input Offset Voltage
−0.3 ≤ VCM ≤ 3V
VCM = 0V
2
10
200
30
mV
µA
µA
ns
Input Bias Current
100
10
Input Offset Current
VCM = 0V
Propagation Delay To Output*
Uncommitted Comparator
Input Offset Voltage
±50mV input
100
150
-0.3 ≤ VCM ≤ 3V
VCM = 0V
2
10
200
30
mV
µA
µA
V
Input Bias Current
100
10
Input Offset Current
VCM = 0V
Output Low Voltage
IO = 2mA
0.3
50
0.5
100
Propagation Delay To Sat*
Soft Start/Restart Control Section
Saturation Voltage (2 pins)
Charge Current (2 pins)
±50mV input, 2.5k load to 5V
ns
ISINK = 100µA
0.2
5
0.5
10
V
µA
V
2
Restart Delay Threshold
2.8
3.0
3.2
*Guaranteed by design but not 100% tested.
3
UC1860
UC2860
UC3860
ERROR AMPLIFIER
The error amplifier is a high gain, low offset, high bandwidth de-
sign with precise limits on its output swing. The bandwidth of the
amplifier is externally determined by the resistance seen at the
inverting input. Unity gain bandwidth is approximately:
Frequency (0dB) = 1/(2π * RIN (-) * CCOMP)
The input common mode range of the amplifier is from 2.8 to
4.5V. As long as one pin is within this range, the other can go as
low as zero.
The output swing with respect to the lVFO pin is limited from zero
to 2V. Note that pulling Sft Strt (soft start) low will lower the ref-
erence of the upper clamp. The lower clamp, however, will
dominate should the upper clamp reference drop below the
lower reference.
The VCC comparator is used for off-line applications by leaving
the UVLO pin open. In this application the supply current is
typically less than 0.3mA during start-up.
UNDER VOLTAGE LOCKOUT SECTION
The under voltage lockout consists of three comparators that
monitor VCC, UVLO and VREF. The VREF comparator makes
sure that the reference voltage is sufficiently high before op-
eration begins. When the UVLO comparator is low, the outputs
are driven low, the fault latch is reset, the soft start pin is dis-
charged, and the toggle flip-flop is loaded for output A.
The UVLO comparator is used for DC to DC applications or to
gate the chip on and off. To utilize its hysteretic threshold by an
external resistive divider, the internal impedance of the pin
must be accounted for. To run from a 5V external supply,
UVLO, VCC, and VREF are tied together.
ICC vs VCC
4
UC1860
UC2860
UC3860
VARIABLE FREQUENCY OSCILLATOR
Normally low trigger pulses are used to synchronize the
oscillator to a faster clock. Normally high trigger pulses
can also be used to synchronize to a slower clock.
The VFO block is controlled through 4 pins: CVFO, lVFO,
Osc Dsbl (oscillator disable), and Trig (trigger input). Os-
cillator frequency is approximately:
ONE SHOT TIMER
Frequency = IVFO/(CVFO 1V)
*
The one shot timer performs three functions and is pro-
grammed by the RC pin. The first function is to control
output driver pulse width. Secondly, it clocks the toggle
flip-flop. Thirdly, it establishes the maximum allowable fre-
quency for the VFO. One shot operation is initiated at the
beginning of each oscillator cycle. The RC pin, pro-
grammed by an external resistor and capacitor to ground,
is charged to approximately 4.3V and then allowed to dis-
charge. The lower threshold is approximately 80% of the
peak. On time is approximately:
With a fixed capacitor and low voltage applied to Trig and
Osc Dsbl, frequency is linearly modulated by varying the
current into the lVFO pin.
The Trig and Osc Dsbl inputs are used to modify VFO op-
eration. If Osc Dsbl is held high, the oscillator will com-
plete the current cycle but wait until Osc Dsbl is returned
low to initiate a new cycle. If a pulse is applied to Trig dur-
ing a cycle, the oscillator will immediately initiate a new
cycle. Osc Dsbl has priority over Trig, but if a trigger pulse
is received while Osc Dsbl is high, the VFO will remember
t(on) = 0.2 R C.
*
*
the trigger pulse and start a new cycle as soon as Osc After crossing the lower threshold, the resistor continues
Dsbl goes low.
to discharge the capacitor to approximately 3V, where it
waits for the next oscillator cycle.
VFO Frequency vs IVFO
Maximum Frequency vs R
On Time vs R
5
UC1860
UC2860
UC3860
FAULT MANAGEMENT SECTION
3.0V. As long as one of the inputs is within this range, the
other can be as high as 5V.
During UVLO, the fault management section is initialized.
The latch is reset, and both Sft Strt (soft start) and Rst Dly
(restart delay) are pulled low. When Sft Strt is low, it low-
ers the upper clamp of the error amplifier. As Sft Strt in-
creases in voltage, the upper clamp increases from a
value equal to the lower clamp until it is 2V more positive.
A capacitor to ground from the Sft Strt pin will control the
start rate.
The high speed fault comparator will work over the input
common mode range of -0.3 to 3.0V. When a fault is
sensed, the one shot is immediately terminated, Sft Strt is
pulled low, and Rst Dly is allowed to go high. Three
modes of fault disposition can easily be implemented. If
Rst Dly is externally held low, then a detected fault will
shut the chip down permanently. If the Rst Dly pin is left
open, a fault will simply cause an interruption of opera-
tion. If a capacitor is connected from Rst Dly to ground,
then hic-up operation is implemented. The hic-up time is:
UNCOMMITTED COMPARATOR
The uncommitted comparator, biased from the reference
voltage, operates independently from the rest of the chip.
The open collector output is capable of sinking 2mA. The
inputs are valid in the common mode range of -0.3 to
t (off) = 600 kohm C(Rst Dly).
*
Input Bias Current Input Voltage
6
UC1860
UC2860
UC3860
OPEN LOOP LABORATORY TEST FIXTURE
may be applied. When the switch is set to the resistive di-
vider, the chip will operate in consecutive mode (ie: A,B,
off,...)
The open loop laboratory test fixture is designed to allow
familiarization with the operating characteristics of the
UC3860. Note the pin numbers apply to the DlP.
S3 allows input of an external logic signal to disable the
oscillator.
To get started, preset all the options as follows:
S4 demonstrates the uncommitted comparator. When set
to output A, the comparator will accelerate the discharge
of pin 9, shortening the output pulse.
Adjust the error amplifier variable resistor pot (R1)
so the wiper is at a high potential.
Open the lVFO resistor switch (S1).
Throw the Trig switch (S2) to ground.
Throw the Osc Dsbl switch (S3) to ground.
S5 shorted to ground will disable the chip and the outputs
will be low. If the switch is open, the VCC start and stop
thresholds are 17 and 10V. Switched to the resistive di-
vider, the thresholds are approximately 12 and 10V.
Throw the uncommitted comparator switch (S4) to
ground.
S6 sets the mode of the toggle flip-flop. When grounded,
the outputs operate alternately. Switched to 5V, the out-
puts switch in unison. (Note: If S6 and S2 are set for uni-
son operation and triggered consecutive outputs, the chip
will free run at the maximum frequency determined by the
one shot.)
Throw the UVLO switch (S5) to the resistive divider.
Throw the Out Mode switch (S6) to ground.
Open the restart delay switch (S7).
Throw the fault switch (S8)to ground.
In this configuration, the chip will operate for Vcc greater
than 12V. Adjustment of the following controls allows ex-
amination of specific features.
S7 open allows the chip to restart immediately after a
fault sense has been removed. When grounded, it causes
the chip to latch off indefinitely. This state can be reset by
UVLO, VCC, or opening the switch. Connected to IµF pro-
grams a hic-up delay time of 600 ms.
R1 adjusts the output of the error amp. Notice the voltage
at pin 5 is limited from 0 to 2V above the voltage at pin 7.
S1 changes the error amp output to VFO gain. With S1
open, the maximum frequency is determined by the error
amp output. With S1 closed, the one shot will set the
maximum frequency.
S8 allows the simulation of a fault state. When flipped to
the RC network, the comparator monitors scaled average
voltage of output B. Adjusting frequency will cause the
comparator to sense a ’fault’ and the chip will enter fault
sequence.
S2 demonstrates the trigger. An external trigger signal
7
UC1860
UC2860
UC3860
OUTPUT STAGE
BYPASS NOTE
The two totem pole output stages can be programmed by
Mode to operate alternately or in unison. When Mode is
low the outputs alternate. During UVLO, the outputs are
low.
The reference should be bypassed with a 0.1µF ceramic
capacitor from the VREF pin directly to the ground plane
near the Signal Ground pin. The timing capacitors on
CVFO and RC should be treated likewise. VCC, however,
should be bypassed with a ceramic capacitor from the
VCC pin to the section of ground plane that is connected
to Power Ground. Any required bulk reservoir capacitor
should parallel this one. The two ground plane sections
can then be joined at a single point to optimize noise re-
jection and minimize DC drops.
Extreme care needs to be exercised in the application of
these outputs. Each output can source and sink transient
currents of 2A or more and is designed for high values of
dl/dt. This dictates the use of a ground plane, shielded in-
terconnect cables, Schottky diode clamps from the output
pins to Pwr Gnd (power ground), and some series resis-
tance to provide damping. Pwr Gnd should not exceed
±0.2V from signal ground.
Output Saturation Voltage vs Load Current
Output Rise & Fall Time vs Load Capacitance
Output Saturation Voltage vs Load Current
UNITRODE INTEGRATED CIRCUITS
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8
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