UC1907DW [TI]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, 0.150 INCH, PLASTIC, SOIC-16;
| 型号： | UC1907DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, 0.150 INCH, PLASTIC, SOIC-16 光电二极管 |
| 文件： | 总12页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
FEATURES
SOIC-16 DW PACKAGE
(TOP VIEW)
D
D
Fully Differential High Impedance Voltage
Sensing
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C/S OUT
C/S (+)
C/S (–)
STATUS INDICATE
CURRENT SHARE BUS
ADJ OUT
ADJ INPUT
COMP
(+) SENSE
VCC
OPTO DRIVE
Accurate Current Amplifier for Precise
Current Sharing
(–) SENSE
D
D
D
D
Opto Coupler Driving Capability
POWER RETURN
ARTIFICIAL GND
VREF
1.25% Trimmed Reference
Master Status Indication
4.5-V to 35-V Operation
ISET
PLCC-20, LCC-20,
Q OR L PACKAGE
(TOP VIEW)
DIL-16 J or N PACKAGE
(TOP VIEW)
3
2
1
20 19
C/S OUT
C/S (+)
C/S (–)
STATUS INDICATE
CURRENT SHARE BUS
ADJ OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
C/S (–)
(–) SENSE
4
5
6
7
8
18
17
16
15
14
ADJ OUT
ADJ INPUT
N/C
N/C
(–) SENSE
POWER RETURN
ARTIFICIAL GND
VREF
ADJ INPUT
COMP
POWER RETURN
ARTIFICIAL GND
COMP
(+) SENSE
(+) SENSE
10 VCC
OPTO DRIVE
9
10 11 12 13
ISET
9
DESCRIPTION
The UCx907 family of load share controller ICs provides all the necessary features to allow
multiple-independent-power modules to be paralleled such that each module supplies only its proportionate share
to total-load current.
This sharing is accomplished by controlling each module’s power stage with a command generated from a
voltage-feedback amplifier whose reference can be independently adjusted in response to a common-share-bus
voltage. By monitoring the current from each module, the current share bus circuitry determines which paralleled
module would normally have the highest output current and, with the designation of this unit as the master, adjusts
all the other modules to increase their output current to within 2.5% of that of the master.
The current share bus signal interconnecting all the paralleled modules is a low-impedance, noise-insensitive line
which will not interfere with allowing each module to act independently should the bus become open or shorted to
ground. The UC3907 controller will reside on the output side of each power module and its overall function is to supply
a voltage feedback loop. The specific architecture of the power stage is unimportant. Either switching or linear designs
may be utilized and the control signal may be either directly coupled or isolated though the use of an optocoupler or
other isolated medium.
Other features of the UC3907 include 1.25% accurate reference: a low-loss, fixed-gain current-sense amplifier, a fully
differential, high-impedance voltage sensing capability, and a status indicator to designate which module is
performing as master.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2000, Texas Instruments Incorporated
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1
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ꢓ
SLUS165C – MARCH 1999 - REVISED JANUARY 2002
block diagram
VOLTAGE ERROR AMPLIFIER
(+) SENSE
11
10
–
12 COMP
V
+
CC
VCC (4.5 V TO 35 V)
1.75 V
DRIVE
0.25 V
9
1.0 V
OPTO DRIVE
AMPLIFIER
+
DRV
–
GROUND
V
REF
1.75 V
AMPLIFIER
Ω
1 k
–
Ω
50 k
20 k
Ω
GND
+
(–) SENSE
POWER RTN
ARTIFICIAL GND
VREF
4
5
6
7
1
8
ISET
14 ADJ OUT
ADJUST
50 mV
AMPLIFIER
13 ADJ INPUT
–
ADJ
17.5 kΩ
+
C/S OUT
Ω
40 k
BUFFER
AMPLIFIER
CURRENT SENSE
AMPLIFIER
Ω
Ω
2 k
2 k
–
C/S (–)
3
2
100
15 CURRENT SHARE BUS
16 STATUS INDICATE
–
+
+
Ω
10 k
C/S (+)
Ω
40 k
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Opto out voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Opto out current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Status indicate sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
C/S input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V
Share bus voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 35 V
Other analog inputs and outputs (zener clamped) maximum forced voltage . . . . . . . . . . . . . . . . –0.3 V to10 V
Other analog inputs and outputs (zener clamped) maximum forced current . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ground amp sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Pins 1, 9, 12, 15 sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
J
Lead temperature (solder 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
‡
Pin Nos. refer to 16 Pin DIL Package.
Currents are positive into, negative out of the specified terminal. Consult packaging section of databook for thermal limitations and considerations
of package.
2
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
electrical characteristics, these specifications apply for T = –55°C to 125°C for UC1907, –40°C to
A
85°C for UC2907, and 0°C to 70°C for UC3907, V = 15 V, T = T (unless otherwise stated )
IN
A
J
PARAMETER
Voltage Amp Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
COMP = 1 V,
COMP = 1 V,
T
= 25°C
1.975
1.960
2.000
2.000
2.025
2.040
15
V
A
Input voltage
over temp
V
Line regulation
V
= 4.5 V to 35 V
mV
mV
mV
IN
reference = 0.0 mA to –10 mA
Load regulation
I
L
10
Long term stability
Total output variation
Input adjust range
Input bias current
Open loop gain
T
A
= 125°C,
1000hrs See Note 2
5
25
Line, load, temp
1.960
85
2.040
115
ADJ OUT from max high to max low
100
mV
µA
dB
kHz
mA
µA
V
–1
COMP = 0.75 V to 1.5 V
65
Unity gain bandwidth
Output sink current
Output source current
T
A
= 25°C
See Note 2
700
6
(+) SENSE = 2.2 V,
(+) SENSE = 1.8 V,
(+) SENSE = 1.8 V,
(+) SENSE = 2.2 V,
COMP = 1 V
COMP = 1 V
15
600
2
400
1.85
V
V
high
low
I
I
= –400 µΑ
OUT
L
= 1 mA
0.15
0.40
V
OUT
L
Reference Section
T
= 25°C
1.970
1.955
–15
2.000
2.000
–30
2.030
2.045
–60
V
V
A
Output voltage
Over operating temp
VREF = 0.0 V
Short circuit current
Ground Amp Section
Output voltage
mA
200
250
300
5
mV
mV
mV
mV
Common mode variation
(–) SENSE from 0.0 V to 2 V
I
I
= 0.0 mA to 20 mA,
= 0.0 mA to 20 mA,
T
= 25°C
10
15
L
A
Load regulation
over temp
L
Adjust Amp Section
Input offset voltage
Input bias current
ADJ OUT = 1.5 V, V
CM
= 0.0 V
40
–2
65
50
60
mV
µA
dB
Hz
ms
µA
µA
V
Open loop gain
1.5 V ≤ ADJ OUT ≤ 2.25 V
= 25°C,
Unity gain bandwidth
Transconductance
Output sink current
Output source current
T
A
C
=1 µF
OUT
See Note 2
500
3
I
= –10 µA to 10 µA,
= 0.0 V,
V
= 1.5 V
1.7
55
4.5
225
350
2.90
1.15
OUT
OUT
V
V
V
V
V
V
ADJ OUT = 1.5 V
ADJ OUT = 1.5 V
135
200
2.70
0.75
ID
= 250 mV,
110
2.20
ID
V
high
low
= 250 mV,
I
= – 50 mA
OUT
OUT
ID
OUT
OUT
V
= 0.0 V,
I
= 50 mA
V
ID
Common mode rejection ratio
= 0.0 to 10 V
70
50
dB
CM
ADJ OUT = 1.5 V to 2 V,
OUT
Output gain to V/A
57
64 mV/V
∆(+) SENSE/ ∆ADJ OUT
NOTE 1: Unless otherwise specified all voltages are with respect to (–) SENSE. Currents are positive into, negative out of the specified terminal.
NOTE 2: Ensured by design. Not production tested.
3
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
electrical characteristics, these specifications apply for T = –55°C to 125°C for UC1907, –40°C to
A
85°C for UC2907, and 0°C to 70°C for UC3907, V = 15 V, T = T (unless otherwise stated )
IN
A
J
PARAMETER
Current Amp Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Gain
V
CM
V
C/S
V
C/S
V
CM
= 0.0 V,
V
= 50 mV to 100 mV
19.2
210
180
19.6
250
250
20.1
290
330
V/V
mV
mV
ID
T = 25°C
A
(+) = V
(+) = V
(–) = 0.0 V,
C/S
Output voltage
(–) = 0.0 V, over temp
C/S
Input offset change with common mode
input
= 0 V to 13 V
600 µV/V
V
V
high
low
V
ID
V
ID
V
IN
= 1 V
10
60
14.5
350
V
OUT
= – 1 V,
I
= 1 mA
450
mV
dB
OUT
L
Power supply rejection ratio
Slew rate
= 4.5 V to 35 V,
V
= 0.0 V
CM
0.4
V/µs
Drive Amp Section R
= 500 Ω to Artificial GND, Opto Drive = 15 V
COMP = 0.5 V to 1 V
SET
Voltage gain
2.3
3.8
2.5
4.1
2.6
4.4
V/V
V
I
I
V
high
low
(+) SENSE = 2.2 V
SET OUT
V
(+) SENSE = 1.8 V
270
300
35
mV
V
SET OUT
Opto out voltage range
Zero current input threshold
Buffer Amp Section
Input offset voltage
4
1.55
1.65
1.75
V
Input = 1 V
Input = 1 V,
Input = 1 V,
5
mV
kΩ
mA
dB
dB
Output off impedance
Output source current
output = 1.5 V to 2 V
output = 0.5 V
5
6
10
15
20
Common mode rejection ratio
Power supply rejection ratio
Under Voltage Lockout Section
Startup threshold
V
= 0.3 V to 10 V
70
70
CM
= 4.5 V to 35 V
V
IN
3.7
4.4
V
Threshold hysteresis
200
mV
Status Indicate Section
V
low
ADJ OUT = current share bus
ADJ OUT = 1 V,
0.2
0.1
0.5
5
V
OUT
Output leakage
V
OUT
= 35 V
µA
Total Stand by Current Section
Startup current
V
V
= UVLO – 0.2 V
3
6
5
mA
mA
IN
Operating current
= 35 V
10
IN
NOTE 1: Unless otherwise specified all voltages are with respect to (–) SENSE. Currents are positive into, negative out of the specified terminal.
NOTE 2: Ensured by design. Not production tested.
4
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
pin assignments
(–) SENSE: (Pin 4) This is a high-impedance pin allowing remote sensing of the system ground, bypassing any
voltage drops which might appear in the power return line. This point should be considered as the true ground. Unless
otherwise stated, all voltages are with respect to this point.
Artificial Ground: (Pin 6) This is a low-impedance-circuit ground which is exactly 250 mV above the (–) SENSE
terminal. This offset allows the ground buffer amplifier negative headroom to return all the control bias and operating
currents while maintaining a high impedance at the (–) SENSE input.
Power RTN: (Pin 5) This should be the most negative voltage available and can range from zero to 5 V below the
(–) SENSE terminal. It should be connected as close to the power source as possible so that voltage drops across
the return line and current-sensing impedances lie between this terminal and the (–) SENSE point.
VREF: (Pin 7) The internal voltage reference is a band-gap circuit set at 2.0 V with respect to the (–) SENSE input
(1.75 V above the artificial ground), and an accuracy of ±1.5%. This circuit, as well as all the other chip functions, will
work over a supply voltage range of 4.5 V to 35 V allowing operation from unregulated dc, an auxiliary voltage, or
the same output voltage that it is controlling. Under-voltage lockout has been included to insure proper startup by
disabling internal bias currents until the reference rises into regulation.
Voltage Amplifier: (Pins 11, 12) This circuit is the feedback-control-gain stage for the power module’s output-voltage
regulation, and overall-loop compensation will normally be applied around this amplifier. Its output will swing from
slightly above the ground return to an internal clamp of 2.0 V. The reference trimming is performed closed loop, and
measured at pin 11, (+) SENSE. The value is trimmed to 2 V ±1.25%.
Drive Amplifier: (Pins 8, 9, 12) This amplifier is used as an inverting buffer between the voltage amplifier’s output
and the medium used to couple the feedback signal to the power controller. It has a fixed-voltage gain of 2.5 and is
usually configured with a current-setting resistor to ground. This establishes a current-sinking output optimized to
drive optical couplers biased at any voltage from 4.5 V to 35 V, with current levels up to 20 mA. The polarity of this
stage is such that an increasing voltage at the voltage amplifier’s sense input (as, for example, at turnon) will increase
the opto’s current. In a nonisolated application, a voltage signal ranging from 0.25 V to 4.1 V may be taken from the
current-setting output but it should be noted that this voltage will also increase with increasing sense voltage and an
external inverter may be required to obtain the correct feedback polarity.
Current Amplifier: (Pins 1, 2, 3) This amplifier has differential-sensing capability for use with an external shunt in
the power-return line. The common mode range of its input will accommodate the full range between the power return
point and VCC-2 V which will allow undefined-line impedances on either side of the current shunt. The gain is
internally set at 20, giving the user the ability to establish the maximum-voltage drop across the current-sense resistor
at any value between 50 mV and 500 mV. While the bandwidth of this amplifier may be reduced with the addition of
an external-output capacitor to ground, in most cases this is not required as the compensation of the adjust amplifier
will typically form the dominant pole in the adjust loop.
Buffer Amplifier: (Pins 1, 15) This amplifier is a unidirectional buffer which drives the current-share bus. The line
which will interconnect all power modules paralleled for current sharing. Since the buffer amplifier will only source
current, it insures that the module with the highest-output current will be the master and drive the bus with a
low-impedance drive capability. All other buffer amplifiers will be inactive with each exhibiting a 10-kΩ load impedance
to ground. The share bus terminal is protected against both shorts to ground and accidental voltages in excess of
50 V.
5
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SLUS165C – MARCH 1999 - REVISED JANUARY 2002
pin assignments
Adjust Amplifier: (Pins 13, 14, 15) This amplifier adjusts the individual module’s reference voltage to maintain
equal-current sharing. It is a transconductance type in order that its bandwidth may be limited and noise kept out of
the reference-adjust circuitry, with a simple capacitor to ground. The function of this amplifier is to compare its own
module-output current to the share-bus signal, which represents the highest output current. This will force an adjust
command which is capable of increasing the reference voltage as seen by the voltage amplifier by as much as 100
mV. This number stems from the 17.5:1 internal resistor ratio between the adjust amplifier’s clamped output and the
reference, and represents a 5% total range of adjustment. This value should be adequate to compensate for
unit-to-unit reference and external-resistor tolerances. The adjust amplifier has a built-in 50-mV offset on its inverting
input which will force the unit acting as the master to have a low output, resulting in no change to the reference. While
this 50-mV offset represents an error in current sharing, the gain of the current amplifier reduces it to only 2.5 mV
across the current-sense resistor. It should also be noted that when the module is acting independently with no
connection to the share bus node, or when the share bus node is shorted to ground, its reference voltage will be
unchanged. Since only the circuit acting as a master will have a low output from the adjust amplifier, this signal is used
to activate a flag output to identify the master, should some corrective action be needed.
Status Indicate: (Pin 16) This pin is an open-collector output intended to indicate the unit which is acting as the
master. It achieves this by sensing when the adjust amp is in its low state and pulling the status-indicate pin low.
additional information
Please refer to additional application information.
1. By Mark Jordan, UC3907 Load Share IC Simplifies Parallel Power Supply Design, TI Literature Number
SLUA147.
2. By Laszlo Balogh, UC3902 Load Share Controller and its Performance in Distributed Power Systems, TI
Literature Number SLUA128.
UDG-94103
Figure 1. Load System Diagram
6
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ꢉ ꢊꢋ ꢌ ꢍꢎ ꢋꢏꢐ ꢁꢊ ꢑ ꢒꢏ ꢊꢉ ꢉꢐ ꢏ
ꢓ
SLUS165C – MARCH 1999 - REVISED JANUARY 2002
additional information (continued)
V
CC
0–20 mA
ISOLATED
UC3907
CONTROL
DRIVE
AMPLIFIER
+
12
1.0 V
9
I
0–4 V
DIRECT
CONTROL
VOLTAGE ERROR
AMPLIFIER
SET
(+) SENSE
–
Ω
Ω
50 k
20 k
11
–
8
V
RANGE 2.0 V–2.1 V
REF
+
MASTER
INDICATE
REF
1.75 V
V
CC
7
16
V
CC
1.750 V
REF
10
0.250 V
GND
ADJUST AMPLIFIER
+
–
BUFFER
AMPLIFIER
AMPLIFIER
50 mV
+
CURRENT
SHARE
BUS
–
–
(
) SENSE
15
+
20X
–
4
6
+
+
Ω
10 k
ARTIFICIAL GND
2
3
14
1
13
5
C/S OUT ADJ IN
PWR RET
CURRENT
SENSE
ADJ
COMP
+
TO PWR
RETURN
FROM LOAD
MODULE LOAD CURRENT
UDG-99053
Figure 2. Load System Connection Diagram
UDG-94105
Figure 3. UC3907 In a Load-Sharing Feedback Loop for an Off-Line Isolated Supply
7
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
LCCC
LCCC
SOIC
Drawing
UC1907J
UC1907J883B
UC1907L
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
J
J
16
16
20
20
16
TBD
TBD
TBD
TBD
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FK
FK
DW
UC1907L883B
UC2907DW
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2907DWG4
UC2907DWTR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2907DWTRG4
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2907J
UC2907N
OBSOLETE
ACTIVE
CDIP
PDIP
J
16
16
TBD
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N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UC2907NG4
UC3907DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
N
16
16
16
16
16
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
DW
DW
DW
DW
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3907DWG4
UC3907DWTR
UC3907DWTRG4
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3907J
UC3907N
OBSOLETE
ACTIVE
CDIP
PDIP
J
16
16
TBD
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N
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UC3907NG4
ACTIVE
PDIP
N
16
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
UC2907DWTR
UC3907DWTR
SOIC
SOIC
DW
DW
16
16
2000
2000
330.0
330.0
16.4
16.4
10.85
10.85
10.8
10.8
2.7
2.7
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC2907DWTR
UC3907DWTR
SOIC
SOIC
DW
DW
16
16
2000
2000
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
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