UC1910_08 [TI]
4-Bit DAC and Voltage Monitor;
| 型号： | UC1910_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-Bit DAC and Voltage Monitor |
| 文件： | 总6页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1910
UC2910
UC3910
4-Bit DAC and Voltage Monitor
FEATURES
DESCRIPTION
•
Precision 5V Reference
The UC3910 is a complete precision reference and voltage monitor cir-
cuit for Intel Pentium® Pro and other high-end microprocessor power
supplies. It is designed for use in conjunction with the UC3886 PWM. The
UC3910 together with the UC3886 converts 5VDC to an adjustable out-
put ranging from 2.0VDC to 3.5VDC in 100mV steps with 1% DC system
accuracy.
•
4-Bit Digital-to-Analog (DAC)
Converter
•
•
•
0.5% DAC/Reference Combined
Error
Programmable Undervoltage and
Overvoltage Fault Windows
The UC3910 utilizes thin film resistors to ensure high accuracy and sta-
bility of its precision circuits. The chip includes a precision 5V voltage ref-
erence which is capable of sourcing 10mA to external circuitry. The
output voltage of the DAC is derived from this reference, and the accu-
racy of the DAC/reference combination is 0.5%. Programmable window
comparators monitor the supply voltage to indicate that it is within ac-
ceptable limits. The window is programmed as a percentage centered
around the DAC output. An overvoltage protection comparator is set at a
percentage 2 times larger than the programmed lower overvoltage level
and drives an external SCR as well as provides an open collector output.
Undervoltage lockout protection assures the correct logic states at the
outputs during power-up and power-down.
Overvoltage Comparator with
Complementary SCR Driver and
Open Collector Outputs
•
Undervoltage Lockout
BLOCK DIAGRAM
UDG-95097-3
3/97
UC1910
UC2910
UC3910
CONNECTION DIAGRAM
DIL-16, SOIC-16 (Top View)
J, N, or D Packages
ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 12V, VSENSE = 3.5V, VOVTH/UVTH = 1.26V,
VD0 = VD1 = VD2 = VD3 = 0V, 0°C < TA < 70°C for the UC3910, –25°C < TA < 80°C for the UC2910, –55°C < TA < 125°C for the
UC1910 TA = TJ.
PARAMETER
Undervoltage Lockout
TEST CONDITIONS
MIN
TYP
MAX UNITS
VIN UVLO Turn-on Threshold
UVLO Threshold Hysteresis
Supply Current
7
8
9
V
50
200
500
mV
IIN Startup
VCC = 5V
2
3.5
12
mA
mA
IIN
VCC = 12V
10
DAC/Reference
DACOUT Voltage Accuracy
Line, Load, 0°C < TA < 70°C (Note 1)
Line, Load, –55°C < TA < 125°C
DX Pin Floating
−0.9
–1.5
4.6
0.9
1.5
%
%
V
D0-D3 Voltage High
D0-D3 Input Bias Current
VREF Output Voltage
VREF Total Variation
4.85
DX Pin Tied to GND
–140 −105
µA
V
IVREF = 0mA, 0°C < TA < 70°C
Line, Load, 0°C < TA < 70°C (Note 1)
Line, Load, –55°C < TA < 125°C
VREF = 0V
4.97
4.96
4.925
10
5
5
5
5.03
5.04
V
5.075
V
VREF Sourcing Current
DAC Buffer
mA
Input Offset Voltage
IDACBUF = –1mA, 0°C < TA < 70°C
−25
25
–1
mV
mA
Output Sourcing Current
Monitor Circuitry (Note 2)
VSENSE UV Threshold Voltage
–12
Code 0, Ratio = 0.45 (Note 3)
Code 0, Ratio = 0.9
3.174 3.237
3.3
V
V
V
V
V
V
V
V
2.87 2.975 3.08
1.816 1.85 1.884
Code 15, Ratio = 0.45
Code 15, Ratio = 0.9
Code 0, Ratio = 0.45
Code 0, Ratio = 0.9
1.635
3.7
1.7
1.765
VSENSE OV Threshold Voltage
3.763 3.826
3.92 4.025 4.13
2.116 2.15 2.184
Code 15, Ratio = 0.45
Code 15, Ratio = 0.9
1.635
2.3
2.365
2
UC1910
UC2910
UC3910
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise specified, VCC = 12V, VSENSE = 3.5V, VOVTH/UVTH =
1.26V, VD0 = VD1 = VD2 = VD3 = 0V, 0°C < TA < 70°C for the UC3910, –25°C < TA < 80°C for the UC2910, –55°C < TA < 125°C for
the UC1910 TA = TJ.
PARAMETER
Monitor Circuitry (Note 2) (cont.)
VSENSE OVP Threshold Voltage
TEST CONDITIONS
MIN
TYP
MAX UNITS
Code 0, Ratio = 0.45
3.937 4.025 4.113
V
V
Code 0, Ratio = 0.9
Code 15, Ratio = 0.45
Code 15, Ratio = 0.9
Code 0, Ratio = 0.9
Code 15, Ratio = 0.45
Code 0, Ratio = 0.9
Code 15, Ratio = 0.45
OV, UV, OVP Comparators
OV, UV Comparators
OVP Comparator
4.41
2.235
2.505
70
4.55
2.3
2.6
88
4.69
2.365
2.695
120
40
V
V
OV, UV Comparator Hysteresis
OVP Comparator Hysteresis
mV
mV
mV
mV
V
15
25
160
40
218
62
300
85
Input Common Mode Range
Propagation Delay
0
5
5
µs
µs
5
PWRGOOD, OVP, OVPB Outputs
PWRGOOD Voltage Low
OVP Sourcing Current
IPWRGOOD = 10mA
VOVP = 1.4V
0.4
0.4
V
mA
V
65
OVPB Voltage Low
IOVPB = 1mA
Note 1: "Line, Load" implies that the parameter is tested at all combinations of the conditions:
10.8V < VCC < 13.2V, –2mA < IVREF < 0mA.
Note 2: These are the actual voltages on VSENSE which will cause the OVPB and PWRGOOD outputs to switch, assuming the
DACOUT voltage is perfect. These limits apply for 0°C < TA < 70°C.
Note 3: "Code 0" means pins D0 - D4 are all low; "Code 15" means they are all floating or high (See Table 1). "Ratio" is the divider
ratio of the resistor string between DACBUF and OVTH/UVTH (See Figure 1).
PIN DESCRIPTIONS
Decimal
Code
D3
D2
D1
D0
DACOUT
Voltage
D0-D3 (DAC Digital Input Control Codes): These are
the DAC digital input control codes, with D0 repre-
senting the least significant bit (LSB) and D3, the most
significant bit (MSB) (See Table 1). A bit is set low by
being connected to GND; a bit is set high by floating it,
or connecting it to a 3V to 5V voltage source. Each con-
trol pin is pulled up to approximately 4.8V by an internal
40µA current source.
15
14
13
12
11
10
9
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
DACBUF (Buffered DACOUT Voltage): This pin pro-
vides a buffered version of the DACOUT voltage to al-
low external programming of the OV/UV thresholds (see
OVTH/UVTH below).
8
7
6
5
4
DACOUT (Digital-to-Analog Converter Output Volt-
age): This pin is the output of the 4-bit digital to analog
(DAC) converter. Setting all input control codes low pro-
duces 3.5V at DACOUT; setting all codes high pro-
duces 2.0V at DACOUT. The LSB step size (i.e.
resolution) is 100mV (See Table 1). The DACOUT
source impedance is typically 3kΩ and must therefore
drive a high impedance input. Bypass DACOUT at the
driven input with a 0.01µF, low ESR, low ESL capacitor
for best circuit noise immunity.
3
2
1
0
Table 1. Programming the DACOUT Voltage
respect to GND. The two GND pins are connected to-
gether internally but should also be connected exter-
nally using a short PC board trace. Bypass capacitors
on the VCC and VREF pins should be connected di-
rectly to the ground plane near one of the signal ground
GND (Signal Ground): All voltages are measured with
3
UC1910
UC2910
UC3910
PIN DESCRIPTIONS (cont.)
pins.
put): This pin is an open collector output which is
driven low to reset the microprocessor when VSENSE
rises above or falls below its nominal value by a per-
centage programmed by OVTH/UVTH. The OV and UV
comparators’ hysteresis is a function of the DACBUF
voltage and the OV/UV programmed percentage.
OVP (Overvoltage Comparator Output): This output
pin drives an external SCR circuit with up to 65mA
when the voltage on VSENSE rises above its nominal
value by a percentage set by the voltage on the
OVTH/UVTH pin (see below). The OVP comparator hys-
teresis is a function of both the DACBUF voltage and
the OV/UV percentage programmed.
VCC (Positive Supply Voltage): This pin supplies
power to the chip. Connect VCC to a stable voltage
source of at least 9V and capable of sourcing at least
15mA. The OVP and PWRGOOD outputs are held low,
the OVPB output is in a high impedance state, and the
VSENSE pin is pulled low until VCC exceeds the upper
undervoltage lockout threshold. This pin should be by-
passed directly to the GND pin with a 0.1µF low ESR,
low ESL capacitor.
OVPB (Overvoltage Comparator Complementary
Output): This output is a complement to the OVP out-
put (see above) and provides an open collector capable
of sinking 1mA when the voltage on VSENSE rises
above its nominal value by a percentage set by the volt-
age on the OVTH/UVTH pin (see below).
OVTH/UVTH (Undervoltage and Lower Overvoltage
Threshold Input): This pin is used to program the win-
dow thresholds for the OV and UV comparators. The
OV-UV window is centered around the DACBUF voltage
VREF (Voltage Reference Output): This pin provides
an accurate 5V reference, capable of delivering up to
10mA to external circuitry, and is internally short circuit
current limited. For best reference stability, bypass
VREF directly to the GND pin with a 0.1µF, low ESR,
low ESL capacitor.
±
±
and can be programmed from 5% to 15% about
DACBUF. Connect a resistor divider between DACBUF
and GND to set the percentage. The threshold for the
OVP comparator is internally set to a percentage 2
times larger than the programmed OV percentage;
therefore, its range extends from 10% to 30% above
DACBUF.
VSENSE (Output Voltage Sensing Input): This pin is
the input to the OVP and PWRGOOD comparators and
is connected to the system output voltage through a
lowpass filter. When choosing the resistor value for this
filter, make sure that no more than 500µA will flow
PWRGOOD (Undervoltage/Lower Overvoltage Out-
APPLICATION INFORMATION
The Overvoltage (OV), Undervoltage (UV) and Overvol-
tage Protection Voltage (OVP) threshold detection volt-
ages are programmed as a percentage about the
nominal DAC output voltage, DACOUT. Figure 1 illus-
trates how to program the UC3910 by setting a voltage
divider, RDIV, at the OVTH/UVTH pin. The voltage di-
vider ratio is defined as
RS1
RDIV =
RS1 + RS2
The UC3910 allows a ratio RDIV at the OVTH/UVTH pin
from 0.3 to 0.9, which corresponds to overvoltage and
undervoltage percentage thresholds from 5% to 15%
and an OVP percentage threshold from 10% to 30%.
These thresholds are shown in Figure 2.
The OV, UV and OVP percentage thresholds are given
by
%VOV = RDIV • 16.7
%VUV = –(RDIV • 16.7)
%VOVP = %VOV • 2.0 = RDIV • 33.4
UDG-96020
An R-C filter is added to the VSENSE pin to filter noise
and ripple at the comparator inputs. An R-C filter fre-
quency of FSWITCH/10 is recommended. Choose the
Figure 1. Setting the OV/UV/OVP Threshold
Percentages
4
UC1910
UC2910
UC3910
APPLICATION INFORMATION (cont.)
30
25
20
OVP
15
OV
10
5
0
-5
UV
-10
-15
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Ratio RDIV
UDG-96019
Figure 3. Driving and SCR Using the UC3910 OVP
Figure 2. OV, UV and OVP Percentage Thresholds as a
Function of the Divider Ratio RDIV
Signal
value of RF such that it limits the current into VSENSE
The Overvoltage Protection output, OVP, can be used
to directly drive a crowbarring SCR, as shown in Figure
3.
to ≤ 0.5mA.
1
RF • CF =
FSWITCH
A typical application is shown in Figure 4 using the
UC3910 together with the UC3886 Average Current
Mode PWM Controller IC for a power supply to drive In-
tel’s Pentium®Pro processor.
2 • π •
10
VOUT
RF ≥
0.5mA
UDG-96021
Figure 4. UC3910 Configured with the UC3886 for a Pentium® Pro DC/DC Converter
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
5
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