UC2525AJ [TI]
Regulating Pulse Width Modulators; 调节脉冲宽度调制器
| 型号： | UC2525AJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Regulating Pulse Width Modulators |
| 文件： | 总9页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1525A/27A
UC2525A/27A
UC3525A/27A
Regulating Pulse Width Modulators
FEATURES
DESCRIPTION
• 8 to 35V Operation
The UC1525A/1527A series of pulse width modulator integrated circuits are de-
signed to offer improved performance and lowered external parts count when
used in designing all types of switching power supplies. The on-chip +5.1V ref-
erence is trimmed to ±1% and the input common-mode range of the error ampli-
fier includes the reference voltage, eliminating external resistors. A sync input to
the oscillator allows multiple units to be slaved or a single unit to be synchro-
nized to an external system clock. A single resistor between the CT and the dis-
charge terminals provides a wide range of dead-time adjustment. These
devices also feature built-in soft-start circuitry with only an external timing ca-
pacitor required. A shutdown terminal controls both the soft-start circuitry and
the output stages, providing instantaneous turn off through the PWM latch with
pulsed shutdown, as well as soft-start recycle with longer shutdown commands.
These functions are also controlled by an undervoltage lockout which keeps the
outputs off and the soft-start capacitor discharged for sub-normal input volt-
ages. This lockout circuitry includes approximately 500mV of hysteresis for jit-
ter-free operation. Another feature of these PWM circuits is a latch following the
comparator. Once a PWM pulse has been terminated for any reason, the out-
puts will remain off for the duration of the period. The latch is reset with each
clock pulse. The output stages are totem-pole designs capable of sourcing or
sinking in excess of 200mA. The UC1525A output stage features NOR logic,
giving a LOW output for an OFF state. The UC1527A utilizes OR logic which
results in a HIGH output level when OFF.
• 5.1V Reference Trimmed to ±1%
• 100Hz to 500kHz Oscillator Range
• Separate Oscillator Sync Terminal
• Adjustable Deadtime Control
• Internal Soft-Start
• Pulse-by-Pulse Shutdown
• Input Undervoltage Lockout with
Hysteresis
• Latching PWM to Prevent Multiple
Pulses
• Dual Source/Sink Output Drivers
BLOCK DIAGRAM
OSC
OUT
VREF
16
4
13
11
VC
NOR
UVLO
Lockout
Reference
Regulator
+VIN 15
OUTPUT A
GROUND 12
To internal
circuitry
SYNC
RT
3
6
5
7
Flip
Flop
NOR
OSC
CT
14
OUTPUT B
DISCHARGE
UC1525A Output Stage
13
11
VC
COMP
R
S
S
OR
COMPENSATION
INV INPUT
9
1
2
8
PWM
La tch
Error
Amp
VREF
50 µA
OUTPUT A
NI INPUT
SOFTSTART
OR
3 kΩ
SHUTDOWN 10
14
OUTPUT B
5 kΩ
UC1527A Output Stage
SLUS191B - February 1997 - Revised June 2005
UC1525A/27A
UC2525A/27A
UC3525A/27A
ABSOLUTE MAXIMUM RATINGS(Note 1)
RECOMMENDED OPERATING CONDITIONS
(Note 3)
Supply Voltage, (+VIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V
Collector Supply Voltage (VC) . . . . . . . . . . . . . . . . . . . . . . +40V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +5.5V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +VIN
Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA
Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Power Dissipation at TA = +25°C (Note 2). . . . . . . . . . 1000mW
Power Dissipation at TC = +25°C (Note 2) . . . . . . . . . 2000mW
Operating Junction Temperature . . . . . . . . . . –55°C to +150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . +300°C
Note 1: Values beyond which damage may occur.
Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V
Collector Supply Voltage (VC). . . . . . . . . . . . . . . +4.5V to +35V
Sink/Source Load Current (steady state) . . . . . . . . 0 to 100mA
Sink/Source Load Current (peak) . . . . . . . . . . . . . . 0 to 400mA
Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillator Frequency Range. . . . . . . . . . . . . . 100Hz to 400kHz
Oscillator Timing Resistor . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ
Oscillator Timing Capacitor . . . . . . . . . . . . . . . .001µF to .01µF
Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . . 0 to 500Ω
Operating Ambient Temperature Range
UC1525A, UC1527A . . . . . . . . . . . . . . . . . . –55°C to +125°C
UC2525A, UC2527A . . . . . . . . . . . . . . . . . . . –25°C to +85°C
UC3525A, UC3527A . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Note 3: Range over which the device is functional and parame-
ter limits are guaranteed.
Note 2: Consult packaging Section of Databook for thermal
limitations and considerations of package.
CONNECTION DIAGRAMS
DIL-16 (TOP VIEW)
J or N Package
PLCC-20, LCC-20 (TOP VIEW)
Q, L Package
PACKAGE PIN FUNCTION
FUNCTION
N/C
PIN
1
Inv. Input
N.I. Input
SYNC
2
3
4
OSC. output
N/C
5
6
CT
7
RT
8
Discharge
Softstart
N/C
Compensation
Shutdown
Output A
Ground
N/C
9
10
11
12
13
14
15
16
17
18
19
20
VC
Output B
+VIN
VREF
2
UC1525A/27A
UC2525A/27A
UC3525A/27A
ELECTRICAL CHARACTERISTICS:+VIN = 20V, and over operating temperature, unless otherwise specified, TA = TJ.
UC1525A/UC2525A
UC1527A/UC2527A
UC3525A
UC3527A
UNITS
PARAMETER
Reference Section
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
Output Voltage
TJ = 25°C
IN = 8 to 35V
5.05
5.10
10
5.15
20
5.00
5.10
10
5.20
20
V
Line Regulation
V
mV
mV
Load Regulation
IL = 0 to 20mA
20
50
20
50
Temperature Stability (Note 5)
Total Output Variation (Note 5)
Shorter Circuit Current
Output Noise Voltage (Note 5)
Long Term Stability (Note 5)
Oscillator Section(Note 6)
Initial Accuracy (Notes 5 & 6)
Voltage Stability (Notes 5 & 6)
Temperature Stability (Note 5)
Minimum Frequency
Over Operating Range
Line, Load, and Temperature
20
50
20
50
5.00
5.20
100
200
50
4.95
5.25
100
V
V
REF = 0, TJ = 25°C
80
40
20
80
40
20
mA
10Hz ≤ 10kHz, TJ = 25°C
200 µVrms
TJ = 125°C
50
mV
TJ = 25°C
± 2
± 0.3
± 3
± 6
± 1
± 6
120
± 2
± 1
± 3
± 6
± 2
± 6
120
%
%
VIN = 8 to 35V
Over Operating Range
RT = 200kΩ, CT = 0.1µF
RT = 2kΩ, CT = 470pF
%
Hz
kHz
mA
V
Maximum Frequency
400
1.7
3.0
0.3
1.2
400
1.7
3.0
0.3
1.2
Current Mirror
I
RT = 2mA
2.0
3.5
0.5
2.0
1.0
2.2
2.0
3.5
0.5
2.0
1.0
2.2
Clock Amplitude (Notes 5 & 6)
Clock Width (Notes 5 & 6)
Sync Threshold
TJ = 25°C
1.0
2.8
2.5
1.0
2.8
2.5
µs
V
Sync Input Current
Sync Voltage = 3.5V
mA
Error Amplifier Sectio(nVCM = 5.1V)
Input Offset Voltage
0.5
1
5
10
1
2
1
10
10
1
mV
µA
Input Bias Current
Input Offset Current
µA
DC Open Loop Gain
RL ≥ 10MΩ
60
1
75
2
60
1
75
2
dB
Gain-Bandwidth Product
(Note 5)
AV = 0dB, TJ = 25°C
MHz
DC Transconductance
(Notes 5 & 7)
TJ = 25°C, 30kΩ ≤ RL ≤ 1MΩ
1.1
1.5
1.1
1.5
mS
Output Low Level
0.2
5.6
75
0.5
0.2
5.6
75
0.5
V
V
Output High Level
3.8
60
50
3.8
60
50
Common Mode Rejection
Supply Voltage Rejection
V
V
CM = 1.5 to 5.2V
IN = 8 to 35V
dB
dB
60
60
Note 5: These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
Note 6: Tested at fOSC = 40kHz (RT = 3.6kW, CT = 0.01mF, RD = 0W). Approximate oscillator frequency is defined by:
1
f =
CT (0.7RT + 3RD )
Note 7: DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV = gMRL
where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum AV when the
error amplifier output is loaded.
3
UC1525A/27A
UC2525A/27A
UC3525A/27A
ELECTRICAL CHARACTERISTICS:+VIN = 20V, and over operating temperature, unless otherwise specified, TA = TJ.
UC1525A/UC2525A
UC1527A/UC2527A
UC3525A
UC3527A
UNITS
PARAMETER
PWM Comparator
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
Minimum Duty-Cycle
0
0
%
%
V
Maximum Duty-Cycle (Note 6)
Input Threshold (Note 6)
45
49
0.9
3.3
.05
45
49
0.9
3.3
.05
Zero Duty-Cycle
Maximum Duty-Cycle
0.7
0.7
3.6
1.0
3.6
1.0
V
Input Bias Current (Note 5)
Shutdown Section
µA
Soft Start Current
V
V
SD = 0V, VSS = 0V
SD = 2.5V
25
50
0.4
0.8
0.4
0.2
80
0.7
1.0
1.0
0.5
25
50
0.4
0.8
0.4
0.2
80
0.7
1.0
1.0
0.5
µA
V
Soft Start Low Level
Shutdown Threshold
Shutdown Input Current
Shutdown Delay (Note 5)
To outputs, VSS = 5.1V, TJ = 25°C
SD = 2.5V
VSD = 2.5V, TJ = 25°C
0.6
0.6
V
V
mA
µs
Output Drivers(Each Output) (VC = 20V)
Output Low Level
Output High Level
I
SINK = 20mA
0.2
1.0
19
18
7
0.4
2.0
0.2
1.0
19
18
7
0.4
2.0
V
V
ISINK = 100mA
I
I
SOURCE = 20mA
SOURCE = 100mA
18
17
6
18
17
6
V
V
Under-Voltage Lockout
VC OFF Current (Note 7)
Rise Time (Note 5)
V
COMP and VSS = High
8
8
V
VC = 35V
200
600
300
200
600
300
µA
ns
ns
CL = 1nF, TJ = 25°C
CL = 1nF, TJ = 25°C
100
50
100
50
Fall Time (Note 5)
Total Standby Current
Supply Current
VIN = 35V
14
20
14
20
mA
Note 5: These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
Note 6: Tested at fOSC = 40kHz (RT = 3.6kW, CT = 0.01mF, RD = 0W)
Note 7: Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A.
4
UC1525A/27A
UC2525A/27A
UC3525A/27A
PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS
UC1525A output circuit (1/2 circuit shown).
UC1525A output saturation characteristics.
For single-ended supplies, the driver outputs are
grounded. The VC terminal is switched to ground by the
totem-pole source transistors on alternate oscillator
cycles.
In conventional push-pull bipolar designs, forward base
drive is controlled by R1-R3. Rapid turn-off times for the
power devices are achieved with speed-up capacitors
C1 and C2.
The low source impedance of the output drivers provides
rapid charging of power FET Input capacitance while
minimizing external components.
Low power transformers can be driven by the UC1525A.
Automatic reset occurs during dead time, when both
ends of the primary winding are switched to ground.
5
UC1525A/27A
UC2525A/27A
UC3525A/27A
UC1525A oscillator schematic.
PRINCIPLES OF OPERATION AND TYPICAL CHARAC- turn-off signal to the outputs; and a 150µA-current sink
TERISTIC SHUTDOWN OPTIONS
(See Block Diagram)
begins to discharge the external soft-start capacitor. If the
shutdown command is short, the PWM signal is termi-
nated without significant discharge of the soft-start ca-
Since both the compensation and soft-start terminals
(Pins 9 and 8) have current source pull-ups, either can
readily accept a pull-down signal which only has to sink a
maximum of 100µA to turn off the outputs. This is subject
to the added requirement of discharging whatever exter-
nal capacitance may be attached to these pins.
pacitor, thus, allowing, for example,
a convenient
implementation of pulse-by-pulse current limiting. Holding
Pin 10 high for a longer duration, however, will ultimately
discharge this external capacitor, recycling slow turn-on
upon release.
Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation. All transitions of
the voltage on pin 10 should be within the time frame of
one clock cycle and not repeated at a frequency higher
than 10 clock cycles.
An alternate approach is the use of the shutdown circuitry
of Pin 10 which has been improved to enhance the avail-
able shutdown options. Activating this circuit by applying
a positive signal on Pin 10 performs two functions; the
PWM latch is immediately set providing the fastest
Oscillator Charge Time vs RT and CT.
Oscillator Discharge Time vs RD and CT.
6
UC1525A/27A
UC2525A/27A
UC3525A/27A
RL is impedance from pin 9 to ground. Values below 30kΩ
will begin to limit the maximum duty cycle.
Maximum value RD vs minimum value RT.
Error amplifier voltage gain and phase vs frequency.
Lab test fixture.
7
UC1525A/27A
UC2525A/27A
UC3525A/27A
REVISION HISTORY
REVISION
DATE
CHANGE
SLUS191B
6/28/05
Updated pin 10 description in the Principles of Operation and Typical
Characteristics Shutdown Options Section.
8
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