UC2572D [TI]
Negative Output Flyback Pulse Width Modulator;
| 型号： | UC2572D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Negative Output Flyback Pulse Width Modulator 开关 光电二极管 |
| 文件： | 总9页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1572
UC2572
UC3572
Negative Output Flyback Pulse Width Modulator
FEATURES
DESCRIPTION
• Simple Single Inductor Flyback PWM
for Negative Voltage Generation
The UC3572 is a negative output flyback pulse width modulator which con-
verts a positive input voltage to a regulated negative output voltage. The
chip is optimized for use in a single inductor negative flyback switching con-
verter employing an external PMOS switch. The block diagram consists of
a precision reference, an error amplifier configured for voltage mode opera-
tion, an oscillator, a PWM comparator with latching logic, and a 0.5A peak
gate driver. The UC3572 includes an undervoltage lockout circuit to insure
sufficient input supply voltage is present before any switching activity can
occur, and a pulse-by-pulse current limit. Output current can be sensed and
limited to a user determined maximum value. The UVLO circuit turns the
chip off when the input voltage is below the UVLO threshold. In addition, a
sleep comparator interfaces to the UVLO circuit to turn the chip off. This re-
duces the supply current to only 50µA, making the UC3572 ideal for battery
powered applications.
• Drives External PMOS Switch
• Contains UVLO Circuit
• Includes Pulse-by-Pulse Current Limit
• Low 50µA Sleep Mode Current
BLOCK DIAGRAM
UDG-94094-2
SLUS275A - MARCH 1999 - REVISED AUGUST 2001
UC1572
UC2572
UC3572
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V
EAINV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC
IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
RAMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
CS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7A to 0.7A
I3VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15mA
Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
DIL-8, SOIC-8 (TOP VIEW)
D, N or J Packages
Currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
ORDERING INFORMATION
TEMPERATURE RANGE
–55°C to +125°C
–40°C to +85°C
PACKAGE
J
UC1572
UC2572
UC3572
D, N or J
D or N
0°C to +70°C
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Reference Section
3VREF
2.94
3
1
1
3.06
10
V
Line Regulation
Load Regulation
Oscillator Section
Frequency
VCC = 4.75 to 30V
mV
mV
I3VREF = 0V to –5mA
10
VCC = 5V to 30V
85
100
115
kHz
Error Amp Section
EAINV
EAOUT = 2V
–10
0
–0.2
–0.2
90
10
mV
V
IEANV = –1mA
–0.9
–1.0
IEAINV
EAOUT = 2V
A
AVOL
EAOUT = 0.5V to 3V
EAINV = –100mV
65
dB
V
EAOUT High
EAOUT Low
IEAOUT
3.6
4
4.4
0.2
EAINV = 100mV
0.1
V
EAINV = –100mV, EAOUT = 2V
EAINV = 100mV, EAOUT = 2V
TJ = 25°C, F = 10kHz
–350 –500
µA
mA
MHz
7
20
1
Unity Gain Bandwidth
Current Sense Comparator Section
Threshold
0.6
0.185 0.205 0.225
V
Input Bias Current
CS = 0
–0.4
300
–1
µA
nS
CS Propogation Delay
2
UC1572
UC2572
UC3572
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.
PARAMETER
Gate Drive Output Section
OUT High Saturation
TEST CONDITIONS
MIN
TYP
MAX UNITS
IOUT = 0
0
0.3
1.5
2.5
0.4
2.2
80
V
V
IOUT = –10mA
IOUT = –100mA
IOUT = 10mA
IOUT = 100mA
0.7
1.5
0.1
1.5
30
V
OUT Low Saturation
V
V
Rise Time
TJ = 25°C, CLOAD = 1nF + 3.3 Ohms
TJ = 25°C, CLOAD = 1nF + 3.3 Ohms
nS
nS
Fall Time
30
80
Pulse Width Modulator Section
Maximum Duty Cycle
Minimum Duty Cycle
Modulator Gain
EAINV = +100mV, VCC = 5V to 30V
EAINV = –100mV, VCC = 5V to 30V
EAOUT = 1.5V to 2.5V
92
55
96
0
%
%
45
65
%/V
Undervoltage Lockout Section
Start Threshold
3.5
4.2
4.5
V
Hysteresis
100
200
300
mV
Sleep Mode Section
Threshold
1.8
2.2
2.6
V
Supply Current Section
IVCC
VCC = 5V, 30V
9
15
mA
A
VCC = 30, CS = 3V
50
150
UDG-94095
Figure 1. Typical waveforms.
3
UC1572
UC2572
UC3572
PIN DESCRIPTIONS
3VREF: Precision 3V reference. Bypass with 100nF ca- OUT: Gate drive for external PMOS switch connected
pacitor to GND.
between VCC and the flyback inductor. OUT drives the
gate of the PMOS switch between VCC and GND.
CS: Current limit sense pin. Connect to a ground refer-
enced current sense resistor in series with the flyback in- RAMP: Oscillator and ramp for pulse width modulator.
ductor. OUT will be held high (PMOS switch off) if CS Frequency is set by a capacitor to GND by the equation
exceeds 0.2V.
1
F =
15k • CRAMP
EAINV: Inverting input to error amplifier. Summing junc-
tion for 3VREF and VOUT sense. The non-inverting input
of the error amplifier is internally connected to GND. This
pin will source a maximum of 1mA.
Recommended operating frequency range is 10kHz to
200kHz.
VCC: Input voltage supply to chip. Range is 4.75 to 30V.
Bypass with a 1µF capacitor.
EAOUT: Output of error amplifier. Use EAOUT and EAINV
for loop compensation components.
GND: Circuit Ground.
VIN
RSLEEP3
1MEG
SLEEP
M
SLEEP
CV
10µF
CC
C
10µF
IN
UC1572
4
8
7
1
2
6
VCC
C3V
100nF
OUT
5
REF
M
SWITCH
3VREF
RAMP
EAINV
EAOUT
GND
C
680pF
RAMP
R
SLEEP1
56k
R
REF
L
FLYBACK
R
C
COMP
R
D
SLEEP2
33k
FLYBACK
COMP
CS
3
R
CS
GND
GND
–12V OUT
COUT
100µF
RV
40k
SENSE
VOUT
UDG-99057
Figure 2. Typical application: +5V to –12V flyback converter.
4
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
SOIC
Drawing
UC1572J
UC2572D
OBSOLETE
ACTIVE
J
8
8
TBD
Call TI
Call TI
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
UC2572DG4
UC2572DTR
UC2572DTRG4
UC2572N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
P
P
D
D
D
D
P
P
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UC2572NG4
UC3572D
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
UC3572DG4
UC3572DTR
UC3572DTRG4
UC3572N
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UC3572NG4
50 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Apr-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
UC2572DTR
UC3572DTR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Apr-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC2572DTR
UC3572DTR
SOIC
SOIC
D
D
8
8
2500
2500
340.5
340.5
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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