UC2584DW [TI]
Secondary Side Synchronous Post Regulator;
| 型号： | UC2584DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Secondary Side Synchronous Post Regulator 开关 光电二极管 |
| 文件： | 总7页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1584
UC2584
UC3584
Secondary Side Synchronous Post Regulator
FEATURES
DESCRIPTION
• Practical Operation at Switching
Frequencies up to 1MHz
The UC3584 is a low voltage, Secondary Side Synchronous Post Regula-
tor. It is intended to be used for auxiliary output voltage regulation in single
secondary winding, multiple output power supplies (for more details refer
to the Application Section of this Data sheet). The UC3584 is most suited
for systems where the main output is regulated between 5V and 14V. Out-
put voltages regulated by the UC3584 can range from virtually 0V up to
the output voltage of the main output.
• Wide Band Error Amplifier
• Undervoltage Lockout with Hysteresis
• Output Active Low During UVLO
• Soft Start/Maximum Duty Cycle
Control
Auxiliary output voltage regulation with the UC3584 uses leading edge
modulation making it compatible to primary side peak current or voltage
mode control. The UC3584 clock circuit is synchronized to the switching
frequency utilizing the falling edge of the transformer’s secondary winding
waveform.
• Trimmed Bandgap Reference
• Internally Regulated 15V Boost
Supply
• Short Circuit Protection with
Programmable Delay
TYPICAL APPLICATION DIAGRAM.
7µH
5V
MAIN
33µH
COILTRONICS
IRFR024
OS-CON
330µF
+
+
10
10
2
2
1µF
390µF
3.3V
AUX
+
+
+
+
1500pF
0.1µF
CSHD
10-45L
100Ω
1.5W
30.1kΩ
170kHz
PUSH-PULL
4.75kΩ
1.33kΩ
1kΩ
1
FB
SYNC 16
CT 15
220pF
3300pF
100pF
120pF
24.3kΩ
3.57kΩ
3.3Ω
15kΩ
20kΩ
RT 14
1N4148
2
3
COMP
SS
0.1µF
0.1µF
VREG 13
1000pF
10µF
4
5
CDLY
GND
0.1µF
VCC 12
+
SOLID
TANTALUM
10BQ040
33µH
6
SRC
COLTRONICS
BST2 11
PGND 10
1.5µF
+
470µF
7
8
OUT
VFLT
BST1
9
1N4148
UDG-99062
03/99
UC1584
UC2584
UC3584
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
VFLT Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V, 30V at 2A
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 20V
SYNC Maximum Sink Current. . . . . . . . . . . . . . . . . . . . . 600µA
PWM Driver, IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 300mA
PWM Driver, IOUT (Peak). . . . . . . . . . . . . . . . . . . . . . . . . ± 1.5A
Maximum Operating Frequency . . . . . . . . . . . . . . . . . . . . 1MHz
Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . 300°C
Currents are positive into, negative out of specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
CONNECTION DIAGRAMS
ORDERING INFORMATION
TEMPERATURE RANGE
–55°C to +125°C
PACKAGE
CDIP
DIL-16, SOIC-16 (Top View)
J, N or DW Packages
UC1584J
UC2584DW
UC2584N
UC3584DW
UC3584N
–40°C to +85°C
SOIC-Wide
PDIP
0°C to +70°C
SOIC-Wide
PDIP
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C for the UC3584, –40°C to 85°C for
the UC2584, and –55°C to 125°C for the UC1584, VCC = 15V. TA = TJ.
PARAMETERS
Error Amplifier
TEST CONDITIONS
MIN TYPE MAX UNITS
FB
COMP = FB
VCOMP = VFB
1.468
150
1.5
300
50
1.532
450
400
7
V
nA
mV
V
IFB
COMP VOL
COMP VOH
AVOL
FB = 1.6V, ICOMP = 200µA
FB = 1.4V, ICOMP = –200µA
5.1
60
60
5
5.5
80
dB
dB
MHz
PSRR (COMP)
GBW Product
Oscillator
Frequency
Ramp Low
Ramp High
Ramp Amplitude
PWM
COMP = FB, VCC = 14V to 16V
F = 100kHz
10
RT = 3.75k, CT = 400pF, No Synchronization
RT = 3.75k, CT = 400pF, No Synchronization
RT = 3.75k, CT = 400pF, No Synchronization
RT = 3.75k, CT = 400pF, No Synchronization
500
1.75
3.5
kHz
V
V
1.75
V
Maximum Duty Cycle
Minimum Duty Cycle
PWM DRIVER
VSAT High
VSAT Low
COMP = 4.5V
COMP = 0V
90
%
%
0
VFLT – VOUT, IOUT = –100mA
2.5
0.8
75
3
V
V
VOUT – VSRC, IOUT = 50mA
2.2
100
100
TRISE
Load = 1nF, SRC = 0V, Measure VOUT 1V to 9V
Load = 1nF, SRC = 0V, Measure VOUT 9V to 1V
ns
ns
TFALL
25
2
UC1584
UC2584
UC3584
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C for the UC3584, –40°C to 85°C for the
UC2584, and –55°C to 125°C for the UC1584, VCC = 15V. TA = TJ.
PARAMETERS
TEST CONDITIONS
MIN TYPE MAX UNITS
Soft Start
Charge Current
Discharge Current
SS Delay
30
1
µA
mA
ms
C
SS = 500nF
50
Fault Latch
Charge Current
Discharge Current
Fault Latch Delay
UVLO
30
5
µA
mA
ms
CDLY = 500nF
50
VCC On
10.5
1.7
V
V
Hysteresis
Regulated Voltage
VREG
IREG = 0mA to 1mA
4.8
14
5.2
V
VCC Regulator
VCC
Boost inductor connected to 5V
15
12
55
16
40
V
ICC
No Load, Boost Circuitry Inactive
No Load, Boost Circuitry Active (Note 1)
mA
mA
Note 1: Guaranteed by design. Not 100% tested in production.
BLOCK DIAGRAM
UDG-97141
3
UC1584
UC2584
UC3584
PIN DESCRIPTIONS
BST1: Collector of the boost switch. This is the RT: A Timing Resistor connected between RT and GND
connection point of the external boost inductor and boost sets the discharge current of the timing capacitor.
diode. The boost converter generates the bias supply for
the UC3584 from the regulated 5V output.
SRC: Source connection of the floating driver to the
external switch.
BST2: See BST1. BST2 must be connected externally
SS: Soft Start. An external capacitor is connected
to BST1 pin.
between SS and GND to set the duration of the Soft
CDLY: Delay Set. External CDLY capacitor sets the Start cycle.
delay from the time Short Circuit condition is detected
and Fault Condition is asserted.
SYNC: Synchronization Pin. The UC3584 is
synchronized from the falling edge of the transformer’s
COMP: Output of the Voltage Error Amplifier.
CT: Connect the Timing Capacitor between CT and GND.
FB: Inverting Input of the Voltage Error Amplifier.
GND: Analog System Ground.
secondary winding. Voltage must exceed 1V at minimum
input line.
VCC: Bias supply of the chip, approximately 15V. This is
also the output of the boost regulator. The VCC pin must
be decoupled to PGND.
OUT: Output of the floating driver for an external,
N-channel MOSFET.
VFLT: Positive rail of the floating driver’s bias supply.
Decouple to SRC using a high frequency (ceramic)
capacitor.
PGND: Power Ground. This is the reference node for the
boost bias supply regulator. PGND and GND must be
connected externally.
VREG: Output of the internal 5V regulated supply. Must
be decoupled to GND.
APPLICATION INFORMATION
Biasing the UC3584
Oscillator and Trailing Edge Synchronization
Bias supply for the UC3584 is generated from the main The UC3584 is outfitted with a synchronizable oscillator
output of the power supply by a boost regulator. The in- which also generates a ramp signal across the CT capac-
ductor, diode and capacitor of the boost converter are ex- itor for the PWM comparator. For easy implementation of
ternal components, while the boost switch is internal to the leading edge pulse width modulation technique, the
the chip. The boost converter operates in a burst mode oscillator has an inverted ramp waveform as shown in
with a built-in hysteresis of approximately 1V centered at Fig. 1. The free running oscillator frequency is deter-
15V. This is a bang-bang controller and when enabled mined by the timing components, RT and CT, according
has a fixed duty cycle of 75%.
to the following approximate equations:
1.7
Undervoltage Detection
9.3
RT
=
1−DMAX
The UVLO circuit of the UC3584 monitors the voltage on
VCC. During power up and power down, the pulse width
modulator and the output driver are disabled and OUT is
held active low. Operation is enabled when VCC reaches
10.5V. The UVLO circuitry has a built-in hysteresis of
1.7V (10.5V to 8.8V) thus VCC must drop below 8.8V in
order to assert UVLO again.
2− 8.2×108 • C
(
)
T
fOSC
=
0.9
R
• CT
(
)
T
where
R is the timing resistor, its value should be between
T
Precision Reference
1kΩ and 100kΩ,
An internal precision bandgap reference provides accu-
rate voltages to the error amplifier and other control sec-
tions of the IC. A buffered 5V regulated voltage is also
available for external circuitry on the VREG pin. This pin
must be decoupled to the signal GND connection by a
good quality high frequency capacitor.
C is the timing capacitor,
T
D
MAX
is the desired maximum duty cycle, and
f
is the free running oscillator frequency.
OSC
Figure 2 graphically depicts the measured frequency
data.
4
UC1584
UC2584
UC3584
APPLICATION INFORMATION (cont.)
VSEC
INTERNAL
SYNC PULSE
CT
COMP
OUT
UDG-99064
Figure 1. Trailing edge synchronization, leading edge modulation.
Edge Modulation
1. VCC within normal range (UVLO is inactive),
2. No fault condition is detected,
3. C is discharging.
During normal operation the oscillator must be synchro-
nized to the falling edge of the transformer secondary
waveform. Synchronization is achieved by connecting
SYNC to the secondary winding via a resistor divider.
The resistor divider must be chosen to provide a SYNC
pin voltage in excess of 1V at the lowest operating volt-
age on the transformer secondary winding. The UC3584
will generate a narrow internal synchronization pulse
which will synchronize the oscillator to the switching fre-
quency of the main converter.
T
During the fast charging time of the C capacitor is held
T
low.
Ultimately, the output of the PWM circuitry controls the
conduction interval of an external N-channel MOSFET
switch in the power supply. The UC3584 employs an
on-board, floating gate driver circuit to interface to the
external switch. An external capacitor connected be-
tween VFLT and SRC acts as a floating power supply for
PWM and Output Driver
The UC3584 employs leading edge modulation tech-
nique to set the required on time of its output. Leading
edge modulation is preferred for secondary side regula-
tion in multiple output converters to prevent ambiguity in
the primary current waveform. In fact, this is the only fea-
sible technique to preserve compatibility with primary
side peak current mode control.
1.E+06
1.E+05
1.E+04
47pF
As Fig. 1 depicts the UC3584 utilizes voltage mode con-
trol to regulate output voltage. The output pulse width
(the on-time of the MOSFET switch) is determined on a
cycle-by-cycle basis by comparing the output of the volt-
age error amplifier and the ramp waveforms across the
timing capacitor. OUT is asserted when the voltage on
COMP exceeds the voltage on CT. There are three more
conditions which must be satisfied to obtain an active
high on the OUT pin. These conditions are:
100pF
470pF
220pF
1000pF
1500pF
1.E+04
1200pF
1.E+03
1.E+05
TIMING RESISTOR (Ohms)
Figure 2. Oscillator frequency vs. R with C as a
T
T
parameter.
5
UC1584
UC2584
APPLICATION INFORMATION (cont.)
the driver during the on-time of the switch. Charge is be- below 5V, a fault condition is declared, the PWM output
ing replenished to the bootstrap capacitor during the is disabled and soft start cycle is initiated. Under persis-
off-time of the switch through the bootstrap diode con- tent fault conditions the UC3584 will continuously cycle
nected between VCC and VFLT as shown in the typical through soft start sequence, attempting to bring the out-
application diagram.
put to its regulated, nominal voltage. The value of CDLY
capacitor should be chosen large enough to delay the
activation of the fault sequence in case of load transients
which can also cause the error amplifier output to go
high temporarily.
Soft Start
The UC3584 Soft Start circuitry is designed to implement
closed loop startup of the power supply output. During
Soft Start, the reference to the noninverting input of the
error amplifier is controlled by the voltage across the soft
Error Amplifier
start capacitor on SS. As this voltage rises, it provides an The Error Amplifier of the UC3584 is used to regulate the
increasing reference to the error amplifier. Once the soft voltage of an auxiliary output in a power supply. The
start capacitor charges above the 1.5V precision refer- noninverting input of the error amplifier is connected to
ence of the error amplifier, SS gets disconnected from an internal, 1.5V reference. The inverting input (FB pin)
the noninverting input of the error amplifier. This tech- is tied to an output voltage divider. The compensation
nique allows the error amplifier to stay in its linear mode network of the negative feedback loop is connected be-
and to regulate the output voltage of the power supply tween the amplifier’s output (COMP pin) and FB. The
according to the gradually increasing reference voltage noninverting input of the error amplifier is also connected
on its noninverting input. Further advantage of the closed to the SS node through a diode. This arrangement allows
loop start up scheme is the absence of output voltage closed loop soft start for the output of a power supply
overshoot during power up of the power supply output.
regulated by the UC3584. Closed loop soft start assures
that the error amplifier is kept in active mode and the out-
put voltage of the converter follows the reference voltage
on its noninverting input as it ramps up (following the SS
node). If a fault condition is detected, SS node gets
pulled to ground, forcing the error amplifier’s reference
low. Consequently, the error amplifier’s output voltage
goes low and duty cycle is reduced.
Fault Detection
Fault Detection feature is implemented to detect exces-
sive overload conditions. Under these conditions the er-
ror amplifier output goes high to command the maximum
duty cycle. As soon as the error amplifier’s output ex-
ceeds 5V, the fault delay capacitor connected to the
CDLY pin starts charging. If C
capacitor voltage
DLY
reaches 2V before the error amplifier output falls back
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
6
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