UC2714J [TI]
Complementary Switch FET Drivers; 辅助开关FET驱动器
| 型号： | UC2714J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Complementary Switch FET Drivers |
| 文件： | 总16页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
Complementary Switch FET Drivers
Check for Samples: UC1714, UC1715, UC2714, UC2715, UC3714, UC3715
1
FEATURES
DESCRIPTION
These two families of high speed drivers are
designed to provide drive waveforms for
•
•
Single Input (PWM and TTL Compatible)
High-Current Power FET Driver, 1-A Source
and 2-A Sink
complementary switches. Complementary switch
configurations are commonly used in synchronous
rectification circuits and active clamp/reset circuits,
which provide zero voltage switching. In order to
facilitate the soft switching transitions, independently
programmable delays between the two output
waveforms are provided on these drivers. The delay
pins also have true-zero voltage-sensing capability
•
•
Auxiliary Output FET Driver, 0.5-A Source and
1-A Sink
Time Delays Between Power and Auxiliary
Outputs Independently Programmable from 50
to 500-ns
•
Time Delay or True Zero-Voltage Operation
Independently Configurable for Each Output
which
allows
immediate
activation
of
the
corresponding switch when zero voltage is applied.
These devices require a PWM-type input to operate
and interface with commonly available PWM
controllers.
•
•
•
•
•
Switching Frequency to 1 MHz
Typical 50-ns Propagation Delays
ENBL Pin Activates 220-μA Sleep Mode
Power Output is Active-Low in Sleep Mode
Synchronous Rectifier Driver
In the UC1714 series, the AUX output is inverted to
allow driving a p-channel MOSFET. In the UC1715
series, the two outputs are configured in a true
complementary fashion.
BLOCK DIAGRAM
2
PWR
50ns œ500ns
TIMER
INPUT
T1
6
7
S
Q
R
UC1714
ONLY
VREF
4
1
AUX
VCC
50ns œ500ns
TIMER
S
Q
VCC
BIAS
ENBL
GND
5V
LOGIC
GATES
T2
5
R
VREF
TIMER
REF
3V
3
GND
1.4V
ENBL
8
ENABLE
Pin numbers refer to J, N and D packages.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)(2)
Auxiliary Driver IOH
MIN
MAX
–100
–500
200
1
UNIT
mA
mA
mA
A
continuous
peak
Auxiliary Driver IOL
continuous
peak
Input Voltage Range (INPUT, ENBL)
Power Driver IOH
–0.3
20
V
continuous
peak
–200
–1
mA
A
Power Driver IOL
continuous
peak
400
2
mA
A
VCC
Supply voltage
20
V
Lead Temperature (Soldering 10 seconds)
Operating Junction Temperature(3)
Storage Temperature Range
300
150
150
°C
°C
°C
–65
(1) Consult the Packaging Section at the end of this datasheet for thermal limitations and specifications of packages.
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals.
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, VCC = 15 V, ENBL ≥ 2 V, RT1 = 100 kΩ from T1 to GND, RT2 = 100 kΩ from T2 to GND, and −55°C
< TA < 125°C for the UC1714 and UC1715, –40°C < TA < 85°C for the UC2714 and UC2715, and 0°C < TA < 70°C for the
UC3714 and UC3715, TA = TJ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Overall
VCC
7
20
24
V
ICC
Nominal
Sleep mode
Power Driver (PWR)
Pre turn-on PWR output, low
ENBL = 2 V
18
mA
µA
ENBL = 0.8 V
200
300
VCC = 0 V, IOUT = 10 mA, ENBL at
0.8 V
0.3
1.6
V
VPWR
PWR output low, sat.
PWR output high, sat.
INPUT = 0.8 V, IOUT = 40 mA
INPUT = 0.8 V, IOUT = 400 mA
INPUT = 2 V, IOUT = −20 mA
INPUT = 2 V, IOUT = −200 mA
CL = 2200 pF
0.3
2.1
2.1
2.3
30
0.8
2.8
3
V
V
VCC
−
VPWR
3
Rise time
60
60
80
700
100
ns
ns
Fall time
CL = 2200 pF
25
T1 Delay, AUX to PWR
INPUT rising edge, RT1 = 10 kΩ(1)
INPUT rising edge, RT1 = 100 kΩ(1)
INPUT falling edge, 50%(2)
20
35
ns
ns
350
500
35
PWR Prop Delay
Auxiliary Driver (AUX)
VAUX AUX output low, sat.
VIN = 2 V, IOUT = 20 mA
VIN = 2 V, IOUT = 200 mA
VIN = 0.8 V, IOUT = –10 mA
VIN = 0.8 V, IOUT = –100 mA
CL = 1000 pF
0.3
1.8
2.1
2.3
45
0.8
2.6
3
V
VCC
–
AUX output high, sat.
Rise Time
V
VAUX
3
60
ns
(1) T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is defined from the
90% of the falling edge of PWR to the 50% point of the transition edge of AUX.
(2) Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal’s transition with no
load on outputs.
2
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, VCC = 15 V, ENBL ≥ 2 V, RT1 = 100 kΩ from T1 to GND, RT2 = 100 kΩ from T2 to GND, and −55°C
< TA < 125°C for the UC1714 and UC1715, –40°C < TA < 85°C for the UC2714 and UC2715, and 0°C < TA < 70°C for the
UC3714 and UC3715, TA = TJ
PARAMETER
Fall Time
TEST CONDITIONS
MIN
TYP
30
MAX
60
UNIT
CL = 1000 pF
ns
T2 Delay, PWR to AUX
INPUT falling edge, RT2 = 10 kΩ(1)
INPUT falling edge, RT2 = 100 kΩ(1)
INPUT rising edge, 50%(2)
20
50
80
ns
ns
250
350
35
550
80
AUX Prop Delay
Enable (ENBL)
Input Threshold
Input Current
Input Current
0.8
2.7
1.2
1
2
10
V
IIH
IIL
ENBL = 15 V
ENBL = 0 V
µA
µA
–1
–10
T1
Current Limit
T1 = 0 V
–1.6
3
–2
3.3
70
mA
V
Nominal Voltage at T1
Minimum T1 Delay
T1 = 2.5 V(1)
T2 = 0 V
40
ns
T2
Current Limit
–1.2
3
–2
3.3
mA
V
Nominal Voltage at T2
Minumum T2 Delay
2.7
0.8
T2 = 2.5 V(1)
50
100
ns
Input (INPUT)
Input Threshold
1.4
1
2
10
V
IIH
IIL
Input Current
Input Current
INPUT = 15 V
INPUT = 0 V
µA
µA
–5
–20
DEVICE INFORMATION
DIL-8, SOIC-8; J or N, D Packages
(TOP VIEW)
SOIC-16; DP Package
(TOP VIEW)
Copyright © 1999–2013, Texas Instruments Incorporated
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
www.ti.com
PIN DESCRIPTIONS
AUX The AUX switches immediately at the rising edge of INPUT’but waits through the T2 delay after the falling
edge of INPUT before switching. AUX is capable of sourcing 0.5 A and sinking 1 A of drive current. See
the Time Relationships diagram below (Figure 1) for the differences between the UC1714 and UC1715 for
INPUT, MAIN, and AUX. During sleep mode, AUX is inactive with a high impedance.
ENBL The ENBL input switches at TTL logic levels (approximately 1.2 V), and the input range is from 0 to 20 V.
The ENBL input places the device into sleep mode when it is a logical low. The current into VCC during
the sleep mode is typically 220 μA.
GND This is the reference pin for all input voltages and the return point for all device currents. GND carries the
full peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must
be damped or clamped such that GND remains the most negative potential.
INPUT The input switches at TTL logic levels (approximately 1.4 V) but the allowable range is from 0 to 20 V,
allowing direct connection to most common IC PWM controller outputs. The rising edge immediately
switches the AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly,
the INPUT falling edge immediately turns off the PWR output and initiates a timing delay, T2, before
switching the AUX output.
Note that if the input signal comes from a controller with FET drive capability, this signal provides another
option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide the delay
at the trailing edge.
PWR The PWR output waits for the T1 delay after the rising edge of INPUT before switching on, but switches
off immediately at the falling edge of INPUT’(neglecting propagation delays). This output is capable of
sourcing 1 A and sinking 2 A of peak gate-drive current. PWR output includes a passive, self-biased circuit
which holds this pin active low, when ENBL ≤ 0.8V regardless of the voltage of VCC.
T1
T2
A resistor to ground programs the time delay between the AUX switch turnoff and PWR turnon.
This pin functions in the same way as T1 but controls the time delay between PWR turnoff and activation
of the AUX switch.
T1, T2 The resistor on each of these pins sets the charging current on internal timing capacitors to provide
independent time control. The nominal voltage level at each pin is 3 V and the current is internally limited
to 1 mA. The total delay from INPUT to each output includes a propagation delay in addition to the
programmable timer but because the propagation delays are approximately equal, the relative time delay
between the two outputs can be assumed to be solely a function of the programmed delays. The
relationship of the time delay vs. RT is shown in the TYPICAL CHARACTERISTICS curves (see Figure 2).
Either or both pins are alternatively used for voltage sensing in lieu of delay programming, which is done
by pulling the timer pins below their nominal voltage level which immediately activates the timer output.
VCC The VCC input range is from 7 to 20 V. This pin must be bypassed with a capacitor to GND consistent with
peak load current demands.
4
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
TYPICAL CHARACTERISTICS
T1 DELAY, T2 DELAY
vs
RT
TIME RELATIONSHIPS
INPUT
PROPAGATION
DELAYS
PWR OUTPUT
T1 DELAY
T2 DELAY
UC1714 AUX OUTPUT
UC1715 AUX OUTPUT
(2) T1 delay is defined from the 50% point of the transition edge of
AUX to the 10% of the rising edge of PWR. T2 delay is defined from
the 90% of the falling edge of PWR to the 50% point of the transition
edge of AUX.
Figure 1.
Figure 2.
ICC
vs
ICC
SWITCHING FREQUENCY WITH NO LOAD AND 50%
DUTY CYCLE RT1 = RT2 = 50 k
vs
RT WITH OPPOSITE RT = 50 k
Figure 3.
Figure 4.
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
T1 DEADBAND
vs
T2 DEADBAND
vs
TEMPERATURE AUX TO PWR
TEMPERATURE PWR TO AUX
Figure 5.
Figure 6.
6
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Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
TYPICAL APPLICATIONS
Figure 7. Typical Application With Timed Delays
Figure 8. Using The Timer Input For Zero-Voltage Sensing
Wake-up occurs with the first pulse while turnoff is determined by the (RTO CTO) time constant.
Figure 9. Self-Actuated Sleep Mode With The Absence Of An Input PWM Signal
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
www.ti.com
Figure 10. Using The UC1715 As A Complementary Synchronous Rectifier Switch Driver With N-Channel
FETs
VIN is limited to 10 V as VCC rises to approximately 2VIN
.
Figure 11. Synchronous Rectifier Application With A Charge Pump To Drive The High-Side N-Channel
Buck Switch
With active reset provided by the UC1714 driving an N-channel switch (Q1) and a P-channel auxiliary switch (Q2).
Figure 12. Typical Forward Converter Topology
8
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
www.ti.com
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
Figure 13. Using An N-Channel Active Reset Switch With A Floating Drive Command
Copyright © 1999–2013, Texas Instruments Incorporated
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
UC1714, UC1715, UC2714
UC2715, UC3714, UC3715
SLUS170B –FEBRUARY 1999–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (January 2002) to Revision B
Page
•
•
•
Added TI's general Absolute Maximum Ratings table note to end of Absolute Maximum table .......................................... 2
Changed ENBL ≥ 0.8V to ENBL ≤ 0.8V in PWR pin description .......................................................................................... 4
Changed layout from Unitrode Products datasheet to TI datasheet .................................................................................... 8
10
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Product Folder Links: UC1714 UC1715 UC2714 UC2715 UC3714 UC3715
PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
UC1714J
UC1715J
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
CDIP
CDIP
CDIP
SOIC
J
J
8
8
8
8
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
-55 to 125
-40 to 85
UC1715J883B
UC2714D
J
Call TI
Call TI
D
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-250C-1 YEAR
UC2714D
UC2714DG4
UC2714DTR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-250C-1 YEAR
Level-2-250C-1 YEAR
Level-2-250C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
UC2714D
UC2714D
UC2714D
2500
2500
Green (RoHS
& no Sb/Br)
UC2714DTRG4
Green (RoHS
& no Sb/Br)
UC2714J
UC2714N
OBSOLETE
ACTIVE
CDIP
PDIP
J
8
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
P
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2714N
UC2714N
UC2715D
UC2715D
UC2715DP
UC2715DP
UC2715D
UC2715D
UC2715N
UC2715N
UC3714D
UC2714NG4
UC2715D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
P
D
D
D
D
D
D
P
P
D
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-2-250C-1 YEAR
Level-2-250C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
75
Green (RoHS
& no Sb/Br)
UC2715DG4
UC2715DP
UC2715DPG4
UC2715DTR
UC2715DTRG4
UC2715N
8
75
Green (RoHS
& no Sb/Br)
16
16
8
40
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
2500
2500
50
Green (RoHS
& no Sb/Br)
8
Green (RoHS
& no Sb/Br)
8
Green (RoHS
& no Sb/Br)
UC2715NG4
UC3714D
8
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
8
75
Green (RoHS
& no Sb/Br)
Level-2-250C-1 YEAR
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
UC3714DG4
UC3714DTR
UC3714DTRG4
UC3714N
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
D
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-250C-1 YEAR
Level-2-250C-1 YEAR
Level-2-250C-1 YEAR
N / A for Pkg Type
UC3714D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
P
P
D
D
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
UC3714D
UC3714D
UC3714N
UC3714N
UC3715D
UC3715D
UC3715DP
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
UC3714NG4
UC3715D
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
75
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
UC3715DG4
75
Green (RoHS
& no Sb/Br)
0 to 70
UC3715DP
UC3715DPG4
UC3715DTR
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
16
16
8
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
2500
2500
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-250C-1 YEAR
UC3715D
UC3715D
UC3715N
UC3715N
UC3715DTRG4
UC3715N
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
PDIP
D
P
P
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-250C-1 YEAR
N / A for Pkg Type
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
Green (RoHS
& no Sb/Br)
UC3715NG4
50
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
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11-Apr-2013
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1714, UC1715, UC2714, UC2714M, UC3714, UC3715 :
Catalog: UC3714, UC3715, UC2714
•
Military: UC2714M, UC1714, UC1715
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC2714DTR
UC2715DTR
UC3714DTR
UC3715DTR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC2714DTR
UC2715DTR
UC3714DTR
UC3715DTR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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