UC28025NG4 [TI]
经济型双端高速 PWM 控制器 | N | 16 | -40 to 105;
| 型号： | UC28025NG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 经济型双端高速 PWM 控制器 | N | 16 | -40 to 105 开关 控制器 开关式稳压器 开关式控制器 光电二极管 电源电路 开关式稳压器或控制器 |
| 文件： | 总18页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀ ꢁꢂ ꢃꢄ ꢂꢆ
SLUS557B − MARCH 2003 − REVISED APRIL 2004
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FEATURES
DESCRIPTION
D
Peak Current Mode, Average Current Mode,
or Voltage Mode (with Feed-Forward) Control
Methods
The UC28023 and UC28025 are fixed-frequency
PWM controllers optimized for high-frequency
switched-mode power supply applications. The
UC28023 is a single output PWM for single-ended
topologies while the UC28025 offers dual
alternating outputs for double-ended and full
bridge topologies.
D
D
D
D
Practical Operation Up to 1 MHz
50-ns Propagation Delay to Output
1.5-A Peak Totem Pole Outputs
9-V to 30-V Nominal Operational Voltage
Range
Targeted for cost effective solutions with minimal
external components, UC2802x include an
oscillator, a temperature compensated reference,
a wide band width error amplifier, a high-speed
current-sense comparator and high-current
active-high totem-pole outputs to directly drive
external MOSFETs.
D
Wide Bandwidth Error Amplifier
D
Fully Latched Logic with Double Pulse
Suppression
D
D
D
D
D
Pulse-by-Pulse Current Limiting
Programmable Maximum Duty Cycle Control
Under−Voltage Lockout with Hysteresis
Trimmed 5.1-V Reference with UVLO
Same Functionality as UC3823 and UC3825
Protection circuitry includes a current limit
comparator with a 1-V threshold, a TTL
compatible shutdown port, and a soft-start pin
which will double as a maximum duty cycle clamp.
The logic is fully latched to provide jitter free
operation and prohibit multiple pulses at an
output. An undervoltage lockout section with
800 mV of hysteresis assures low start-up
current. During undervoltage lockout, the outputs
are high impedance. Particular care was given to
minimizing propagation delays through the
comparators and logic circuitry while maximizing
bandwidth and slew rate of the error amplifier.
APPLICATIONS
D
Off-Line and DC/DC Power Supplies
D
Converters Using Voltage Mode, Peak
Current Mode, or Average Current Mode
Control Methods
D
Single-Ended or Two-Switch Topology
Designs
Devices are available in the industrial temperature
range of −40°C to 105°C. Package offerings are
16-pin SOICW (DW), or 16-pin PDIP (N)
packages.
ORDERING INFORMATION
PACKAGED DEVICES
OUTPUT
CONFIGURATION
EXTERNAL CURRENT
LIMIT REFERENCE
T
T
J
A =
PDIP-16 (N)
SOICW−16 (DW)
UC28023DW
UC28025DW
Single
Yes
No
UC28023N
UC28025N
−40°C to 105°C
Dual Alternating
(1)
The DW package are also available taped and reeled. Add an R suffix to the device type (i.e., UC28023DWR (2,000 devices per reel).
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Copyright 2004, Texas Instruments Incorporated
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1
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ꢀ ꢁꢂꢃ ꢄꢂ ꢅ
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UC28023
UC28025
RATING
UNIT
V
Input voltage range,
V
V
V
V
30
C, CC
C, CC
Output current, I
OUT(DC)
OUT
OUT
OUTA, OUTB
OUTA, OUTB
0.5
A
Peak output current, pulsed 0.5 ms I
OUT(pulsed)
2.0
A
Capacitive load, C
200
pF
A
LOAD
INV, NI, RAMP
SS, ILIM/SD
VREF
INV, NI, RAM
SS, ILIM/SD
VREF
−0.3 V to 7 V
Analog inputs
2.0
A
Output current, I
Output current, I
10
REF
CLOCK
SS
CLOCK
SS
−5
CLOCK
Soft-start sink current, I
SINK_SS
5
mA
Output current, I
EAOUT
RT
EAOUT
RT
20
−5
OUT(EA)
Oscillator charging current, I
OSC_CHG
Power Dissipation at T = 25°C (all packages)
1
W
A
Operating junction temperature range, T
−55 to 150
−65 to 150
300
J
Storage temperature, T
stg
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, T
sol
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. All currents are positive into and negative out of the specified terminal.
UC28023
N PACKAGE
UC28023
DW PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLOCK
RT
CT
RAMP
SS
VREF
VCC
OUT
INV
NI
VREF
VCC
OUT
VC
1
2
3
4
5
6
7
8
16
15
14
13
12
EAOUT
CLOCK
RT
VC
PGND
ILIMREF
GND
PGND
CT
11 ILIMREF
10 GND
RAMP
SS
ILIM/SD
9
ILIM/SD
UC28025
UC28025
N PACKAGE
(TOP VIEW)
DW PACKAGE
(TOP VIEW)
1
16
15
14
13
12
11
10
9
INV
VREF
VCC
OUTB
VC
PGND
OUTA
GND
INV
NI
VREF
VCC
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
NI
EAOUT
CLOCK
RT
CT
RAMP
SS
EAOUT
CLOCK
RT
OUTB
VC
PGND
CT
11 OUTA
10 GND
ILIM/SD
RAMP
SS
9
ILIM/SD
2
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
ELECTRICAL CHARACTERISTICS
T
= −40°C to 105°C , T = T
A,
R
= 3.65 kΩ, C = 1 nF, V
CC
= 15 V (unless otherwise noted)
A
J
T
T
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
V
REF
Reference voltage
T = 25°C,
I = 1 mA
REF
5.05
5.10
2
5.15
15
V
J
Line regulation voltage
Load regulation voltage
10 V ≤ V
≤ 30 V
CC
mV
1 mA ≤ I
≤ 10 mA
5
15
REF
(1)
Temperature stability
T
(min)
< T < T
(max)
0.2
0.4 mV/°C
A
(1)
Total output voltage variation
Line, load, temperature
10 Hz < f < 10 kHz
4.95
5.25
V
(1)
Output noise voltage
50
5
µV
mV
mA
(1)
Long term stability voltage
T = 125°C,
J
1000 hours
25
I
Short circuit current
V
REF
= 0 V
−20
360
−50
−100
SS
OSCILLATOR
Initial accuracy
(1)
(1)
f
T = 25°C
J
400
0.2%
5%
440
kHz
kHz
V
OSC
Voltage stability
Temperature stability
10 V ≤ V
CC
≤ 30 V
2.0%
(1)
(1)
T
(min)
< T < T
(max)
A
Total voltage variation
Line, temperature
340
3.9
460
V
High-level clock output voltage
Low-level clock output voltage
4.5
2.3
CLOCK_H
V
2.9
3.0
CLOCK_L
(1)
Ramp peak voltage
V
2.6
0.70
1.6
2.8
RAMP(p)
RAMP(v)
(1)
Ramp valley voltage
V
1.00
1.8
1.25
2.0
(1)
V
Ramp vally-to-peak voltage
RAMP(v-p)
ERROR AMPLIFIER
V
Input offset voltage
Input bias current
Input offset current
Open loop gain
15
3.0
1.0
mV
IN
I
0.6
0.1
95
BIAS
IN
µA
I
A
VOL
1 V ≤ V
OUT
≤ 4 V
60
75
CMRR
PSRR
Common mode rejection ratio
Power supply rejection ratio
Output sink current
1.5 V ≤ V
CM
≤ 5.5 V
95
dB
10 V ≤ V
CC
≤ 30 V
85
110
2.5
−1.3
4.7
0.5
5.5
12
I
V
= 1 V
= 4 V
1.0
−0.5
4.0
0
OUT(sink)
(EAOUT)
(EAOUT)
(EAOUT)
(EAOUT)
mA
V
Output source current
V
IOUT(src)
V
V
High-level output voltage
Low-level output voltage
I
I
= −0.5 mA
= 1 mA
5.0
1.0
OH
OL
(1)
Unity gain bandwidth
3.0
6
MHz
(1)
Slew rate
V/µs
PWM COMPARATOR
I
RAMP bias current
V
= 0 V
−1
90%
45%
−5
µA
BIAS
RAMP
UC28023
UC28025
UC28023
UC28025
80%
40%
Maximum duty cycle
(2)
0%
0%
Minimum duty cycle
EAOUT zero DC threshold
(1)
V
= 0 V
1.10
1.25
50
1.40
100
V
RAMP
t
Delay to output time
ns
DELAY
(1)
(2)
Ensured by design. Not production tested.
Tested as 80% minimum for the oscillator which is the equivalent of 40% for UC28025.
3
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
ELECTRICAL CHARACTERISTICS
T
= −40°C to 105°C , T = T
R
= 3.65 kΩ, C = 1 nF, V
CC
= 15 V (unless otherwise noted)
A
J
A,
T
T
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT-START
I
I
Charge current
Discharge current
V
= 0.5 V
= 1.0 V
3
9
20
µA
CHG
SS
V
SS
1.0
7.5
mA
DISCHG
CURRENT LIMIT/SHUTDOWN
I
Current limit bias current
Offset voltage
0 V < V
(ILIM/SD)
< 4 V
10
15
µA
LIMIT
ILIMIT
UC28023
UC28023
mV
(1)
Common mode range
I
1.00
0.9
1.25
1.1
LIMREF
Current limit threshold voltage UC28025
Shutdown threshold voltage
1.0
1.40
50
V
1.25
1.55
80
(1)
Delay to output time
t
ns
DELAY
OUTPUT
I
I
I
I
= 20 mA
0.25
1.2
13.5
13
0.40
2.2
OUT
OUT
OUT
OUT
V
Low-level output voltage
OL
= 200 mA
= −20 mA
= −200 mA
V
13.0
12
V
OH
High-level output voltage
Collector leakage
V
= 30 V
100
30
500
60
µA
C
(1)
Rise time / Fall time
C
= 1 nF
ns
LOAD
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage
Hysteresis
8.8
0.4
9.2
0.8
9.6
1.2
V
SUPPLY CURRENT
Start-up current
V
V
= 8 V
1.1
25
2.0
35
CC
mA
I
Operating current
= V
RAMP
= V
ILIM
= 0 V = 1 V
INV
CC
(1)
INV
Ensured by design. Not production tested.
THERMAL RESISTANCE
PACKAGE
θ
JA
(°C/W)
θ
JC
(°C/W)
45
(2)
(2)
90
N
(2)
DW
(2)
50−100
27
(2)
Specified θ (junction-to-ambient) is for devices mountied to 5-square-inch FR4 PC board with one ounce copper
JA
where noted. When resistance range is given, lower values are for 5-square-inch aluminum PC board. Test PWB is 0.062
inches thick and typically uses 0.635 mm trace width for power packages and 1.3 mm trace widths for non-power
packages with a 100x100 mil probe land area at the end of each trace.
4
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
FUNCTIONAL BLOCK DIAGRAM
CLOCK
RT
4
5
6
UC28025
13 VC
Toggle F/F
OSCILLATOR
CT
11 OUTA
PWM
Latch
1.25 V
T
RAMP
EAOUT
NI
7
3
R
14 OUTB
12 PGND
S
D
Wide Bandwidth
Error Amplifier
2
1
V
IN
+
9 µA
INV
UC28023
Inhibit
13 VC
14 OUT
12 PGND
SS
8
1 V
(UC28025 Only)
ILIM
Comparator
11
9
ILIMREF
(UC28023
Only)
1 V
Shutdown
Comparator
ILIM/SD
Internal Bias
1.4 V
16 VREF
VCC 15
GND 10
VCC Good
REF GEN
VREF Good
9 V
4 V
UVLO
Output Inhibit
UDG−03048
5
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
UC28023 UC28025
CLOCK
CT
4
6
4
6
O
I
Output of the internal oscillator
Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should
be connected to the device ground using minimal trace length.
EAOUT
GND
3
10
9
3
10
9
O
−
I
Output of the error amplifier for compensation
Analog ground return pin.
ILIM/SD
ILIMREF
INV
Input to the current limit comparator and the shutdown comparator.
Pin to set the current limit threshold externally.
Inverting input to the error amplifier
11
1
−
I
1
I
NI
2
2
I
Non-inverting input to the error amplifier
OUT
14
−
−
O
O
O
−
High current totem pole output of the on-chip drive stage.
High current totem pole output A of the on-chip drive stage.
High current totem pole output B of the on-chip drive stage.
Ground return pin for the output driver stage
OUTA
OUTB
PGND
11
14
12
−
12
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode
operation this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
RAMP
7
7
I
RT
SS
5
8
5
8
I
I
Timing resistor connection pin for oscillator frequency programming
Soft-start input pin which also doubles as the maximum duty cycle clamp.
Power supply pin for the output stage. This pin should be bypassed with a 0.1-µF monolithic
VC
13
15
16
13
15
16
−
−
ceramic low ESL capacitor with minimal trace lengths.
Power supply pin for the device. This pin should be bypassed with a 0.1-µF monolithic ceramic
VCC
VREF
low ESL capacitor with minimal trace lengths
5.1−V reference. For stability, the reference should be bypassed with a 0.1-µF monolithic ceramic
O
low ESL capacitor and minimal trace length to the ground plane.
6
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
+
V
IN
V
5 V
OUT
390 Ω
42 V to 56 V
1 A to 10 A
−
+
4.7 µF
0.8 µH
15 V
15
13
VCC
VC
1N 5820
0.1 µF
16 VREF
OUTB 14
6 µF
1 kΩ
−
5:1
10 kΩ
2
1
NI
OUTA 11
UC28025
ILIM/SD
100 Ω
4.7 µF 12 Ω
1 kΩ
1 kΩ
4.3 kΩ
4.7 µF
150 pF
INV
9
1 nF
22 pF
3.3 kΩ
3
4
5
EAOUT RAMP
7
6
8.2 kΩ
120 pF
10 nF
1 kΩ
CLOCK
CT
C
T
RT
PGND 12
470 pF
GND
10
SS
8
1.5 kΩ
0.1 µF
UDG−03047
Figure 1. Typical Application: 1.5 MHz, 48-V to 5-V DC/DC Push-Pull Converter Using UC28025
7
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
PCB LAYOUT CONSIDERATIONS
High speed circuits demand careful attention to layout and component placement. To assure proper
performance of the UC2802x follow these rules:
1. Use a ground plane.
2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output
pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves this
purpose.
3. Bypass VCC, VC, and VREF. Use 0.1-µF monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1-cm of total lead length for each capacitor between the bypassed pin and the
ground plane.
4. Treat the timing capacitor, C , as a bypass capacitor.
T
ERROR AMPLIFIER
Figure 2 shows a simplified schematic of the UC2802x error amplifier and Figures 3 and 4 show its
characteristics.
5.1 V
VREF
16
3
EAOUT
INV
NI
1
2
200 Ω
UDG−03049
Figure 2. Simplified Error Amplifier Schematic
8
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
GAIN AND PHASE
vs
VOLTAGE
vs
FREQUENCY
TIME
100
80
5
4
3
V
IN
V
OUT
GAIN
60
40
20
0
0
2
PHASE
−20
−90
−40
100
−180
100 M
1
1 k
10 k
100 k
1 M
10 M
0
0.2
t
0.4
0.6
0.8
1.0
− Delay Time− µs
f
− Frequency − Hz
delay
OSC
Figure 3. Open Loop Frequency Response
Figure 4. Unity Gain Slew Rate
CONTROL METHODS
UC2802x
UC2802x
CT
6
CT
C
T
OSCILLATOR
6
7
OSCILLATOR
I
SENSE
RAMP
*
RAMP
7
1.25 V
1.25 V
*
C
T
R
SENSE
From
Error Amplifier
From
Error Amplifier
UDG−03050
* A small filter may be required to supress switch noise.
UDG−03050
Figure 5. Voltage Mode Control
Figure 6. Peak Current Mode Control
9
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
OSCILLATOR
DEAD TIME
vs
TIMING CAPACITANCE
10.0
UC2802x
3 kΩ ≤ R ≤ 100 kΩ
RT
CT
T
I
R
5
6
4.70
3 V
I
I
C = R
2.20
1.00
0.47
0.22
5.1 V
CLOCK
4
Blanking
0.10
T
D
400 µA
0.047
0.047
1.0
2.2
4.7
10.0
22.0
47
100
UDG−03052
C
− Timing Capacitance − nF
T
Figure 8.
Figure 7. Oscillator Circuit
DEAD TIME
vs
TIMING RESISTANCE
vs
FREQUENCY
FREQUENCY
160
140
120
100
80
100 k
4.7 nF
2.2 nF
1 nF
R
= 1 nF
T
470 pF
10 k
100 nF
47 nF
R
= 470 pF
T
22 nF
10 nF
1 k
100
10 k
100 k
− Frequency − Hz
1 M
1 k
f
10 k
100 k
1 M
f
− Frequency − Hz
OSC
OSC
Figure 10.
Figure 9. Oscillator Circuit
10
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
SYNCHRONIZATION
Figure 11 shows a generalized synchronization. Figure 12 shows a synchronozed operation of two units in close
proximity.
UC2802x
(Master)
UC2802x
(Slave)
VREF 16
R
T
1.15 Ω
10 µF
5
6
RT
CT
2N222
CLOCK
RT
4
5
6
0.1 µF
43 Ω
R
T
24 Ω
0.1 µF
0.1 µF
43 Ω
43 Ω
C
C
T
T
CT
To other
slaves
24 Ω
Local
Ramp
Local
Ramp
470 Ω
UDG−03050
Figure 11. Generalized Synchronization
UC2802x
(Master)
UC2802x
(Slave)
CLOCK
4
5
6
4
CLOCK
16 VREF
R
T
RT
5
6
RT
CT
Local
Ramp
CT
C
T
UDG−03050
Figure 12. Synchronization of Two Units In Close
Proximity
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
FEEDFORWARD CIRCUIT
VIN
UC2802x
RFF
7
4
RAMP
CFF
CLOCK
6
5
CT
RT
UDG−03050
Figure 13. Feedforward Technique for Off-Line Voltage-Mode Applications
CONSTANT VOLT-SECOND CLAMP CIRCUIT
The circuit for the UC28023 shown in Figure 14 describes achievement a constant volt-second product clamp
over varying input voltages. The ramp generator components, R and C are chosen so that the ramp at Pin
T
R
9 (ILIM/SD) crosses the 1-V threshold at the same time the desired maximum volt-second product is reached.
The delay through the functional inverter block must be such that the ramp capacitor can be completely
discharged during the minimum deadtime.
UC28023
VIN
OUT
RT
14
ILIM/SD
9
CR
UDG−03050
Figure 14. Achieving Constant Volt-Second Product Clamp with the UC28023
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
The circuit for the UC28025 shown in Figure 15 describes achievement a constant volt-second product clamp
over varying input voltages. The ramp generator components, R and C are chosen so that the ramp at Pin
T
R
9 (ILIM/SD) crosses the 1-V threshold at the same time the desired maximum volt-second product is reached.
The delay through the functional inverter block must be such that the ramp capacitor can be completely
discharged during the minimum deadtime.
UC28025
VIN
OUTB
RT
14
ILIM/SD
9
OUTA
11
CR
UDG−03050
Figure 15. Achieving Constant Volt-Second Product Clamp with the UC28025
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
OUTPUTS
UC28023 has one output and UC28025 has dual alternating outputs.
SATURATION VOLTAGE
vs
OUTPUT CURRENT
UC2802x
3
15 VCC
13 VC
2
Source
OUTx
1
12 PWRGND
10 GND
Sink
0
0
0.25
0.50
OUT
0.75
1.00
1.25
1.50
I
− Output Current − A
Figure 16. Simplified Schematic
Figure 17.
RISE/FALL TIME
vs
RISE/FALL TIME
vs
OUTPUT VOLTAGE AND LOAD CURRENT
OUTPUT VOLTAGE AND LOAD CURRENT
0.2
0
0.2
0
C
=10 nF
C
=1 nF
LOAD
LOAD
15
−0.2
15
10
−0.2
10
5
0
5
0
0
100
200
300
400
500
0
40
80
(t
120
160
200
t
(t
) − Time − ns
t
) − Time − ns
RISE FALL
RISE FALL
Figure 18.
Figure 19.
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SLUS557B − MARCH 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
Open Loop Laboratory Test Fixture
The following test fixture is useful for exercising many of the UC28025’s functions and measuring their
specifications. As with any wideband circuit, careful ground and by-pass procedures should be followed. The
use of a ground plane is highly recommended.
UC28025
15 V
0.1 µF
4
5
6
CLOCK
RT
VCC 15
VC 13
R
T
3.65 kΩ
T
15 V
10 uF
OSCILLATOR
C
1.0 nF
10 µF
0.1 µF
CT
200 Ω
OUTA 11
OUTB 14
7
3
RAMP
EAOUT
27 kΩ
50 Ω
1N5820
68 kΩ
ERROR
AMPLIFIER
1N5820
4.7 kΩ
4.7 kΩ
10 kΩ
27 kΩ
2
1
8
NI
PGND 12
GND 10
22 kΩ
INV
SS
0.1 µF
10 µF
VREF 16
10 kΩ
9
ILIM/SD
3.3 kΩ
UDG−03051
Figure 20. Laboratory Test Fixture
References
1. 1.5-MHz Current Mode IC Controlled 50−Watt Power Supply, Texas Instruments Application Note Literature
No. SLUA053.
2. The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, Texas Instruments
Application Note Literature No. SLUA125.
15
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