UC2825AQDWRQ1 [TI]
HIGH-SPEED PWM CONTROLLER;
| 型号： | UC2825AQDWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED PWM CONTROLLER 开关 光电二极管 |
| 文件： | 总14页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC2825A-Q1
www.ti.com
SLUS781–SEPTEMBER 2007
HIGH-SPEED PWM CONTROLLER
1
FEATURES
DESCRIPTION
•
Qualified for Automotive Applications
•
•
Improved Version of the UC3825 PWM
The UC2825A pulse-width modulation (PWM)
controller is an improved versions of the standard
UC3825. Performance enhancements have been
made to several of the circuit blocks. Error amplifier
gain bandwidth product is 12 MHz, while input offset
voltage is 2 mV. Current limit threshold is specified to
a tolerance of 5%. Oscillator discharge current is
specified at 10 mA for accurate dead-time control.
Frequency accuracy is improved to 6%. Startup
supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to
actively sink current during undervoltage lockout
(UVLO) at no expense to the startup current
specification. In addition, each output is capable of
2-A peak currents during transitions.
Compatible With Voltage-Mode or
Current-Mode Control Methods
•
Practical Operation at Switching Frequencies
to 1 MHz
•
•
50-ns Propagation Delay to Output
High-Current Dual Totem-Pole Outputs:
2 A (Peak)
•
•
•
•
Trimmed Oscillator Discharge Current
Low 100-μA Startup Current
Pulse-by-Pulse Current-Limiting Comparator
Latched Overcurrent Comparator With
Full-Cycle Restart
BLOCK DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
UC2825A-Q1
www.ti.com
SLUS781–SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Functional improvements have also been implemented. The shutdown comparator is now a high-speed
overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full
discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the
low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that
the fault frequency does not exceed the designed soft start period. The CLOCK pin has become CLK/LEB. This
pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for
easier interfacing.
The UC2825A has dual alternating outputs and the same pin configuration of the UC3825. "A" version parts have
UVLO thresholds identical to the original UC3825.
See the application report, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers
(SLUA125) for detailed technical and application information.
ORDERING INFORMATION(1)
MAXIMUM
DUTY CYCLE
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
TJ
UVLO
PACKAGE(2)
Reel of 2000
–40°C to 125°C
<50%
9.2 V/8.4 V
SOIC – DW
UC2825AQDWRQ1
UC2825AQDW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
PIN ASSIGNMENTS
DW PACKAGE
(TOP VIEW)
INV
NI
VREF
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
EAOUT
CLK/LEB
RT
OUTB
VC
PGND
CT
11 OUTA
10
9
RAMP
SS
GND
ILIM
2
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UC2825A-Q1
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SLUS781–SEPTEMBER 2007
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CLK/LEB
4
O
I
Output of the internal oscillator
Timing capacitor connection for oscillator frequency programming. The timing capacitor should be
connected to the device ground using minimal trace length.
CT
6
EAOUT
GND
ILIM
3
10
9
O
Output of the error amplifier for compensation
Analog ground return
I
I
Input to the current limit comparator
INV
1
Inverting input to the error amplifier
NI
2
I
Noninverting input to the error amplifier
High-current totem-pole output A of the on-chip drive stage
High-current totem-pole output B of the on-chip drive stage
Ground return for the output driver stage
OUTA
OUTB
PGND
11
14
12
O
O
Noninverting input to the PWM comparator with 1.25-V internal input offset. In voltage-mode operation,
this serves as the input voltage feed-forward function by using the CT ramp. In peak current-mode
operation, this serves as the slope compensation input.
RAMP
7
I
RT
SS
5
8
I
I
Timing resistor connection for oscillator frequency programming
Soft-start input and the maximum duty cycle clamp
Power supply for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic low
ESL capacitor with minimal trace lengths.
VC
13
15
16
Power supply for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low ESL
capacitor with minimal trace lengths
VCC
VREF
5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic low
ESL capacitor and minimal trace length to the ground plane.
O
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range unless otherwise noted
VALUE
22 V
VIN
IO
Supply voltage
VC, VCC
OUTA, OUTB
OUTA, OUTB
INV, NI, RAMP
ILIM, SS
PGND
Source or sink current, dc
Source or sink current, pulse (0.5 μs)
0.5 A
IO
2.2 A
–0.3 V to 7 V
–0.3 V to 6 V
±0.2 V
Analog inputs
Power ground
ICLK
IO(EA)
ISS
Clock output current
CLK/LEB
EAOUT
–5 mA
Error amplifier output current
Soft-start sink current
5 mA
SS
20 mA
IOSC
TJ
Oscillator charging current
RT
–5 mA
Operating virtual junction temperature range
Storage temperature range
Lead temperature 1,6 mm (1/16 in) from case for 10 s
–55°C to 150°C
–65°C to 150°C
300°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2007, Texas Instruments Incorporated
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SLUS781–SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference, VREF
VO
Ouput voltage
Line regulation
TJ = 25°C, IO = 1 mA
5.05
5.1
2
5.15
V
12 V ≤ VCC ≤ 20 V
15
20
mV
mV
V
Load regulation
1 mA ≤ IO ≤ 10 mA
Line, load, temperature
T(min) < TJ < T(max)
5
Total output variation
Temperature stability
5.03
5.17
(1)
0.2
50
5
0.4 mV/°C
μVRMS
(1)
Output noise voltage
10 Hz < f < 10 kHz
TJ = 125°C, 1000 hours
(1)
Long term stability
25
90
mV
30
30
60
Short circuit current
VREF = 0 V
mA
TJ = 125°C
110
Oscillator
TJ = 25°C
375
0.9
400
1
425
1.1
450
1.15
1
kHz
MHz
kHz
MHz
%
(1)
fOSC
Initial accuracy
RT = 6.6 kΩ, CT = 220 pF, TJ = 25°C
Line, temperature
350
0.85
(1)
Total variation
RT = 6.6 kΩ, CT = 220 pF
12 V < VCC < 20 V
Voltage stability
(1)
Temperature stability
High-level output voltage, clock
Low-level output voltage, clock
Ramp peak
T(min) < TJ < T(max)
±5
4
%
3.7
V
0
0.2
3
V
2.6
0.7
1.6
1.55
9
2.8
1
V
Ramp valley
1.25
2
V
1.8
Ramp valley to peak
V
TJ = –40°C
2
10
11
11
IOSC
Oscillator discharge current
RT = Open, VCT = 2 V
mA
TJ = 125°C
8
Error Amplifier
Input offset voltage
2
0.6
0.1
95
10
3
mV
μA
μA
dB
Input bias current
Input offset current
1
Open loop gain
1 V < VO < 4 V
1.5 V < VCM < 5.5 V
12 V < VCC < 20 V
VEAOUT = 1 V
60
75
85
1
CMRR
PSRR
IO(sink)
IO(src)
Common-mode rejection ratio
Power-supply rejection ratio
Output sink current
95
dB
110
2.5
–1.3
4.7
0.5
12
dB
mA
mA
V
Output source current
High-level output voltage
Low-level output voltage
Gain bandwidth product
VEAOUT = 4 V
–0.5
4.5
0
IEAOUT = –0.5 mA
IEAOUT = –1 mA
f = 200 kHz
5
1
V
6
MHz
V/μs
(1)
Slew rate
6
9
(1) Specified by design
4
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UC2825A-Q1
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SLUS781–SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM Comparator
IBIAS
Bias current, RAMP
VRAMP = 0 V
–1
–8
0
μA
%
Minimum duty cycle
Maximum duty cycle
85
300
8
%
tLEB
Leading edge blanking time
Leading edge blanking resistance
Zero dc threshold voltage, EAOUT
Delay-to-output time(2)
RLEB = 2 kΩ, CLEB = 470 pF
VCLK/LEB = 3 V
375
10
450
12
ns
kΩ
V
RLEB
VZDC
tDELAY
VRAMP = 0 V
1.10
1.25
50
1.4
80
VEAOUT = 2.1 V, VILIM = 0 V to 2 V step
ns
Current Limit / Start Sequence / Fault
ISS
Soft-start charge current
Full soft-start threshold voltage
Restart discharge current
Restart threshold voltage
ILIM bias current
VSS= 2.5 V
8
4.3
14
5
20
μA
V
VSS
IDSCH
ISS
VSS= 2.5 V
100
250
0.3
350
0.5
μA
V
IBIAS
ICL
VILIM = 0 V to 2 V step
15
A
Current limit threshold voltage
Overcurrent threshold voltage
Delay-to-output time, ILIM(1)
0.95
1.14
1
1.2
50
1.05
1.26
80
V
td
VILIM = 0 V to 2 V step
ns
Output
IOUT = 20 mA
IOUT = 200 mA
IOUT = –20 mA
IOUT = –200 mA
CL = 1 nF
0.25
1.2
1.9
2
0.4
2.2
2.9
3
Low-level output saturation voltage
V
High-level output saturation voltage
Rise/fall time(2)
V
tr, tf
20
45
ns
Undervoltage Lockout (UVLO)
Start threshold voltage
UVLO hysteresis
8.4
0.4
9.2
0.8
9.6
1.2
V
V
Supply Current
Isu
Startup current
Input current
VC = VCC = VTH = –0.5 V
100
28
300
36
μA
ICC
mA
(2) Specified by design
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SLUS781–SEPTEMBER 2007
APPLICATION INFORMATION
The oscillator is a sawtooth. The rising edge is governed by a current controlled by the RT pin and value of
capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for the outputs. Selection of RT
should be done first, based on desired maximum duty cycle. CT can then be chosen based on the desired
frequency (RT) and DMAX. The design equations are:
ǒ1.6 DMAXǓ
3 V
R +
C +
T
T
10 mA ǒ1 * DMAXǓ
ǒR fǓ
T
(
)
(1)
Recommended values for RT range from 1 kΩ to 100 kΩ. Control of DMAX less than 70% is not recommended.
IR
RT
3 V
IC = IR
CT
CLK
ID = 10 mA
LEB
R
VTH
C
Figure 1. Oscillator
MAXIMUM DUTY CYCLE
vs
TIMING RESISTANCE
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
100
95
10 M
90
85
80
1 M
100 k
10 k
75
70
1 k
10 k
100 k
10 k
1 k
100 k
W
R - Timing Resistance -
T
RT - Timing Resistance - W
Figure 2.
Figure 3.
6
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UC2825A-Q1
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SLUS781–SEPTEMBER 2007
Leading Edge Blanking (LEB)
The UC2825A performs fixed-frequency PWM control. The outputs are alternately controlled. During every other
cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying in duty cycle from
0% to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is
controlled by the PWM comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates
the pulse. LEB causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse.
This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not
require any filtering as result of LEB.
To program a LEB period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal
10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy, an
external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of
2.4%. The design equation is:
ǒ Ǔ
+ 0.5 R ø 10 kW C
t
LEB
(2)
Values of R less than 2 kΩ should not be used.
LEB is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold, the
pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent
faults without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven
low. For this reason, some noise filtering may be required on the ILIM pin.
CT
CLK/LEB
LEB
Ramp Input
Blanked Ramp
to PWM
Figure 4. Leading Edge Blanking Operational Waveforms
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SLUS781–SEPTEMBER 2007
UVLO, Soft Start, and Fault Management
Soft start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error
amplifier output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output
follows until closed loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start capacitor is
then discharged by a 250-μA current sink. No more output pulses are allowed until the soft-start capacitor is fully
discharged and ILIM is below 1.2 V. At this time, the fault latch resets and the chip executes a soft start.
Should the fault latch get set during soft start, the outputs are immediately terminated, but the soft-start capacitor
does not discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous
fault conditions.
1.2 V
FAULT
5.0 V
VSS
1.2 V
0.2 V
ON
PWM
OFF
Figure 5. Soft-Start and Fault Waveforms
Active-Low Outputs During UVLO
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to
operate.
UDG-95106
UDG-95108
Figure 6. Output Voltage vs Output Current
Figure 7. Output Voltage and Current During UVLO
8
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SLUS781–SEPTEMBER 2007
Control Methods
Current Mode
Voltage Mode
UDG-95110
UDG-95109
.
Figure 8. Control Methods
Synchronization
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the
free-running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The
pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge
of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no
longer accepts an incoming synchronizing signal.
UDG-95113
Figure 9. General Oscillator Synchronization
Figure 10. Two Unit Interface
UDG-95112
Figure 11. Operational Waveforms
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High-Current Outputs
Each totem pole output can deliver a 2-A peak current into a capacitive load. The output can slew a 1000-pF
capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground (PGND) pins help
decouple the device's analog circuitry from the high-power gate drive noise. The use of 3-A Schottky diodes
(1N5120, USD245, or equivalent) (see Figure 13) from each output to both VC and PGND are recommended.
The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive load,
typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. Do not
use standard silicon diodes.
Although they are single-ended devices, two output drivers are available on the UC2825A. These can be
paralleled by the use of a 0.5-Ω (noninductive) resistor connected in series with each output for a combined peak
current of 4 A.
VC
VC
1 nF
10 µF
D1
OUT
6.8 W
D2
PGND
GND
D1, D2 = 1N5820
Figure 12. Power MOSFET Drive Circuit
Ground Planes
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct
operation of the chip. A ground plane must be employed. A unique section of the ground plane must be
designated for high di/dt currents associated with the output stages. This point is the power ground to which the
PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a
single point, although this is not necessary if the high di/dt paths are well understood and accounted for. VCC
should be bypassed directly to power ground with a good high-frequency capacitor. The sources of the power
MOSFET should connect to power ground, as should the return connection for input power to the system and the
bulk input capacitor. The output should be clamped with a high-current Schottky diode to both VCC and PGND.
Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high-frequency
capacitor. Low ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog
circuitry should, likewise, be bypassed to the signal ground plane.
10
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UDG-95115
Figure 13. Ground Planes Diagram
Open-Loop Test Circuit
This test fixture is useful for exercising many functions of this device family and measuring their specifications.
As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground
plane is highly recommended.
UC2825A
Figure 14. Open-Loop Test Circuit Schematic
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
UC2825AQDWRQ1
ACTIVE
SOIC
DW
16
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC2825A-Q1 :
Catalog: UC2825A
Enhanced Product: UC2825A-EP
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
•
Addendum-Page 1
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dataconverter.ti.com
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DLP® Products
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Computers and Peripherals
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www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
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Interface
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interface.ti.com
logic.ti.com
Medical
Security
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Power Mgmt
power.ti.com
Transportation and
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Microcontrollers
RFID
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprf
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