UC2834QG3 [TI]

High Efficiency Linear Regulator 20-PLCC -40 to 85;


型号：	UC2834QG3
厂家：	TEXAS INSTRUMENTS
描述：	High Efficiency Linear Regulator 20-PLCC -40 to 85
文件：	总12页 (文件大小：1168K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UC1834

UC2834

UC3834

High Efficiency Linear Regulator

FEATURES

DESCRIPTION

•

Minimum VIN - VOUT Less Than

0.5V At 5A Load With External

Pass Device

The UC1834 family of integrated circuits is optimized for the design of low

input-output differential linear regulators. A high gain amplifier and 200mA

sink or source drive outputs facilitate high output current designs which use

an external pass device. With both positive and negative precision refer-

ences, either polarity of regulator can be implemented. A current sense am-

plifier with a low, adjustable, threshold can be used to sense and limit

currents in either the positive or negative supply lines.

•

Equally Usable For Either Positive

or Negative Regulator Design

Adjustable Low Threshold Current

Sense Amplifier

In addition, this series of parts has a fault monitoring circuit which senses

both under and over-voltage fault conditions. After a user defined delay for

transient rejection, this circuitry provides a fault alert output for either fault

condition. In the over-voltage case, a 100mA crowbar output is activated.

An over-voltage latch will maintain the crowbar output and can be used to

shutdown the driver outputs. System control to the device can be accom-

modated at a single input which will act as both a supply reset and remote

shutdown terminal. These die are protected against excessive power dissi-

pation by an internal thermal shutdown function.

Under And Over-Voltage Fault Alert

With Programmable Delay

Over-Voltage Fault Latch With

100mA Crowbar Drive Output

BLOCK DIAGRAM

6/94

UC1834

UC2834

UC3834

ABSOLUTE MAXIMUM RATINGS (Note 1)

Input Supply Voltage, V_IN+ . . . . . . . . . . . . . . . . . . . . . . . . . 40V

Driver Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA

Driver Source to Sink Voltage . . . . . . . . . . . . . . . . . . . . . . . 40V

Crowbar Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200mA

+1.5V Reference Output Current . . . . . . . . . . . . . . . . . . −10mA

Fault Alert Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V

Fault Alert Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA

Error Amplifier Inputs . . . . . . . . . . . . . . . . . . . . . . −0.5V to 35V

Current Sense Inputs . . . . . . . . . . . . . . . . . . . . . . −0.5V to 40V

O.V. Latch Output Voltage . . . . . . . . . . . . . . . . . . −0.5V to 40V

O.V. Latch Output Current . . . . . . . . . . . . . . . . . . . . . . . . 15mA

Power Dissipation at TA = 25°C . . . . . . . . . . . . . . . . . . 1000mW

Power Dissipation at TC = 25°C. . . . . . . . . . . . . . . . . . 2000mW

Operating Junction Temperature. . . . . . . . . . −55°C to +150°C

Storage Temperature. . . . . . . . . . . . . . . . . . . −65°C to +150°C

Lead Temperature (soldering, 10 seconds). . . . . . . . . . . 300°C

Note 1: Voltages are reference to VIN−, Pin 5.

Currents are positive into, negative out of the specified

terminals.

Consult Packaging section of Databook for thermal

limitations and considerations of package.

CONNECTION DIAGRAMS

PLCC-20, LCC-20 (TOP VIEW)

Q, L Packages

DIL-16, SOIC-16 (TOP VIEW)

J or N Package, DW Package

PACKAGE PIN FUNCTION

FUNCTION

N/C

VIN +

−2.0V REF

+1.5V REF

Threshold Adjust

N/C

VIN−

Sense−

Sense+

N.Inv. Input

N/C

Inv. Input

Fault Alert

Fault Delay

Driver Sink

N/C

Driver Source

Compensation/ Shutdown 18

O.V. Latch Output/Reset

Crowbar Gate

UC1834

UC2834

UC3834

ELECTRICAL CHARACTERISTICS:

Unless otherwise stated, these specifications apply for TA=−55°C to +125°C

for the UC1834, −40°C to +85°C for the UC2834, and 0°C to +70°C for the

UC3834. VIN+ = 15V, VIN− = 0V, TA = TJ.

UC1834

UC2834

UC3834

UNITS

PARAMETER

TEST CONDITIONS

MIN

TYP MAX MIN

TYP MAX

Turn-on Characteristics

Standby Supply Current

+1.5 Volt Reference

5.5

1.5

Output Voltage

TJ = 25°C

1.485 1.5 1.515 1.47

1.53

1.545

TJ(MIN ≤ TJ ≤ TJ(MAX)

1.47

1.53 1.455

)

Line Regulation

VIN+ = 5 to 35V

IOUT = 0 to 2mA

Load Regulation

-2.0 Volt Reference (Note 2)

Output Voltage (Referenced TJ = 25°C

−2.04

−2.06

−2

−1.96 −2.06

−1.94 −2.08

−2

−1.94

−1.92

to VIN )

TJ(MIN) ≤ TJ ≤ TJ(MAX)

Line Regulation

VIN+ = 5 to 35V

1.5

2.3

1.5

2.3

Output Impedance

Error Amplifier Section

Input Offset Voltage

Input Bias Current

Input Offset Current

kΩ

VCM = 1.5V

−4

−8

µA

−1

0.1

−1

0.1

Small Signal Open Loop Gain Output @ Pin 14, Pin 12 = VIN+

Pin 13, 20Ω to VIN−

CMRR

VCM = 0.5 to 33V, V_IN+ = 35V

VIN+ = 5 to 35V, VCM = 1.5V

PSRR

100

Driver Section

Maximum Output Current

Saturation Voltage

Output Leakage Current

200

0.4

350

0.5

0.1

200

350

0.5

0.1

IOUT = 100mA

1.2

1.5

Pin 12 = 35V, Pin 13 = VIN−, Pin 14 = VIN−

µA

Shutdown Input Voltage

at Pin 14

IOUT ≤ 100µA, Pin 13 = VIN−, Pin 12 =

VIN+

0.4

Shutdown Input Current

at Pin 14

Pin 14 = VIN−, Pin 12 = VIN+

IOUT ≤ 100µA, Pin 13 = VIN−

−100 −150

µA

Thermal Shutdown (Note 3)

165

°C

Fault Amplifier Section

Under- and Over-Voltage

Fault Threshold

VCM = 1.5V, @ E/A Inputs

120

150

180

110

150

190

Common Mode Sensitivity

Supply Sensitivity

VIN+ = 35V, VCM = 1.5 to 33V

VCM = 1.5V, VIN+ = 5 to 35V

−0.4 −0.8

−0.5 −1.0

−0.4 −1.0

−0.5 −1.2

%/v

%/V

Fault Delay

60 ms/µF

Fault Alert Output Current

Fault Alert Saturation Voltage IOUT = 1mA

O.V. Latch Output Current

0.2

0.5

0.2

0.5

O.V. Latch Saturation Voltage IOUT = 1mA

1.0

0.4

1.3

0.6

1.0

0.4

1.3

0.6

O.V. Latch Output Reset

Voltage

0.3

Crowbar Gate Current

−100 −175

−0.5

−100 −175

−0.5

Crowbar Gate Leakage

Current

VIN+ = 35V, Pin 16 = VIN−

−50

µA

Note 2: When using both the 1.5V and −2.0V references the current out of pin 3 should be balanced by an equivalent current into

Pin 2. The −2.0V output will change −2.3mV per µA of imbalance.

Note 3: Thermal shutdown turns off the driver. If Pin 15 (O.V. Latch Output) is tied to Pin 14 (Compensation/Shutdown) the

O.V. Latch will be reset.

UC1834

UC2834

UC3834

Unless otherwise stated, these specifications apply for TA=−55°C to +125°C

for the UC1834, −40°C to +85°C for the UC2834, and 0°C to +70°C for the

UC3834. VIN+ = 15V, VIN− = 0V. TA = TJ

ELECTRICAL CHARACTERISTICS:

UC1834

UC2834

UC3834

UNITS

PARAMETER

TEST CONDITIONS

MIN

TYP MAX MIN

TYP MAX

Current Sense Amplifier Section

Threshold Voltage

Pin 4 Open, VCM = VIN+ or VIN−

Pin 4 = 0.5V, V_CM= VIN+ or VIN−

130

150

170

120

150

180

Threshold Supply Sensitivity Pin 4 Open, VCM = VIN−, VIN+ = 5 to 35V

−0.1 −0.3

−0.1 −0.5

%/V

µA

Adj. Input Current

Pin 4 = 0.5V

VCM = VIN+

VCM = VIN−

−2

−10

−2

−10

Sense Input Bias Current

100

200

100

200

µA

−100 −200

Current Sense Threshold Adjustment

Current Limiting Knee Characteristics

Differential Voltage at Current Sense

Inputs - mV (reference to sense − input)

Error Amplifier Gain and Phase

Frequency Response

Current Sense Amplifier Gain and Phase

Frequency Response

UC1834

UC2834

UC3834

APPLICATION INFORMATION

Foldback Current Limiting

Both the current sense and error amplifiers on the UC1834 The crowbar output on the UC1834 is activated following a

are transconductance type amplifiers. As a result, their volt- sustained over-voltage condition. The crowbar output remains

age gain is a direct function of the load impedance at their high as long as the fault condition persists, or, as long as the

shared output pin, Pin 14. Their small signal voltage gain as over-voltage latch is set. The latch is set with an over-voltage

a function of load and frequency is nominally given by;

fault if the voltage at Pin 15 is above the latch reset threshold,

typically 0.4V. When the latch is set, its Q− output will pull Pin

15 low through a series diode. As long as a nominal pull-up

load exists, the series diode prevents Q− from pulling Pin 15

below the reset threshold. However, Pin 15 is pulled low

enough to disable the driver outputs if Pins 15 and 14 are

tied together. With Pin 15 and 14 common, the regulator

will latch off in response to an over-voltage fault. If the

fault condition is cleared and Pins 14 and 15 are momen-

tarily pulled below the latch reset threshold, the driver out-

puts are re-enabled.

ZL (f)

70Ω

AV E ⁄ A =

and AV C. S. ⁄ A =

700Ω

for: f ≤ 500kHz and |ZL(f)| ≤ 1 MΩ

Where:

AV=Small Signal Voltage Gain to pin 14.

ZL(f) = Load Impedance at Pin 14.

The UC1834 fault delay circuitry prevents the fault outputs

from responding to transient fault conditions. The delay reset

latch insures that the full, user defined, delay passes before an

over-voltage fault response occurs. This prevents unnecessary

crowbar, or latched-off conditions, from occurring following

sharp under-voltage to over-voltage transients.

Setting the Threshold Adjust Voltage (VADJ)

UC1834

UC2834

UC3834

TYPICAL APPLICATIONS

5-10 Amp Positive Regulator

5-10 Amp Negative Regulator

UNITRODE CORPORATION

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

5962-87742012A

ACTIVE

LCCC

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

87742012A

UC1834L/

883B

5962-8774201EA

5962-8774201V2A

ACTIVE

CDIP

TBD

A42

N / A for Pkg Type

-55 to 125

5962-8774201EA

UC1834J/883B

LCCC

POST-PLATE

5962-

8774201V2A

UC1834L

QMLV

5962-8774201VEA

UC1834J

ACTIVE

CDIP

TBD

A42

N / A for Pkg Type

5962-8774201VE

UC1834JQMLV

-55 to 125

UC1834J

UC1834J/81025

UC1834J883B

OBSOLETE

ACTIVE

CDIP

TBD

Call TI

A42

Call TI

-55 to 125

N / A for Pkg Type

5962-8774201EA

UC1834J/883B

UC1834L

ACTIVE

LCCC

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

UC1834L

UC1834L883B

5962-

87742012A

UC1834L/

883B

UC2834DW

UC2834DWG4

UC2834DWTR

UC2834DWTRG4

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 85

UC2834DW

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UC2834J

UC2834N

ACTIVE

CDIP

PDIP

TBD

A42

N / A for Pkg Type

-40 to 85

UC2834J

UC2834N

Green (RoHS

& no Sb/Br)

CU NIPDAU

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

UC2834NG4

UC2834Q

ACTIVE

PDIP

TBD

Call TI

CU SN

Call TI

-40 to 85

ACTIVE

PLCC

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

UC2834Q

UC2834QG3

PLCC

Green (RoHS

& no Sb/Br)

CU SN

Level-2-260C-1 YEAR

-40 to 85

UC2834Q

UC2834QTR

UC2834QTRG3

UC3834DW

OBSOLETE

ACTIVE

PLCC

SOIC

TBD

Call TI

-40 to 85

0 to 70

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

UC3834DW

UC3834N

UC3834DWG4

UC3834N

ACTIVE

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

N / A for Pkg Type

0 to 70

Green (RoHS

& no Sb/Br)

UC3834NG4

Green (RoHS

& no Sb/Br)

UC3834N

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

17-May-2014

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1834, UC1834-SP, UC2834, UC2834M, UC3834 :

Catalog: UC3834, UC1834, UC2834

•

Military: UC2834M, UC1834

•

Space: UC1834-SP

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

8-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UC2834DWTR

SOIC

2000

330.0

16.4

10.75 10.7

2.7

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-May-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

UC2834DWTR

2000

Pack Materials-Page 2

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UC2834QG3 [TI]

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