UC2843ADWG4 [TI]
1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO16, GREEN, PLASTIC, SOIC-16;
| 型号： | UC2843ADWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO16, GREEN, PLASTIC, SOIC-16 开关 光电二极管 |
| 文件： | 总28页 (文件大小：768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
www.ti.com
SLUS223C–APRIL 1997–REVISED JUNE 2007
CURRENT MODE PWM CONTROLLER
FEATURES
DESCRIPTION
•
Optimized For Off-line and DC-to-DC
Converters
The UC1842/3/4/5 family of control devices provides
the necessary features to implement off-line or
dc-to-dc fixed frequency current mode control
•
•
•
•
•
•
•
•
•
•
Low Start-Up Current (<1 mA)
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Under-Voltage Lockout With Hysteresis
Double Pulse Suppression
schemes with
a minimal external parts count.
Internally implemented circuits include under-voltage
lockout featuring start up current less than 1 mA, a
precision reference trimmed for accuracy at the error
amp input, logic to insure latched operation, a PWM
comparator which also provides current limit control,
and a totem pole output stage designed to source or
sink high peak current. The output stage, suitable for
driving N-Channel MOSFETs, is low in the off state.
High Current Totem Pole Output
Internally Trimmed Bandgap Reference
500-kHz Operation
Differences between members of this family are the
under-voltage lockout thresholds and maximum duty
cycle ranges. The UC1842 and UC1844 have UVLO
thresholds of 16 VON and 10 VOFF, ideally suited to
off-line applications. The corresponding thresholds
for the UC1843 and UC1845 are 8.4 V and 7.6 V.
The UC1842 and UC1843 can operate to duty cycles
approaching 100%. A range of zero to 50% is
obtained by the UC1844 and UC1845 by the addition
of an internal toggle flip flop which blanks the output
off every other clock cycle.
Low RO Error Amp
BLOCK DIAGRAM
V
cc
7 12
UVLO
34 V
5 V
REF
S/R
8 14
5
4
9
7
GROUND
V
REF
5 V
50 mA
2.50 V
Internal
BIAS
VREF
Good
Logic
7
11
V
C
OSC
R /C
T
T
6
10
T
Error
Amp
OUTPUT
S
2R
R
5
8
PWM
LATCH
2
1
3
3
1
5
V
FB
R
POWER
GROUND
1 V
CURRENT
SENSE
COMP
COMPARATOR
CURRENT
SENSE
Note 1:
Note 2:
A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number.
Toggle flip flop used only in 1844 and 1845.
A/B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2007, Texas Instruments Incorporated
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
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SLUS223C–APRIL 1997–REVISED JUNE 2007
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
Low impedance source
30 V
Self Limiting
±1 A
Supply voltage
ICC < 30 mA
Output current
Output energy (capacitive load)
Analog inputs (Pins 2, 3)
Error amp output sink current
5 µJ
–0.3 V to 6.3 V
10 mA
TA≤ 25°C (DIL-8)
1 W
Power dissipation
TA≤ 25°C (SOIC-14)
TA≤ 25°C (SOIC-8)
725 mW
650 mW
Storage temperature range
Junction temperature range
–65°C to 150°C
–55°C to 150°C
300°C
Lead temperature (soldering, 10 seconds)
(1) All voltages are with respect to Pin 5. All currents are positive into the specified terminal. Consult Packaging Section of Databook for
thermal limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-8, SOIC-8
N or J PACKAGE, D8 PACKAGE
PLCC-20
Q PACKAGE
(TOP VIEW)
(TOP VIEW)
COMP
V
V
1
2
3
4
8
7
6
5
REF
V
FB
SENSE
CC
I
OUTPUT
GROUND
R /C
T
T
3
2 1 20 19
V
V
NC
18
17
16
15
14
4
5
6
7
8
CC
SOIC-14, CFP-14
D or W PACKAGE
(TOP VIEW)
V
FB
C
NC
OUTPUT
NC
NC
I
SENSE
1
2
3
4
5
6
7
14
13
12
11
10
9
V
REF
COMP
NC
NC
NC
V
9 10 11 12 13
V
FB
CC
V
C
NC
OUTPUT
GROUND
PWR GND
I
SENSE
NC
8
R /C
T
T
NC − No internal connection
2
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SLUS223C–APRIL 1997–REVISED JUNE 2007
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PACKAGE
θJC
28(1)
25
θJA
DIL-8
J
N
125-160
110(2)
SOIC-8
D8
D14
W
42
84-160(2)
50-120(2)
175.4C/W
43-75(2)
SOIC-14
CFP-14
PLCC-20
35
5.49°C/W
34
Q
(1) θJC data values stated were derived from MIL-STD-1835B.
(2) Specified θJA (junction to ambient) is for devices mounted to 5 in2 FR4 PC board with one ounce copper where noted. When resistance
range is given, lower values are for 5 in2. Test PWB was 0.062 in thick and typically used 0.635-mm trace widths for power packages
and 1.3-mm trace widths for non-power packages with 100 x 100-mil probe land area at the end of each trace.
DISSIPATION RATINGS
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA≤ 25°C
TA≤ 70°C
POWER RATING
TA≤ 85°CPO
WER RATING
TA≤ 125°C
POWER RATING
PACKAGE
W
700 mW
5.5 mW/°C
452 mW
370 mW
150 mW
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for –55°C ≤ TA≤ 125°C for the UC184X; –40°C ≤ TA≤ 85°C for the
UC284X; 0°C ≤ TA≤ 70°C for the 384X; VCC = 15 V(1); RT = 10 kΩ; CT = 3.3 nF, TA = TJ.
UC1842/3/4/5
UC3842/3/4/5
UC2842/3/4/5
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
REFERENCE SECTION
Output Voltage
TJ = 25°C, IO = 1 mA
4.95
4.9
5.00
6
5.05
20
4.90
5.00
6
5.10
20
V
Line Regulation
12 ≤ VIN≤ 25 V
1 ≤ I0≤ 20 mA
mV
Load Regulation
Temp. Stability
6
25
6
25
(2)(3)
See
0.2
0.4
5.1
0.2
0.4 mV/°C
(2)
Total Output Variation
Output Noise Voltage
Long Term Stability
Output Short Circuit
OSCILLATOR SECTION
Initial Accuracy
Line, load, tempature
4.82
5.18
V
10 Hz≤ f ≤ 10 kHz, TJ = 25°C(2)
TA = 125°C, 1000 Hrs(2)
50
5
50
5
µV
mV
mA
25
25
–30
47
–100 –180
–30
47
–100 –180
TJ = 25°C(4)
52
0.2%
5%
57
52
0.2%
5%
57
kHz
V
Voltage Stability
12 ≤ VCC≤ 25 V
1%
1%
(2)
Temp. Stability
TMIN≤ TA≤ TMAX
(2)
Amplitude
VPIN 4 peak-to-peak
1.7
1.7
(1) Adjust VCC above the start threshold before setting at 15 V.
(2) These parameters, although specified, are not 100% tested in production.
(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
V
(max) * VREF (min)
REF
Temp Stability +
TJ(max) * TJ (min)
VREF(max) and VREF(min) are the maximum and minimum reference voltages measured over
the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
(4) Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
3
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SLUS223C–APRIL 1997–REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for –55°C ≤ TA≤ 125°C for the UC184X; –40°C ≤ TA≤ 85°C for the
UC284X; 0°C ≤ TA≤ 70°C for the 384X; VCC = 15 V; RT = 10 kΩ; CT = 3.3 nF, TA = TJ.
UC1842/3/4/5
UC3842/3/4/5
UC2842/3/4/5
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
ERROR AMP SECTION
Input Voltage
VPIN 1 = 2.5 V
2.45
2.50
–0.3
90
2.55
–1
2.42
2.50
–0.3
90
2.58
–2
V
µA
Input Bias Current
AVOL
2 ≤ VO≤ 4 V
65
0.7
60
65
0.7
60
dB
(5)
Unity Gain Bandwidth
PSRR
TJ = 25°C
1
1
MHz
dB
12 ≤ VCC≤ 25 V
70
70
Output Sink Current
Output Source Current
VOUT High
VPIN 2 = 2.7 V, VPIN 1 = 1.1 V
VPIN 2 = 2.3 V, VPIN 1 = 5 V
VPIN 2 = 2.3 V, RL = 15 kΩ to ground
VPIN 2 = 2.7 V, RL = 15 kΩ to Pin 8
2
6
2
6
mA
V
–0.5
5
–0.8
6
–0.5
5
–0.8
6
VOUT Low
0.7
1.1
0.7
1.1
CURRENT SENSE SECTION
Gain
(6)(7)
See
2.85
0.9
3
1
3.15
1.1
2.85
0.9
3
1
3.15
1.1
V/V
V
(6)
Maximum Input Signal
PSRR
VPIN 1 = 5 V
(5)(6)
12 ≤ VCC≤ 25 V
70
70
dB
µA
ns
Input Bias Current
Delay to Output
OUTPUT SECTION
–2
–10
300
–2
–10
300
(5)
VPIN 3 = 0 V to 2 V
150
150
ISINK = 20 mA
0.1
1.5
0.4
2.2
0.1
1.5
0.4
2.2
Output Low Level
Output High Level
ISINK = 200 mA
ISOURCE = 20 mA
ISOURCE = 200 mA
V
13
12
13.5
13.5
50
13
12
13.5
13.5
50
(5)
Rise Time
Fall Time
TJ = 25°C, CL = 1 nF
TJ = 25°C, CL = 1nF(5)
150
150
150
150
ns
50
50
UNDER-VOLTAGE LOCKOUT SECTION
X842/4
15
7.8
9
16
8.4
10
17
9.0
11
14.5
7.8
8.5
7.0
16
8.4
10
17.5
9.0
Start Threshold
X843/5
V
X842/4
X843/5
11.5
8.2
Min. Operating Voltage After
Turn On
7.0
7.6
8.2
7.6
PWM SECTION
X842/3
X844/5
95%
46%
97% 100%
95%
47%
97% 100%
Maximum Duty Cycle
48%
50%
0%
48%
50%
0%
Minimum Duty Cycle
TOTAL STANDBY CURRENT
Start-Up Current
0.5
11
34
1
0.5
11
34
1
mA
V
Operating Supply Current
VCC Zener Voltager
VPIN 2 = VPIN 3 = 0 V
ICC = 25 mA
17
17
30
30
(5) These parameters, although specified, are not 100% tested in production.
(6) Parameter measured at trip point of latch with VPIN 2 = 0.
DVPIN 1
A +
, 0 v VPIN 3 v 0.8 V
DVPIN 3
(7) Gain defined as:
4
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SLUS223C–APRIL 1997–REVISED JUNE 2007
ERROR AMP CONFIGURATION
Error amp can source or sink up to 0.5 mA.
2.5 V
0.5 mA
+
_
V
FB
Z
I
2
1
COMP
Z
F
UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should be
shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage
currents.
V
CC
V
CC
7
ON/OFF Command
to REST of IC
UC1842 UC1843
UC1844 UC1845
<17 mA
<1 mA
V
ON
16 V
10 V
8.4 V
7.6 V
V
OFF
V
CC
V
OFF
V
ON
CURRENT SENSE CIRCUIT
A small RC filter may be required to suppress switch transients.
ERROR
AMP
2R
I
S
R
1 V
CURRENT
SENSE
COMPARATOR
COMP
1
3
R
CURRENT
SENSE
C
5
R
S
GND
5
Peak Current (I ) is Determined By The Formula
S
,1.0 V
RS
I
SMAX
5
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SLUS223C–APRIL 1997–REVISED JUNE 2007
OSCILLATOR SECTION
V
8
4
5
REF
Timing Resistance vs Frequency
Deadtime vs C (R >5 kW)
T
T
R
T
30
10
3
100
30
R /C
T
T
C
T
10
3
1
GROUND
0.3
100
1 k
10 k 100 k
1 M
1
2.2 4.7 10 22 47 100
− nF
1.72
C
T
f − Frequency − Hz
For R > 5 K f
T
~
R C
T
T
OUTPUT SATURATION CHARACTERISTICS
4
V
= 15 V
CC
3
T
A
= 25°C
T
A
= −55°C
2
1
SOURCE SAT
(V
V
CC − OH)
SINK SAT (V
OL
)
0
.01
.02 .03 .04 .05 .07 .1
.2
.3 .4 .5 .7
1
Output Current, Source or Sink − A
ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE
0
80
60
40
−45
−90
θ
−135
−180
20
Av
0
10
100
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
6
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SLUS223C–APRIL 1997–REVISED JUNE 2007
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas
capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
V
REF
R1
2N2222
A
V
CC
UC1842
4.7 kW
100 kW
COMP
1
2
3
4
V
8
7
6
5
REF
0.1 mF
1 kW
ERROR AMP
ADJUST
V
FB
V
CC
0.1 mF
5 kW
1 W
1 kW
I
OUTPUT
GROUND
SENSE
I
OUTPUT
GROUND
SENSE
4.7 kW
ADJUST
R
T
/ C
T
C
T
SHUTDOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At
this pint the reference turns off, allowing the SCR to reset.
1 kW
COMP
V
1
8
3
REF
SHUTDOWN
330 W
I
SENSE
500 W
SHUTDOWN
To Current
SENSE RESISTOR
7
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UC2842/3/4/5
UC3842/3/4/5
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SLUS223C–APRIL 1997–REVISED JUNE 2007
OFFLINE FLYBACK REGULATOR
T1
D6
U9D946
L1
R1
5 Ω 1 W
+6 V
VARO
VM 68
C9
3300 pF
600 V
R12
4.7 kΩ
2 W
117 VAC
C11
4700 µF
10 V
C10
N5
C1
250 µF
250 V
4700 µF
10 V
N
P
R2
56 kΩ
2 W
COM
D4
1N3613
D7
UF81002
+12 V
C12
D2
D3
2200 µF
R4
4.7 kΩ
R3
20 kΩ
N12
N12
1N3612
1N3612
16 V
±12 V COM
C13
2200 µF
16 V
R9
68 Ω
3 W
C4
C2
100 µF
25 V
C3
22 µF
47 µF
25 V
7
2
1
−12 V
NC
R5 150 kΩ
D8
UES1002
C14
UC3844
R7
22 Ω
Q1
100 pF
C8
UFN833
8
4
680 pF
600 V
6
R8
R6
10 kΩ
3
1 kΩ
C5
5
USD1120
R10
0.55 Ω
1 W
0.01 µF
R11
R13
20 kΩ
D8
1N3613
C7
470 pF
C6
0.0022 µF
2.7 kΩ
2 W
Power Supply Specifications
1. Input Voltages
a. 5VAC to 130VA (50 Hz/60 Hz)
2. Line Isolation: 3750 V
3. Switchng Frequency: 40 kHz
4. Efficiency at Full Load 70%
5. Output Voltage:
a. +5 V, ±5%; 1A to 4A load
Ripple voltage: 50 mV P-P Max
b. +12 V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max
c. –12 V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max
SLOPE COMPENSATION
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over 50%.
8
4
3
V
REF
0.1 mF
R
T
R
/ C
T
T
C
T
UC1842/3
I
R1
C
SENSE
R2
I
SENSE
R
SENSE
8
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
5962-8670401PA
5962-8670401XA
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
8670401PA
UC1842
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
8670401XA
UC1842L/
883B
5962-8670402PA
5962-8670402XA
ACTIVE
ACTIVE
CDIP
JG
FK
8
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8670402PA
UC1843
LCCC
20
POST-PLATE
5962-
8670402XA
UC1843L/
883B
5962-8670403PA
5962-8670403XA
ACTIVE
ACTIVE
CDIP
JG
FK
8
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8670403PA
UC1844
LCCC
20
POST-PLATE
5962-
8670403XA
UC1844L/
883B
5962-8670404DA
5962-8670404PA
5962-8670404XA
ACTIVE
ACTIVE
ACTIVE
CFP
CDIP
LCCC
W
14
8
1
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
5962-8670404DA
UC1845W/883B
JG
FK
-55 to 125
-55 to 125
8670404PA
UC1845
20
POST-PLATE
5962-
8670404XA
UC1845L/
883B
UC1842J
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1842J
UC1842J883B
8670401PA
UC1842
UC1842L883B
UC1842W
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
8670401XA
UC1842L/
883B
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
UC1842W
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC1843J
ACTIVE
CDIP
CDIP
JG
8
8
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1843J
UC1843J883B
ACTIVE
JG
1
8670402PA
UC1843
UC1843L
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
1
1
TBD
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1843L
UC1843L883B
5962-
8670402XA
UC1843L/
883B
UC1843W
UC1844J
ACTIVE
ACTIVE
ACTIVE
CFP
CDIP
CDIP
W
14
8
1
1
1
TBD
TBD
TBD
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
UC1843W
JG
JG
UC1844J
UC1844J883B
8
8670403PA
UC1844
UC1844L883B
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
8670403XA
UC1844L/
883B
UC1845J
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1845J
UC1845J883B
8670404PA
UC1845
UC1845L
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
1
1
TBD
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1845L
UC1845L883B
5962-
8670404XA
UC1845L/
883B
UC1845W
ACTIVE
ACTIVE
CFP
CFP
W
W
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
UC1845W
UC1845W883B
5962-8670404DA
UC1845W/883B
UC2842D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
8
50
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
UC2842D
UC2842D8
Green (RoHS
& no Sb/Br)
UC2842
D8
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC2842D8G4
UC2842D8TR
UC2842D8TRG4
UC2842DG4
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
UC2842
D8
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
D
2500
2500
50
Green (RoHS
& no Sb/Br)
UC2842
D8
8
Green (RoHS
& no Sb/Br)
UC2842
D8
14
14
14
Green (RoHS
& no Sb/Br)
UC2842D
UC2842D
UC2842D
UC2842DTR
2500
2500
Green (RoHS
& no Sb/Br)
UC2842DTRG4
Green (RoHS
& no Sb/Br)
UC2842J
UC2842N
OBSOLETE
ACTIVE
CDIP
PDIP
JG
P
8
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2842N
UC2842N
UC2843D
UC2842NG4
UC2843D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
P
D
D
D
D
D
D
D
D
8
14
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
50
Green (RoHS
& no Sb/Br)
UC2843D8
75
Green (RoHS
& no Sb/Br)
UC2843
D8
UC2843D8G4
UC2843D8TR
UC2843D8TRG4
UC2843DG4
UC2843DTR
UC2843DTRG4
8
75
Green (RoHS
& no Sb/Br)
UC2843
D8
8
2500
2500
50
Green (RoHS
& no Sb/Br)
UC2843
D8
8
Green (RoHS
& no Sb/Br)
UC2843
D8
14
14
14
Green (RoHS
& no Sb/Br)
UC2843D
UC2843D
UC2843D
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC2843J
UC2843N
OBSOLETE
ACTIVE
CDIP
PDIP
JG
P
8
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2843N
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC2843NG4
UC2844D
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
P
8
14
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
UC2843N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
D
D
D
D
P
P
D
D
D
D
D
D
D
50
75
Green (RoHS
& no Sb/Br)
UC2844D
UC2844D8
Green (RoHS
& no Sb/Br)
UC2844
D8
UC2844D8G4
UC2844D8TR
UC2844D8TRG4
UC2844DG4
UC2844DTR
UC2844DTRG4
UC2844N
8
75
Green (RoHS
& no Sb/Br)
UC2844
D8
8
2500
2500
50
Green (RoHS
& no Sb/Br)
UC2844
D8
8
Green (RoHS
& no Sb/Br)
UC2844
D8
14
14
14
8
Green (RoHS
& no Sb/Br)
UC2844D
UC2844D
UC2844D
UC2844N
UC2844N
UC2845D
2500
2500
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC2844NG4
UC2845D
8
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
14
8
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
UC2845D8
75
Green (RoHS
& no Sb/Br)
UC2845
D8
UC2845D8G4
UC2845D8TR
UC2845D8TRG4
UC2845DG4
UC2845DTR
8
75
Green (RoHS
& no Sb/Br)
UC2845
D8
8
2500
2500
50
Green (RoHS
& no Sb/Br)
UC2845
D8
8
Green (RoHS
& no Sb/Br)
UC2845
D8
14
14
Green (RoHS
& no Sb/Br)
UC2845D
2500
Green (RoHS
& no Sb/Br)
UC2845D
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC2845DTRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
UC2845D
UC2845J
UC2845N
OBSOLETE
ACTIVE
CDIP
PDIP
JG
P
8
8
TBD
Call TI
Call TI
-40 to 85
-40 to 85
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2845N
UC2845N
UC3842D
UC2845NG4
UC3842D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
P
D
D
D
D
D
D
D
D
P
P
D
D
D
D
8
14
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
50
Green (RoHS
& no Sb/Br)
UC3842D8
75
Green (RoHS
& no Sb/Br)
UC3842
D8
UC3842D8G4
UC3842D8TR
UC3842D8TRG4
UC3842DG4
UC3842DTR
UC3842DTRG4
UC3842N
8
75
Green (RoHS
& no Sb/Br)
UC3842
D8
8
2500
2500
50
Green (RoHS
& no Sb/Br)
UC3842
D8
8
Green (RoHS
& no Sb/Br)
UC3842
D8
14
14
14
8
Green (RoHS
& no Sb/Br)
UC3842D
UC3842D
UC3842D
UC3842N
UC3842N
UC3843D
2500
2500
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC3842NG4
UC3843D
8
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
14
8
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
UC3843D8
75
Green (RoHS
& no Sb/Br)
UC3843
D8
UC3843D8G4
UC3843D8TR
8
75
Green (RoHS
& no Sb/Br)
UC3843
D8
8
2500
Green (RoHS
& no Sb/Br)
UC3843
D8
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC3843D8TRG4
UC3843DG4
UC3843DTR
UC3843DTRG4
UC3843N
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
8
14
14
14
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
UC3843
D8
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
P
P
50
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
UC3843D
Green (RoHS
& no Sb/Br)
0 to 70
UC3843D
UC3843D
UC3843N
UC3843N
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
UC3843NG4
8
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
UC3843QTR
UC3844D
OBSOLETE
ACTIVE
PLCC
SOIC
FN
D
20
14
TBD
Call TI
Call TI
0 to 70
0 to 70
50
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844D
UC3844D8
UC3844D8G4
UC3844D8TR
UC3844D8TRG4
UC3844DG4
UC3844DTR
UC3844DTRG4
UC3844N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
CDIP
D
D
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
A42
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
UC3844
D8
75
Green (RoHS
& no Sb/Br)
UC3844
D8
D
8
2500
2500
50
Green (RoHS
& no Sb/Br)
UC3844
D8
D
8
Green (RoHS
& no Sb/Br)
UC3844
D8
D
14
14
14
8
Green (RoHS
& no Sb/Br)
UC3844D
UC3844D
UC3844D
UC3844N
UC3844N
UC3845AJ
D
2500
2500
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Green (RoHS
& no Sb/Br)
UC3844NG4
UC3845AJ
P
8
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
JG
8
1
TBD
N / A for Pkg Type
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC3845D
UC3845D8
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
14
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
UC3845D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
D
D
D
P
P
75
75
Green (RoHS
& no Sb/Br)
UC3845
D8
UC3845D8G4
UC3845D8TR
UC3845D8TRG4
UC3845DG4
UC3845DTR
UC3845DTRG4
UC3845N
8
Green (RoHS
& no Sb/Br)
UC3845
D8
8
2500
2500
50
Green (RoHS
& no Sb/Br)
UC3845
D8
8
Green (RoHS
& no Sb/Br)
UC3845
D8
14
14
14
8
Green (RoHS
& no Sb/Br)
UC3845D
UC3845D
UC3845D
UC3845N
UC3845N
2500
2500
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC3845NG4
8
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 7
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1842, UC1843, UC1844, UC1845, UC3842, UC3843, UC3844, UC3845, UC3845AM :
Catalog: UC3842, UC3843, UC3844, UC3845, UC3842M, UC3845A
•
Military: UC1842, UC1843, UC1844, UC1845
•
Space: UC1842-SP, UC1843-SP, UC1844-SP, UC1845-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
UC2842D8TR
UC2842DTR
UC2843D8TR
UC2843DTR
UC2844D8TR
UC2844DTR
UC2845D8TR
UC2845DTR
UC3842D8TR
UC3842DTR
UC3843D8TR
UC3843DTR
UC3844D8TR
UC3844DTR
UC3845D8TR
UC3845DTR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
8
14
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
6.4
6.5
6.4
6.5
6.4
6.5
6.4
6.5
6.4
6.5
6.4
6.5
6.4
6.5
6.4
6.5
5.2
9.0
5.2
9.0
5.2
9.0
5.2
9.0
5.2
9.0
5.2
9.0
5.2
9.0
5.2
9.0
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
14
8
14
8
14
8
14
8
14
8
14
8
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC2842D8TR
UC2842DTR
UC2843D8TR
UC2843DTR
UC2844D8TR
UC2844DTR
UC2845D8TR
UC2845DTR
UC3842D8TR
UC3842DTR
UC3843D8TR
UC3843DTR
UC3844D8TR
UC3844DTR
UC3845D8TR
UC3845DTR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
8
14
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
340.5
333.2
340.5
333.2
340.5
333.2
340.5
333.2
340.5
333.2
340.5
333.2
340.5
333.2
340.5
333.2
338.1
345.9
338.1
345.9
338.1
345.9
338.1
345.9
338.1
345.9
338.1
345.9
338.1
345.9
338.1
345.9
20.6
28.6
20.6
28.6
20.6
28.6
20.6
28.6
20.6
28.6
20.6
28.6
20.6
28.6
20.6
28.6
14
8
14
8
14
8
14
8
14
8
14
8
14
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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