UC2844N [TI]
Current Mode PWM Controller; 电流模式PWM控制器
| 型号： | UC2844N |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Current Mode PWM Controller |
| 文件： | 总19页 (文件大小：934K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
Current Mode PWM Controller
FEATURES
DESCRIPTION
•
Optimized For Off-line And DC
To DC Converters
The UC1842/3/4/5 family of control ICs provides the necessary features to
implement off-line or DC to DC fixed frequency current mode control schemes
with a minimal external parts count. Internally implemented circuits include
under-voltage lockout featuring start up current less than 1mA, a precision
reference trimmed for accuracy at the error amp input, logic to insure latched
operation, a PWM comparator which also provides current limit control, and a
totem pole output stage designed to source or sink high peak current. The
output stage, suitable for driving N Channel MOSFETs, is low in the off state.
•
•
Low Start Up Current (<1mA)
Automatic Feed Forward
Compensation
•
•
Pulse-by-pulse Current Limiting
Enhanced Load Response
Characteristics
Differences between members of this family are the under-voltage lockout
thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have
UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line
applications. The corresponding thresholds for the UC1843 and UC1845 are
8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles
approaching 100%. A range of zero to 50% is obtained by the UC1844 and
UC1845 by the addition of an internal toggle flip flop which blanks the output
off every other clock cycle.
•
Under-voltage Lockout With
Hysteresis
•
•
Double Pulse Suppression
High Current Totem Pole
Output
•
Internally Trimmed Bandgap
Reference
•
•
500khz Operation
Low RO Error Amp
BLOCK DIAGRAM
A/B
Note 1:
Note 2:
A = DIL-8 Pin Number. B = SO-14 and CFP-14 Pin Number.
Toggle flip flop used only in 1844 and 1845.
SLUS223A - APRIL 1997 - REVISED MAY 2002
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ABSOLUTE MAXIMUM RATINGS(Note 1)
Supply Voltage (Low Impedance Source) . . . . . . . . . . . . . . 30V
Supply Voltage (ICC < 30mA) . . . . . . . . . . . . . . . . . Self Limiting
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A
Output Energy (Capacitive Load) . . . . . . . . . . . . . . . . . . . . 5 µJ
Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . . -0.3V to +6.3V
Error Amp Output Sink Current . . . . . . . . . . . . . . . . . . . . 10 mA
Power Dissipation at TA ≤ 25°C (DIL−8) . . . . . . . . . . . . . . . . . 1 W
Power Dissipation at TA ≤ 25°C (SOIC-14) . . . . . . . . . 725 mW
Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . -55°C to +150°C
Lead Temperature (soldering, 10 seconds). . . . . . . . . . . 300°C
Note 1:
All voltages are with respect to Pin 5.
All currents are positive into the specified terminal.
Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (TOP VIEW)
N or J Package, D8 Package
PLCC-20 (TOP VIEW)
Q Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
1
N/C
COMP
N/C
2
3
N/C
4
VFB
5
N/C
6
ISENSE
N/C
7
8
N/C
9
SOIC-14, CFP-14. (TOP VIEW)
D or W Package
RT/CT
N/C
10
11
12
13
14
15
16
17
18
19
20
PWR GND
GROUND
N/C
OUTPUT
N/C
VC
VCC
N/C
VREF
DISSIPATION RATING TABLE
Package
TA ≤ 25°C
Derating Factor
TA ≤ 70°C
TA ≤ 85°C
TA ≤ 125°C
Power Rating
Above TA ≤ 25°C
Power Rating
Power Rating
Power Rating
W
700 mW
5.5 mW/°C
452 mW
370 mW
150 mW
2
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for -55°C ≤ TA ≤ 125°C for the
UC184X; -40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC = 15V
(Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
Reference Section
Output Voltage
Line Regulation
Load Regulation
Temp. Stability
Total Output Variation
Output Noise Voltage
Long Term Stability
Output Short Circuit
Oscillator Section
Initial Accuracy
Voltage Stability
Temp. Stability
Amplitude
TJ = 25°C, IO = 1mA
12 ≤ VIN ≤ 25V
4.95
4.9
5.00
6
5.05
20
4.90
4.82
5.00
6
5.10
20
V
mV
mV
1 ≤ I0 ≤ 20mA
6
25
6
25
(Note 2) (Note 7)
0.2
0.4
5.1
0.2
0.4 mV/°C
Line, Load, Temp. (Note 2)
10Hz ≤ f ≤ 10kHz, TJ = 25°C (Note2)
TA = 125°C, 1000Hrs. (Note 2)
5.18
V
50
5
50
5
µV
mV
mA
25
25
-30
47
-100
-180
-30
47
-100
-180
TJ = 25°C (Note 6)
52
0.2
5
57
1
52
0.2
5
57
1
kHz
%
12 ≤ VCC ≤ 25V
TMIN ≤ TA ≤ TMAX (Note 2)
VPIN 4 peak to peak (Note 2)
%
1.7
1.7
V
Error Amp Section
Input Voltage
VPIN 1 = 2.5V
2.45
2.50
-0.3
90
1
2.55
-1
2.42
2.50
-0.3
90
1
2.58
-2
V
µA
dB
MHz
dB
mA
mA
V
Input Bias Current
AVOL
2 ≤ VO ≤ 4V
65
0.7
60
2
65
0.7
60
2
Unity Gain Bandwidth
PSRR
(Note 2) TJ = 25°C
12 ≤ VCC ≤ 25V
70
6
70
6
Output Sink Current
Output Source Current
VOUT High
VPIN 2 = 2.7V, VPIN 1 = 1.1V
VPIN 2 = 2.3V, VPIN 1 = 5V
VPIN 2 = 2.3V, RL = 15k to ground
VPIN 2 = 2.7V, RL = 15k to Pin 8
-0.5
5
-0.8
6
-0.5
5
-0.8
6
VOUT Low
0.7
1.1
0.7
1.1
V
Current Sense Section
Gain
(Notes 3 and 4)
2.85
0.9
3
1
3.15
1.1
2.85
0.9
3
1
3.15
1.1
V/V
V
Maximum Input Signal
PSRR
VPIN 1 = 5V (Note 3)
12 ≤ VCC ≤ 25V (Note 3) (Note 2)
70
-2
70
-2
dB
µA
ns
Input Bias Current
Delay to Output
-10
-10
VPIN 3 = 0 to 2V (Note 2)
150
300
150
300
Note 2:
Note 3:
Note 4:
These parameters, although guaranteed, are not 100% tested in production.
Parameter measured at trip point of latch with VPIN 2 = 0.
Gain defined as
∆ VPIN 1
A =
, 0 ≤ VPIN 3 ≤ 0.8V
∆ VPIN 3
Adjust VCC above the start threshold before setting at 15V.
Note 5:
Note 6:
Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
Note 7:
VREF (max) − VREF (min)
Temp Stability =
TJ (max) − TJ (min)
VREF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate
temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
3
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
Unless otherwise stated, these specifications apply for −55°C ≤ TA ≤ 125°C for the
UC184X; −40°C ≤ TA ≤ 85°C for the UC284X; 0°C ≤ TA ≤ 70°C for the 384X; VCC =
ELECTRICAL CHARACTERISTICS:
15V (Note 5); RT = 10k; CT = 3.3nF, TA=TJ.
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNITS
PARAMETER
TEST CONDITION
MIN
TYP
MAX
MIN
TYP
MAX
Output Section
Output Low Level
ISINK = 20mA
ISINK = 200mA
0.1
1.5
13.5
13.5
50
0.4
2.2
0.1
1.5
13.5
13.5
50
0.4
2.2
V
V
Output High Level
ISOURCE = 20mA
13
12
13
12
V
ISOURCE = 200mA
V
Rise Time
TJ = 25°C, CL = 1nF (Note 2)
TJ = 25°C, CL = 1nF (Note 2)
150
150
150
150
ns
ns
Fall Time
50
50
Under-voltage Lockout Section
Start Threshold
X842/4
X843/5
X842/4
X843/5
15
7.8
9
16
8.4
10
17
9.0
11
14.5
7.8
8.5
7.0
16
8.4
10
17.5
9.0
V
V
V
V
Min. Operating Voltage
After Turn On
11.5
8.2
7.0
7.6
8.2
7.6
PWM Section
Maximum Duty Cycle
X842/3
X844/5
95
46
97
48
100
50
0
95
47
97
48
100
50
0
%
%
%
Minimum Duty Cycle
Total Standby Current
Start-Up Current
0.5
11
34
1
0.5
11
34
1
mA
mA
V
Operating Supply Current
VPIN 2 = VPIN 3 = 0V
ICC = 25mA
17
17
VCC Zener Voltage
30
30
Note 2:
Note 3:
.
These parameters, although guaranteed, are not 100% tested in production.
Parameter measured at trip point of latch with VPIN 2 = 0
∆ VPIN 1
Note 4:
Gain defined as: A =
; 0 ≤ VPIN 3 ≤ 0.8V.
∆ VPIN 3
Note 5:
Note 6:
Adjust VCC above the start threshold before setting at 15V.
Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
ERROR AMP CONFIGURATION
Error Amp can Source or Sink up to 0.5mA
4
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output driver is activating the power switch with extraneous leakage
biased to sink minor amounts of current. Pin 6 should currents.
be shunted to ground with a bleeder resistor to prevent
CURRENT SENSE CIRCUIT
Peak Current (IS) is Determined By The Formula
1.0V
ISMAX ′
RS
A small RC filter may be required to suppress switch transients.
OSCILLATOR SECTION
5
UC1842/3/4/5
UC2842/3/4/5
ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
OUTPUT SATURATION CHARACTERISTICS
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads ne- single point ground. The transistor and 5k potentiometer
cessitate careful grounding techniques. Timing and by- are used to sample the oscillator waveform and apply
pass capacitors should be connected close to pin 5 in a an adjustable ramp to pin 3.
SHUT DOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two clock cycle after the shutdown condition at pin 1 and/or
methods; either raise pin 3 above 1V or pull pin 1 below 3 is removed. In one example, an externally latched
a voltage two diode drops above ground. Either method shutdown may be accomplished by adding an SCR
causes the output of the PWM comparator to be high which will be reset by cycling VCC below the lower
(refer to block diagram). The PWM latch is reset domi- UVLO threshold. At this point the reference turns off, al-
nant so that the output will remain low until the next lowing the SCR to reset.
6
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
OFFLINE FLYBACK REGULATOR
Power Supply Specifications
5. Output Voltage:
A. +5V, ±5%; 1A to 4A load
Ripple voltage: 50mV P-P Max
1. Input Voltages
5VAC to 130VA
(50 Hz/60Hz)
B. +12V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
2. Line Isolation
3750V
3. Switching Frequency 40kHz
4. Efficiency at Full Load 70%
C. -12V ,±3%; 0.1A to 0.3A load
Ripple voltage: 100mV P-P Max
SLOPE COMPENSATION
A fraction of the oscillator ramp can be resistively
summed with the current sense signal to provide
slope compensation for converters requiring duty
cycles over 50%.
7
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
LCCC
LCCC
CDIP
CDIP
LCCC
LCCC
CDIP
CDIP
LCCC
LCCC
CDIP
CDIP
LCCC
LCCC
CDIP
CDIP
CDIP
LCCC
CFP
Drawing
JG
JG
FK
FK
JG
JG
FK
FK
JG
JG
FK
FK
JG
JG
FK
FK
JG
JG
JG
FK
W
5962-8670401PA
5962-8670401VPA
5962-8670401VXA
5962-8670401XA
5962-8670402PA
5962-8670402VPA
5962-8670402VXA
5962-8670402XA
5962-8670403PA
5962-8670403VPA
5962-8670403VXA
5962-8670403XA
5962-8670404PA
5962-8670404VPA
5962-8670404VXA
5962-8670404XA
UC1842J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
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UC1842JQMLV
UC1842L883B
UC1842W
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1
1
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CDIP
CDIP
LCCC
LCCC
LCCC
CFP
JG
JG
JG
FK
FK
FK
W
UC1843J883B
UC1843JQMLV
UC1843L
8
8
20
20
20
14
8
1
1
POST-PLATE Level-NC-NC-NC
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UC1843L883B
UC1843LQMLV
UC1843W
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UC1844J
CDIP
CDIP
CDIP
LCCC
LCCC
LCCC
CFP
JG
JG
JG
FK
FK
FK
W
UC1844J883B
UC1844JQMLV
UC1844L
8
8
20
20
20
14
8
1
1
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POST-PLATE Level-NC-NC-NC
UC1844L883B
UC1844LQMLV
UC1844W
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A42 SNPB
A42 SNPB
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1
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UC1845J
CDIP
CDIP
CDIP
LCCC
LCCC
LCCC
CFP
JG
JG
JG
FK
FK
FK
W
UC1845J883B
UC1845JQMLV
UC1845L
8
8
20
20
20
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1
1
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
CDIP
PDIP
Drawing
UC2842D
UC2842D8
UC2842D8TR
UC2842DR
UC2842DTR
UC2842DW
UC2842DWTR
UC2842J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
D
D
14
8
50
75
None
None
None
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
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8
2500
D
14
14
16
16
8
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D
2500
40
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
DW
DW
JG
P
2000
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UC2842N
8
50
Pb-Free
(RoHS)
CU SNPB
Level-NC-NC-NC
UC2842P
UC2843D
OBSOLETE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
CDIP
PDIP
P
D
8
14
8
None
None
None
None
None
None
None
Call TI
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50
75
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
UC2843D8
UC2843D8TR
UC2843DR
UC2843DTR
UC2843J
ACTIVE
D
ACTIVE
D
8
2500
OBSOLETE
ACTIVE
D
14
14
8
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D
2500
50
CU NIPDAU Level-1-220C-UNLIM
OBSOLETE
ACTIVE
JG
P
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UC2843N
8
Pb-Free
(RoHS)
CU SNPB
Level-NC-NC-NC
UC2844D
UC2844D8
UC2844D8TR
UC2844DTR
UC2844N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
P
14
8
50
75
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
8
2500
2500
50
14
8
Pb-Free
(RoHS)
CU SNPB
Level-NC-NC-NC
UC2845D
UC2845D8
UC2845D8TR
UC2845DTR
UC2845J
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
CDIP
PDIP
D
D
14
8
50
75
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
ACTIVE
D
8
2500
2500
ACTIVE
D
14
8
OBSOLETE
ACTIVE
JG
P
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UC2845N
8
50
Pb-Free
(RoHS)
CU SNPB
Level-NC-NC-NC
UC3842D
UC3842D8
UC3842D8TR
UC3842DTR
UC3842J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
CDIP
PDIP
D
D
14
8
50
75
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
D
8
2500
2500
1
D
14
8
JG
P
A42 SNPB
CU SNPB
Level-NC-NC-NC
Level-NC-NC-NC
UC3842N
8
50
Pb-Free
(RoHS)
UC3842P
UC3843D
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
CDIP
P
D
8
14
8
None
None
None
None
None
None
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50
75
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
UC3843D8
UC3843D8TR
UC3843DTR
UC3843J
D
D
8
2500
2500
1
D
14
8
JG
A42 SNPB
Level-NC-NC-NC
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
UC3843N
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU SNPB
Level-NC-NC-NC
UC3843P
UC3843QTR
UC3844D
OBSOLETE
OBSOLETE
ACTIVE
PDIP
PLCC
SOIC
SOIC
SOIC
SOIC
CDIP
PDIP
P
FN
D
8
20
14
8
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
50
75
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
UC3844D8
UC3844D8TR
UC3844DTR
UC3844J
ACTIVE
D
ACTIVE
D
8
2500
2500
1
ACTIVE
D
14
8
ACTIVE
JG
P
A42 SNPB
CU SNPB
Level-NC-NC-NC
Level-NC-NC-NC
UC3844N
ACTIVE
8
50
Pb-Free
(RoHS)
UC3844P
UC3845D
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
CDIP
PDIP
P
D
8
14
8
None
None
None
None
None
None
Call TI
Call TI
50
75
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
UC3845D8
UC3845D8TR
UC3845DTR
UC3845J
D
D
8
2500
2500
1
D
14
8
JG
P
A42 SNPB
CU SNPB
Level-NC-NC-NC
Level-NC-NC-NC
UC3845N
8
50
Pb-Free
(RoHS)
UC3845P
OBSOLETE
PDIP
P
8
None
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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