UC2849_技术文档

UC1849

UC2849

UC3849

Secondary Side Average Current Mode Controller

FEATURES

DESCRIPTION

The UC1849 family of average current mode controllers accurately accom-

plishes secondary side average current mode control. The secondary side

output voltage is regulated by sensing the output voltage and differentially

sensing the AC switching current. The sensed output voltage drives a volt-

age error amplifier.The AC switching current, monitored by a current sense

resistor, drives a high bandwidth, low offset current sense amplifier. The

outputs of the voltage error amplifier and current sense amplifier differential-

ly drive a high bandwidth, integrating current error amplifier. The sawtooth

waveform at the current error amplifier output is the amplified and inverted

inductor current sensed through the resistor. This inductor current down-

slope compared to the PWM ramp achieves slope compensation, which

gives an accurate and inherent fast transient response to changes in load.

•

Practical Secondary Side Control

of Isolated Power Supplies

•

1MHz Operation

Differential AC Switching Current

Sensing

•

Accurate Programmable

Maximum Duty Cycle

Multiple Chips Can be

Synchronized to Fastest

Oscillator

•

Wide Gain Bandwidth Product

(70MHz, Acl>10) Current Error

and Current Sense Amplifiers

The UC1849 features load share, oscillator synchronization, undervoltage

lockout, and programmable output control. Multiple chip operation can be

achieved by connecting up to ten UC1849 chips in parallel.The SHARE bus

and CLKSYN bus provide load sharing and synchronization to the fastest

oscillator respectively. The UC1849 is an ideal controller to achieve high

power, secondary side average current mode control.

Up to Ten Devices Can Easily

Share a Common Load

BLOCK DIAGRAM

Pin numbers refer to 24-pin packages.

UDG-94110

7/95

UC1849

UC2849

UC3849

ABSOLUTE MAXIMUM RATINGS

Junction Temperature . . . . . . . . . . . . . . . . . . .−65°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . .+300°C

All voltages with respect to VEE except where noted; all currents

are positive into, negative out of the specified terminal.

Consult Packaging Section of Databook for thermal limitations

and considerations of packages.

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V

Output Current Source or Sink . . . . . . . . . . . . . . . . . . . . . .0.3A

Analog Input Voltages . . . . . . . . . . . . . . . . . . . . . . .−0.3V to 7V

ILIM, KILL, SEQ, ENBL, RUN . . . . . . . . . . . . . . . .−0.3V to 7 V

CLKSYN Current Source . . . . . . . . . . . . . . . . . . . . . . . . .12mA

RUN Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA

SEQ Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA

RDEAD Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA

Share Bus Voltage (voltage with respect to GND) . . .0V to 6.2V

ADJ Voltage (voltage with respect to GND) . . . . . .0.9V to 6.3V

VEE (voltage with respect to GND) . . . . . . . . . . . . . . . . .−1.5V

Storage Temperature . . . . . . . . . . . . . . . . . . .−65°C to +150°C

RECOMMENDED OPERATING CONDITIONS

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V to20V

Sink/Source Output Current . . . . . . . . . . . . . . . . . . . . . .250mA

Timing Resistor (RT) . . . . . . . . . . . . . . . . . . . . . . . . .1k to 200k

Timing Capacitor (CT) . . . . . . . . . . . . . . . . . . . . . .75pF to 2nF

CONNECTION DIAGRAMS

DIL-24, SOIC-24,TSSOP-24 (Top View)

J or N, DW, PW Packages

PLCC-28 (Top View)

Q Package

ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for TA = −55°C to +125°C for

UC1849; −40°C to +85°C for UC2849; and 0°C to +70°C for UC3849;VCC = 12V, VEE = GND, Output no load, CT = 345pF, RT =

4530Ω, RDEAD = 511Ω, RCLKSYN = 1k, TA = TJ.

PARAMETER

Current Sense Amplifier

Ib

TEST CONDITIONS

MIN

TYP

MAX UNITS

0.5

3

5

µA

mV

dB

MHz

V

Vio

TA = +25°C

Over Temperature

Avo

60

90

7

GBW (Note 2)

Acl = 1, RIN = 1k, CC = 15pF, f = 200kHz (Note 1)

Io = 1mA, Voltage above VEE

Io = 0mA

4.5

Vol

0.5

3.8

3.5

80

Voh

V

Io = −1mA

V

CMRR

−0.2 < Vcm < 8V

dB

PSRR

10V < VCC < 20V

Current Error Amplifier

Ib

0.5

3

µA

Vio

20

mV

2

UC1849

UC2849

UC3849

ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for TA = −55°C to +125°C for

UC1849; −40°C to +85°C for UC2849; and 0°C to +70°C for UC3849;VCC = 12V, VEE = GND, Output no load, CT = 345pF, RT =

4530Ω, RDEAD = 511Ω, RCLKSYN = 1k, TA = TJ.

PARAMETER

Current Error Amplifier (cont.)

Avo

TEST CONDITION

MIN

TYP

MAX UNITS

60

90

7

dB

MHz

V

GBW (Note 2)

Acl = 1, RIN = 1k, CC=15pF, f=200kHz (Note 1)

IO = 1mA, Voltage above VEE

IO = 0mA

4.5

Vol

0.5

3.8

3.5

80

Voh

V

IO = −1mA

V

CMRR

−0.2 < Vcm < 8V

dB

PSRR

10V < VCC < 20V

Voltage Error Amplifier

Ib

0.5

2

3

5

µA

mV

dB

MHz

V

Vio

Avo

60

90

7

GBW (Note 2)

f = 200kHz

4.5

Vol

IO = 175µA, Volts above VEE

ILIM > 3V

0.3

3

0.6

3.15

100

Voh

2.85

V

Voh - ILIM

Tested ILIM = 0.5V, 1.0V, 2.0V

−0.2 < Vcm < 8V

−100

mV

dB

CMRR

80

PSRR

10V < VCC < 20V

2X Amplifier and Share Amplifier

V offset (b; y = mx + b)

GAIN (m; y = mx + b)

GBW (Note 2)

RSHARE

20

mV

V

Slope with AVOUT = 1V and 2V

1.98

2.02

100

200

0

kHZ

k

VCC = 0, VSHARE/ISHARE

Total Offset

Vol

Negative supply is VEE, GND Open, VAO = GND

VAO = Voltage Amplifier Vol, Volts above VEE

IO = 0mA, ILIM = 3V, VAO = Voltage Amp Voh

IO = −1mA, ILIM = 3V, VAO = Voltage Amp Voh

−75

0.2

5.7

75

0.6

6.3

mV

V

0.45

6

Voh

V

6

V

Adjust Amplifier

Vio

gm

Vol

40

60

−1

1

80

mV

mS

V

IOUT= −10µA to 10µA, VOUT = 3.5V, CADJ = 1µF

IOUT = 0

0.9

0.85

5.7

1.1

1.15

6.3

IOUT = 50µA

1

V

Voh

IOUT = 0, VSHARE = 6.5V

IOUT = −50µA, VSHARE = 6.5V

6

V

5.7

6

6.3

V

Oscillator

Frequency

450

80

2

500

85

550

90

kHz

%

Max Duty Cycle

OSC Ramp Amplitude

2.5

2.8

V

Clock Driver/SYNC (CLKSYN)

Vol

0.02

3.6

3.2

25

0.2

V

Voh

RCLKSYN = 200Ω

V

ISOURCE

RCLKSYN

VTH

mA

k

VCC = 0, VCLKSYN/ICLKSYN

10

1.5

V

3

UC1849

UC2849

UC3849

ELECTRICAL CHARACTERISTICS (cont)Unless otherwise stated these specifications apply for TA = −55°C to +125°C

for UC1849; −40°C to +85°C for UC2849; and 0°C to +70°C for UC3849;VCC = 12V, VEE = GND, Output no load, CT = 345pF,

RT = 4530Ω, RDEAD = 511Ω, RCLKSYN = 1k, TA = TJ.

PARAMETER

VREF Comparator

TEST CONDITION

MIN

TYP

MAX UNITS

Turn-on threshold

4.65

0.4

V

Hysteresis

VCC Comparator

Turn-on Threshold

Hysteresis

7.9

8.3

0.4

8.7

V

KILL Comparator

Voltage Threshold

Sequence Comparator

Voltage Threshold

3

V

2.5

V

SEQ SAT

Enable Comparator

Voltage Threshold

RUN SAT

IO = 10mA

0.25

2.5

V

0.25

Reference

VREF

TA = 25°C

4.95

4.9

5

5.05

5.1

15

V

VREF

VCC = 15V

10 < VCC < 20

0 < Io < 10mA

VREF = 0V

V

Line Regulation

Load Regulation

Short Circuit I

Output Stage

Rise Time

3

mV

mA

15

30

60

90

CL = 100pF

10

20

ns

V

Fall Time

Voh

VCC > 11V, IO = −10mA

IO = −200mA

8.0

7.8

8.4

8.8

V

Vol

IO = 200mA

3.0

0.5

V

IO = 10mA

V

Virtual Ground

VGND-VEE

VEE is externally supplied, GND is floating

and used as Signal GND.

0.2

0.75

21

V

Icc

Icc (run)

30

mA

Note 1: If a closed loop gain greater than 1 is used, the possible GBW will increase by a factor of ACL + 10; where ACL is the

closed loop gain.

Note 2: Guaranteed by design. Not 100% tested in production.

Note 3: Unless otherwise specified all voltages are with respect to GND. Currents are positive into, negative out of the

specified terminal.

PIN DESCRIPTIONS

ter. The 60mV offset guarantees by design to be greater

than the inherent offset of the gm amplifier and the buffer

amplifier. While the 60mV offset represents an error in

current sharing, the gain of the current and 2X amplifiers

reduces it to only 30mV. This pin needs a 1µF capacitor

to compensate the amplifier.

ADJ: The output of the transconductance (gm = −1mS)

amplifier adjusts the control voltage to maintain equal

current sharing.The chip sensing the highest output cur-

rent will have its output clamped to 1V. A resistor divider

between VREF and ADJ drives the control voltage (VA+)

for the voltage amplifier. Each slave unit’s ADJ voltage

increases (to a maximum of 6V) its control voltage (VA+)

until its load current is equal to the master. The 60mV

input offset on the gm amplifier guarantees that the unit

sensing the highest load current is chosen as the mas-

CA-: The inverting input to the current error amplifier.

This amplifier needs a capacitor between CA- and CAO

to set its dominant pole.

4

UC1849

UC2849

UC3849

PIN DESCRIPTIONS (cont.)

CAO: The output of the current error amplifier which is

internally clamped to 4V. It is internally connected to the

inverting input of the PWM comparator.

The dead time is approximately TDISCHARGE = 2

CT.

·

RDEAD

·

1

(1) Frequency ≈

CS-, CS+: The inverting and non-inverting inputs to the

current sense amplifier. This amplifier is not internally

compensated so the user must compensate externally to

attain the highest GBW for the application.

TCHARGE + TDISCHARGE

TCHARGE

(2) Maximum Duty Cycle ≈

TCHARGE + TDISCHARGE

The CT capacitance should be increased by approxi-

mately 40pF to account for parasitic capacitance.

CLKSYN: The clock and synchronization pin for the

oscillator. This is a bidirectional pin that can be used to

synchronize several chips to the fastest oscillator. Its

input synchronization threshold is 1.4V. The CLKSYN

voltage is 3.6V when the oscillator capacitor (CT) is

being discharged, otherwise it is 0V. If the recommended

synchronization circuit is not used, a 1k or lower value

resistor from CLKSYN to GND may be needed to

increase fall time on CLKSYN pin.

OUT: The output of the PWM driver. It has an upper

clamp of 8.5V. The peak current sink and source are

250mA. All UVLO, SEQ, ENBL, and KILL logic either

enable or disable the output driver.

RDEAD: The pin that programs the maximum duty cycle

by connecting a resistor between it and OSC. The maxi-

mum duty cycle is decreased by increasing this resistor

value which increases the discharge time. The dead

time, the time when the output is low, is 2 RDEAD

CSO: The output of the current sense amplifier which is

internally clamped to 4V.

·

CT. The CT capacitance should be increased by approxi-

mately 40pF to account for parasitic capacitance.

ENBL: The active low input with a 2.5V threshold

enables the output to switch. SEQ and RUN are driven

low when ENBL is above its 2.5V threshold.

RT: This pin programs the charge time of the oscillator

ramp.The charge current is

GND: The signal ground used for the voltage sense

amplifier, current sense amplifier, current error amplifier,

voltage reference, 2X amplifier, and share amplifier. The

output sink transistor is wired directly to this pin.

VREF

2

RT

·

The charge time is approximately TCHARGE ≈ RT

CT

·

KILL: The active low input with a 3.0V threshold stops

the output from switching. Once this function is activated

RUN must be cycled low by driving KILL above 3.0V and

either resetting the power to the chip (VCC) or resetting

the ENBL signal.

when the RDEAD resistor is used.

The dead time is approximately TDISCHARGE ≈ 2

·

RDEAD CT.

·

RUN: This is an open collector logic output that signifies

when the chip is operational. RUN is pulled high to VREF

through an external resistor when VCC is greater than

8.4V, VREF is greater than 4.65V, SEQ is greater than

2.5V, and KILL lower than 3.0V. RUN connected to the

VA+ pin and to a capacitor to ground adds an RC rise

time on the VA+ pin initiating a soft start.

ILIM: A voltage on this pin programs the voltage error

amplifier’s Voh clamp. The voltage error amplifier output

represents the average output current.The Voh clamp con-

sequently limits the output current. If ILIM is tied to VREF, it

defaults to 3.0V. A voltage less than 3.0V connected to

ILIM clamps the voltage error amplifier at this voltage and

consequently limits the maximum output current.

SEQ: The sequence pin allows the sequencing of startup

for multiple units. A resistor between VREF and SEQ and

a capacitor between SEQ and GND creates a unique RC

rise time for each unit which sequences the output start-

up.

OSC: The oscillator ramp pin which has a capacitor (CT)

to ground and a resistor (RDEAD) to the RDEAD pin pro-

grams its maximum duty cycle by programming a mini-

mum dead time. The ramp oscillates between 1.2V to

3.4V when an RDEAD resistor is used. The maximum

duty cycle can be increased by connecting RDEAD to

OSC which changes the oscillator ramp to vary between

0.2V and 3.5V. In order to guarantee zero duty cycle in

this configuration VEE should not be connected to GND.

SHARE:The nearly DC voltage representing the average

output current. This pin is wired directly to all SHARE

pins and is the load share bus.

VA+, VA-: The inverting and non-inverting inputs to the

voltage error amplifier.

The charge time is approximately TCHARGE = RT

when the RDEAD resistor is used.

CT

·

VAO: The output of the voltage error amplifier. Its Voh is

clamped with the ILIM pin.

5

UC1849

UC2849

UC3849

PIN DESCRIPTIONS (cont.)

VCC: The input voltage of the chip. The chip is opera- tual ground because of an internal diode between VEE

tional between 8.4V and 20V.

and GND. The GND current flows through the forward

biased diode and out VEE. GND is always the signal

ground from which the voltage reference and all amplifier

inputs are referenced.

VEE: The negative supply to the chip which powers the

lower voltage rail for all amplifiers.The chip is operational

if VEE is connected to GND or if GND is floating. When

voltage is applied externally to VEE, GND becomes a vir- VREF: The reference voltage equal to 5.0V.

UDG-94111-1

Figure 1. Oscillator Block with External Connections

nized to the highest free running frequency by connect-

ing 100pF capacitors in series with each CLKSYN pin

and connecting the other side of the capacitors together

forming the CLKSYN bus. The CLKSYN bus is then

pulled down to ground with a resistance of approximately

10k. Referring to Figure1, the synchronization threshold

is 1.4V. The oscillator blanks any synchronization pulse

that occurs when OSC is below 2.5V. This allows units,

once they discharge below 2.5V, to continue through the

CIRCUIT BLOCK DESCRIPTION:

PWM Oscillator:The oscillator block diagram with exter-

nal connections is shown in Figure 1. A resistor (RT) con-

nected to pin RT sets the linear charge current;

2.5V

RT .

IRT ≈

The timing capacitor (CT) is linearly charged with the

charge current forcing the OSC pin to charge to a 3.4V

threshold. After exceeding this threshold, the RS flip-flop

is set driving CLKSYN high and RDEAD low which dis-

charges CT. This discharge time with the RC time delay

of 2 CT RDEAD is the minimum output low time. OSC

· ·

continues to discharge until it reaches a 1.2V threshold

and resets the RS flip-flop which repeats the charging

sequence as shown in Figure 2. Equations to approxi-

mate frequency and maximum duty cycle are listed

under the OSC pin description. Figure 3 and 4 graphs

show measured variation of frequency and maximum

duty cycle with varying RT, CT, and RDEAD component

values.

UDG-94112

As shown in Figure 5, several oscillators are synchro-

Figure 2. Oscillator and PWM Output Waveform

6

UC1849

UC2849

UC3849

CIRCUIT BLOCK DESCRIPTION (cont.)

Ω

Figure 3. Output Frequency

UDG-94113

Figure 5. Oscillator Synchronization

Connection Diagram

Figure 4. Maximum Duty Cycle

current discharge and subsequent charge cycles whether

or not other units on the CLKSYN bus are still synchro-

nizing. This requires the frequency of all free running

oscillators to be within 40% of each other to guarantee

synchronization.

Grounds, Voltage Sensing and Current Sensing: The

voltage is sensed directly at the load. Proper load sharing

requires the same sensed voltage for each power supply

connected in parallel. Referring to Figure 6, the positive

sense voltage (VSP) connects to the voltage error ampli-

fier inverting terminal (VA-), the return lead for the on-

chip reference is used as the negative sense (VSM).The

current is sensed across the shunt resistor, RS.

Figure 6 shows one recommended voltage and current

sensing scheme when VEE is connected to GND. The

signal ground is the negative sense point for the output

voltage and the positive sense point for the output cur-

rent. The voltage offset on the current sense amplifier is

not needed if VEE is separated from GND. VEE is the

negative supply for the current sense amplifier.When it is

separated from GND, it extends the current sense ampli-

fier’s common mode input voltage range to include VEE

which is approximately −0.7V below ground. The resistor

RADJ is used for load sharing. The unit which is the mas-

ter will force VADJ to 1.0V. Therefore, the regulated volt-

age being sensed is actually

UDG-94114

Figure 6.Voltage and Current Sense VEE Tied to GND

RADJ

VSP − VSM = (VREF − VADJ)

+ VADJ

· (_{R1 + RADJ}

)

VSM = 0V, VADJ = 1V (master), VREF = 5V

RADJ

VSP = 4

(

)

+ 1V

·

R1 + RADJ

7

UC1849

UC2849

UC3849

CIRCUIT BLOCK DESCRIPTION (cont.)

The ADJ pin voltage on the slave chips will increase forc- voltage error amplifier output is the current command

ing their load currents to increase to match the master.

signal representing the average output load current. The

ILIM pin programs the upper clamp voltage of this ampli-

fier and consequently the maximum load current. A gain

of 2 amplifier connected between the voltage error ampli-

fier output and the share amplifier input increases the

current share resolution and noise margin. The average

current is used as an input to a source only load share

buffer amplifier. The output of this amplifier is the current

share bus. The IC with the highest sensed current will

have the highest voltage on the current share bus and

consequently act as the master. The 60mV input offset

guarantees that the unit sensing the highest load current

is chosen as the master.

The AC frequency response of the voltage error amplifier

is shown in Figure 7.

The adjust amplifier is used by the remaining (slave) ICs

to adjust their respective references high in order to bal-

ance each IC’s load current.The master’s ADJ pin will be

at its 1.0V clamp and connected back to the non-invert-

ing voltage error amplifier input through a high value

resistor. This requires the user to initially calculate the

control voltage with the ADJ pin at 1.0V.

m ≈

Figure 7. AC Frequency Response of the Voltage

Error Amplifier

VREF can be adjusted 150mV to 300mV which compen-

sates for 5% unit to unit reference mismatch and external

Startup and Shutdown: Isolated power up can be resistor mismatch. RADJ will typically be 10 to 30 times

accomplished using the UCC1889. Application Note U- larger than R1.This also attenuates the overall variation of

149 is available for additional information.

the ADJ clamp of 1V ±100mV by a factor of 10 to 30, con-

tributing only a 3mV to 10mV additional delta to VREF.

Refer to the UC3907 Application Note U-130 for further

information on parallel power supply load sharing.

The UC1849 offers several features that enhance startup

and shutdown. Soft start is accomplished by connecting

RUN to VA+ and a capacitor to ground.The resulting RC

rise time on the VA+ pin initiates a soft start. It can also Current Control Loop: The current sense amplifier (CSA)

be accomplished by connecting RUN to ILIM.When RUN is designed specifically for the task of sensing and amplify-

is low it will command zero load current, guaranteeing a ing the inductor ripple current at frequencies up to 1MHz.

soft start. The undervoltage lockout (UVLO) is a logical The CSA’s input offset voltage (VIO) is trimmed to less

AND of ENBL < 2.5V, SEQ > 2.5V, VCC > 8.4V and than 1mV to minimize error of the average current signal.

VREF > 4.65V.The block diagram shows that the thresh- This amplifier is not internally compensated allowing the

olds are set by comparators. By placing an RC divider on user to optimally choose the zero crossing bandwidth.

the SEQ pin, the enabling of multiple chips can be

sequenced with different RC time constants. Similarly,

1

(3) Frequency (0dB) =

2π RINV

CCOMP

·

different RC time constants on the ENBL pins can

sequence shutdown. The UVLO keeps the output from

switching; however the internal reference starts up with

VCC less than 8.4V. The KILL input shuts down the

switching of the chip. This can be used in conjunction

with an overvoltage comparator for overvoltage protec-

tion. In order to restart the chip after KILL has been initi-

ated, the chip must be powered down and then back up.

A pulse on the ENBL pin also accomplishes this without

actually removing voltage to the VCC pin.

RINV is the input resistance at the inverting terminal CS-

CCOMP is the capacitance between CS- and CSO.

Although it is only unity gain stable for a GBW of 7MHz,

the amplifier is typically configured with a differential gain

of at least 10, allowing the amplifier to operate at 70MHz

with sufficient phase margin. A closed loop gain of 10

attenuates the output by 20.8dB.

1

20.8 = 20log

·

11

Load Sharing: Load sharing is accomplished similar to

the UC1907. The sensed current for the UC1849 has an

AC component that is amplified and then averaged. The

to the inverting terminal assuring stability. The amplifier’s

gain fed back into the inverting terminal is less than unity

8

UC1849

UC2849

UC3849

CIRCUIT BLOCK DESCRIPTION (cont.)

at 7MHz, where the phase margin begins to roll off. See

Figure 8 for typical Bode plot.

VILIM

VRS.

(5)

CSGAIN =

The current error amplifier (CEA) also needs its loop

compensated by the user with the same criteria as the

current sense amplifier. This amplifier is essentially the

same wide bandwidth amplifier without the input offset

voltage trim.The zero crossing can also be approximate-

ly calculated with Equation 3. The gain bandwidth of the

current loop is optimized by matching the inductor

downslope (Vo/L) to the oscillator ramp slope (Vs

fs).

·

Subharmonic oscillation problems are avoided by keep-

ing the amplified inductor downslope less than the oscil-

lator ramp slope.

β

−

m

The following equation determines the current error

amplifier gain (GCA):

Vs fs

·

(6) GCA =

;

(Vo/L)

·

RS

·

CSGAIN

Figure 8. Current Sense Amplifier and Current Error

Amplifier Bode Plot

where CSGAIN and RS are defined by equations

4 and 5,

The gain of the differential current sense amplifier

(CSGAIN) is calculated by knowing the maximum load

current. The maximum voltage across the shunt resistor

(RS) divided by RS is the maximum load current. By

amplifying the voltage across RS, VRS, to be equal to the

voltage error amplifier Voh, the current control loop keeps

the load from exceeding its current limit. Voh is set at

3.0V if ILIM is connected to VREF.The maximum current

limit clamp can be reduced by reducing the voltage at

ILIM to less than 3.0V as described in the ILIM pin

description.

Vs is the oscillator peak to peak voltage,

fs is the oscillator frequency,

Vo is the output voltage,

and L is the inductance.

Additional Information about average current mode con-

trol can be found in Unitrode Application Note U-140.

Design Example: Figure 9 is an open loop test that lets

the user test the circuit blocks discussed without having

to build an entire control loop. The pulse width can be

varied by either the VADJ or the VISENSE inputs. Figure 10

shows an isolated power supply using the UC1849 sec-

ondary side average current mode controller.

VRS

(4)

RS =

Max ILOAD

UDG-94115-1

Figure 9. Open Loop Circuit

9

UC1849

UC2849

UC3849

UDG-94116-1

Figure 10. UC1849 Application Diagram

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. 603-424-2410 • FAX 603-424-3460

10

IMPORTANT NOTICE

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型号：	UC2849
厂家：	TEXAS INSTRUMENTS
描述：	Secondary Side Average Current Mode Controller 二次侧平均电流模式控制器控制器
文件：	总11页 (文件大小：544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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