UC2909-EP_16 [TI]
SWITCHMODE LEAD-ACID BATTERY CHARGER;
| 型号： | UC2909-EP_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SWITCHMODE LEAD-ACID BATTERY CHARGER |
| 文件： | 总18页 (文件大小：716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC2909-EP
www.ti.com
SLUSA72 –JULY 2010
SWITCHMODE LEAD-ACID BATTERY CHARGER
Check for Samples: UC2909-EP
1
FEATURES
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
Accurate and Efficient Control of Battery
Charging
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
•
Average Current Mode Control from Trickle to
Overcharge
•
•
Resistor Programmable Charge Currents
Thermistor Interface Tracks Battery
Requirements Over Temperature
•
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Not to Exceed 185.35-KHz Oscillation
Frequency at 125°C
•
•
Output Status Bits Report on Four Internal
Charge States
Undervoltage Lockout Monitors VCC and
VREF
(1) Additional temperature ranges available - contact factory
DESCRIPTION
The UC2909 controls lead acid battery charging with a highly efficient average current mode control loop. This
chip combines charge state logic with average current PWM control circuitry. Charge state logic commands
current or voltage control depending on the charge state. The chip includes undervoltage lockout circuitry to
insure sufficient supply voltage is present before output switching starts. Additional circuit blocks include a
differential current sense amplifier, a 1.5% voltage reference, a –3.9-mV/°C thermistor linearization circuit,
voltage and current error amplifiers, a PWM oscillator, a PWM comparator, a PWM latch, charge state decode
bits, and a 100-mA open collector output driver.
FUNCTION BLOCK DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UC2909-EP
SLUSA72 –JULY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE PART
TA
PACKAGE(2)
TOP-SIDE MARKING
NUMBER
-55°C to 125°C
DW
UC2909MDWREP
UC2909EP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
ABSOLUTE MAXIMUM RATINGS(1) (2)
over operating free-air temperature range unless otherwise noted
UNITS
VCC
Supply voltage
OUT, STAT0, STAT1
40
0.1
V
A
Output current sink
CS+, CS-
(3)
–0.4 to VCC
–0.3 to 9
V
Remaining pin voltages
Storage temperature
Junction temperature range
V
Tstg
TJ
-55 to 150
-55 to 150
300
°C
°C
°C
Lead temperature (soldering, 10 seconds)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and
considerations of packages.
(3) Voltages more negative than -0.4 V can be tolerated if current is limited to 50 mA.
DW PACKAGE
(TOP VIEW)
2
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SLUSA72 –JULY 2010
ELECTRICAL CHARACTERISTICS
TA = –55°C to 125°C; CT = 430 pF, RSET = 11.5 KΩ, R10 = 10 KΩ, RTHM = 10 KΩ, VCC = 15 V, Output no load,
RSTAT0 = RSTAT1 = 10 KΩ, CHGENB = OVCTAP = VLOGIC, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CURRENT SENSE AMPLIFIER (CSA) (VID = CS+ - CS-)
CS- = 0 V, CS+ = -50 mV;
CS+ = –200 mV
4.8
4.8
5
5
5.7
V/V
5.1
DC gain
CS+ = 0 V, CS- = 50 mV;
CS- = 250 mV
VOFFSET
CMRR
Offset voltage (VCSO - VCAO
)
CS+ = CS- = 2.3 V, CAO = CA-
45
mV
VCM = -0.2 V to VCC - 2,
8.8 V < VCC < 14 V
50
50
dB
VCM = -0.2 V to VCC
,
14 V < VCC < 35 V
VID = -550 mV,
VOL
-0.2 V < VCM < VCC - 2,
IO = 500 µA
0.3
5.7
0.6
V
V
VID = 700 mV,
-0.2 V < VCM < VCC - 2,
IO = -250 µA
VOH
5.2
3
6.2
Output source current
Output sink current
3dB bandwidth(1)
VID = 700 mV, CSO = 4 V
VID = -55 0mV, CSO = 1 V
VID = 90 mV, VCM = 0 V
-1
4.5
-0.5
mA
mA
200
KHz
CURRENT ERROR AMPLIFIER (CEA)
8.8 V < VCC < 35 V,
VCHGENB = VLOGIC
IB
0.1
0.8
µA
(2)
VIO
8.8 V < VCC < 35 V, CAO = CA-
1 V < VAO < 4 V
TJ = 25°C, f = 100 KHz
IO = 250 µA
10
90
1.5
0.4
5
mV
dB
MHz
V
AVO
60
1
GBW
VOL
0.6
-12
VOH
IO = –5 mA
4.5
V
Output source current
Output sink current
CAO = 4 V
-25
3
mA
mA
CAO = 1 V
2
ICA-
,
ITRCK_CONTRO
L
VCHGENB = GND
8.5
10
11.5
1
µA
VOLTAGE AMPLIFIER (CEA)
IB
Total bias current; regulating level
0.1
1.2
µA
8.8 V < VCC < 35 V,
VCM = 2.3 V,
(2)
VIO
mV
VAO = VA-
AVO
GBW
VOL
1 V < CAO < 4 V
TJ = 25°C, f = 100 KHz
IO = 500 µA
60
90
0.5
0.4
5
dB
MHz
V
0.25
0.6
VOH
IO = -500 µA
4.75
-2
5.25
V
Output source current
Output sink current
CAO = 4 V
-1
mA
mA
CAO = 1 V
2
2.5
VCHGENB = GND,
STAT0 = 0 and STAT1 = 0,
VAO = 2.3 V
VAO leakage: high impedance
state
-1
1
µA
(1) Not tested in production.
(2) VIO is measured prior to packaging with internal probe pad.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –55°C to 125°C; CT = 430 pF, RSET = 11.5 KΩ, R10 = 10 KΩ, RTHM = 10 KΩ, VCC = 15 V, Output no load,
RSTAT0 = RSTAT1 = 10 KΩ, CHGENB = OVCTAP = VLOGIC, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PULSE WIDTH MODULATOR
Maximum duty cycle
CAO = 0.6 V
90
63
95
71
3
100
80
%
%/V
V
Modulator gain
OSC peak
CAO = 2.5 V, 3.2 V
OSC valley
1
V
OSCILLATOR
Frequency
8.8 V < VCC < 35 V
151.65
2.250
168.50
185.35
2.350
KHz
THERMISTOR DERIVED (VID = VRTHM - VR10
)
Initial accuracy,
VAO (RTHM = 10 KΩ)
VID = 0 V, R10 = RTHM = 10 KΩ(3)
2.300
V
Line regulation
VCC = 8.8 V to 35 V
3
2.495
2.398
2.066
10
2.545
2.446
2.107
mV
RTHM = 138 KΩ, R10 = 10 KΩ
RTHM = 33.63 KΩ, R10 = 10 KΩ
RTHM = 1.014 KΩ, R10 = 10 KΩ
2.435
2.340
2.015
VAO
V
CHARGE ENABLE COMPARATOR (CEC)
Threshold voltage
As a function of VA-
CHGENB = 2.3 V
0.99
-0.5
1
1.01
V/V
µA
Input bias current
-0.1
VOLTAGE SENSE COMPARATOR (VSC)
STAT0 = 0, STAT1 = 0, Function of VREF
STAT0 = 1, STAT1 = 0, Function of VREF
0.944
0.895
0.95
0.9
0.955
0.905
Threshold voltage
V/V
OVER CHARGE TAPER CURRENT COMPARATOR (OCTIC)
Threshold voltage
Input bias current
Function of 2.3 V REF, CA- = CAO
0.99
-0.5
1
1.01
V/V
µA
OVCTAP = 2.3 V
-0.1
LOGIC 5 V (VLOGIC)
VLOGIC
VCC = 15 V
4.875
5
3
3
5.125
15
V
Line regulation
Load regulation
8.8 V < VCC < 35 V
0 A < IO < 10 mA
mV
mV
15
Reference comparator turn-on
threshold
4.3
50
4.85
80
V
Short circuit current
VREF = 0 V
30
mA
OUTPUT STAGE
ISINK
continuous
50
mA
IPEAK
VOL
100
1
mA
V
IO = 50 mA
1.4
25
Leakage current
VOUT = 35 V
µA
(3) Thermistor initial accuracy is measured and trimmed with respect to VAO; VAO = VA-
.
4
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UC2909-EP
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SLUSA72 –JULY 2010
ELECTRICAL CHARACTERISTICS (continued)
TA = –55°C to 125°C; CT = 430 pF, RSET = 11.5 KΩ, R10 = 10 KΩ, RTHM = 10 KΩ, VCC = 15 V, Output no load,
RSTAT0 = RSTAT1 = 10 KΩ, CHGENB = OVCTAP = VLOGIC, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STAT0 AND STAT1 OPEN COLLECTOR OUTPUTS
Maximum sink current
Saturation voltage
Leakage current
STATLV OPEN COLLECTOR OUTPUTS
Maximum sink current
Saturation voltage
Leakage current
UVLO
VOUT = 8.8 V
5
10
mA
IOUT = 5 mA
VOUT = 35 V
0.1
0.45
25
V
µA
VOUT = 5 V
IOUT = 2 mA
VOUT = 5 V
2
5
mA
V
0.1
0.45
3
µA
Turn-on Threshold
Hysteresis
6.8
7.8
8.8
V
100
300
500
mV
ICC
ICC (run)
See Figure 1
VCC = 6.5 V
13
2
19
mA
mA
ICC (off)
-40
-20
0
20
40
80
100
Figure 1. ICC vs Temperature
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1000.0
100.0
10.0
1.0
Wirebond Voiding
Fail Mode
Electromigration Fail Mode
0.1
80
90
100
110
120
130
140
150
160
170
180
Continuous TJ (°C)
Notes:
1. See datasheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
3. Enhanced plastic product disclaimer applies.
Figure 2. UC2909-EP Operating Life Derating Chart
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SLUSA72 –JULY 2010
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
CA-
13
The inverting input to the current error amplifier.
The output of the current error amplifier which is internally clamped to approximately 4 V. It is internally
connected to the inverting input of the PWM comparator.
CAO
14
The inverting and non-inverting inputs to the current sense amplifier. This amplifier has a fixed gain of five
CS-, CS+
CSO
17, 16
15
and a common-mode voltage range of from –250 mV to VCC
.
The output of the current sense amplifier which is internally clamped to approximately 5.7 V.
The input to a comparator that detects when battery voltage is low and places the charger in a trickle charge
state. The charge enable comparator makes the output of the voltage error amplifier a high impedance while
forcing a fixed 10 mA into CA- to set the trickle charge current.
CHGENB
10
The reference point for the internal reference, all thresholds, and the return for the remainder of the device.
The output sink transistor is wired directly to this pin.
GND
3
9
The overcharge current taper pin detects when the output current has tapered to the float threshold in the
overcharge state.
OVCTAP
The oscillator ramp pin which has a capacitor (CT) to ground. The ramp oscillates between approximately
1 V to 3 V and the frequency is approximated by:
OSC
19
1
frequency =
1.2 · CT · RSET
(1)
The output of the PWM driver which consists of an open collector output transistor with 100-mA sink
capability.
OUT
R10
5
Input used to establish a differential voltage corresponding to the temperature of the thermistor. Connect a
10-KΩ resistor to ground from this point.
20
A resistor to ground programs the oscillator charge current and the trickle control current for the oscillator
ramp.
The oscillator charge current is approximately:
1.75
¾
RSET
RSET
18
(2)
The trickle control current (ITRCK_CONTROL) is approximately:
0.115
¾
RSET
(3)
A 10-KΩ thermistor is connected to ground and is thermally connected to the battery. The resistance will
vary exponentially over temperature and its change is used to vary the internal 2.3-V reference by -3.9
mV/°C. The recommended thermistor for this function is part number L1005-5744-103-D1, Keystone Carbon
Company, St. Marys, PA.
RTHM
1
STAT0
STAT1
STATLV
VA-
7
6
This open collector pin is the first decode bit used to decode the charge states.
This open collector pin is the second decode bit used to decode the charge states.
This bit is high when the charger is in the float state.
8
12
11
The inverting input to the voltage error amplifier.
VAO
The output of the voltage error amplifier. The upper output clamp voltage of this amplifier is 5 V.
The input voltage to the chip. The chip is operational between 7.5 V and 40 V and should be bypassed with
a 1-µF capacitor. A typical ICC vs. temperature is shown in Figure 1.
VCC
4
2
VLOGIC
The precision reference voltage. It should be bypassed with a 0.1-µF capacitor.
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CHARGE STATE DECODE CHART
STAT0 and STAT1 are open collector outputs. The output is approximately 0.2 V for a logic 0.
STAT1
STAT0
Trickle charge
Bulk charge
Over charge
Float charge
0
0
1
1
0
1
0
1
8
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APPLICATION INFORMATION
A block diagram of the UC2909 is shown on the first page, while a typical application circuit is shown in Figure 3.
The circuit in Figure 3 requires a DC input voltage between 12 V and 40 V.
The UC2909 uses a voltage control loop with average current limiting to precisely control the charge rate of a
lead-acid battery. The small increase in complexity of average current limiting is offset by the relative simplicity of
the control loop design.
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Figure 3. Typical Application Circuit
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Control Loop
Current Sense Amplifier
This amplifier measures the voltage across the sense resistor RS with a fixed gain of five and an offset voltage of
2.3 V. This voltage is proportional to the battery current. The most positive voltage end of RS is connected to
CSensuring the correct polarity going into the PWM comparator.
CSO = 2.3 V when there is zero battery current.
RS is chosen by dividing 350 mV by the maximum allowable load current. A smaller value for RS can be chosen
to reduce power dissipation.
Maximum charge current, Ibulk, is set by knowing the maximum voltage error amplifier output, VOH = 5 V, the
maximum allowable drop across RS, and setting the resistors RG1 and RG2 such that:
5 · VRS
VLOGIC - CA-
5 · VRS
5 V - 2.3 V
5 · V
2.7 V
RG1
¾
RG2
RS = 1.852 · IBULK · RS
=
=
=
(4)
The maximum allowable drop across RS is specified to limit the maximum swing at CSO to approximately 2 V to
keep the CSO amplifier output from saturating.
No charge/load current: VCSO = 2.3 V
Max charge/load current: Vmax(CSO) = 2.3 V - 2 V = 0.3 V
Voltage Error Amplifier
The voltage error amplifier (VEA) senses the battery voltage and compares it to the 2.3-V - 3.9-mV/°C thermistor
generated reference. Its output becomes the current command signal and is summed with the current sense
amplifier output. A 5-V voltage error amplifier upper clamp limits maximum load current. During the trickle charge
state, the voltage amplifier output is opened (high impedance output) by the charge enable comparator. A trickle
bias current is summed into the CA- input which sets the maximum trickle charge current.
The VEA, VOH = 5 V clamp saturates the voltage loop and consequently limits the charge current as stated in
Equation 4.
During the trickle bias state the maximum allowable charge current (ITC) is similarly determined:
ITRCK_CONTROL · RG1
ITC =
RS · 5
(5)
ITRCK_CONTROL is the fixed control current into CA-. ITRCK_CONTROL is 10 µA when RSET = 11.5 KΩ. See RSET pin
description for equation.
Current Error Amplifier
The current error amplifier (CA) compares the output of the current sense amplifier to the output of the voltage
error amplifier. The output of the CA forces a PWM duty cycle which results in the correct average battery
current. With integral compensation, the CA will have a very high DC current gain, resulting in effectively no
average DC current error. For stability purposes, the high frequency gain of the CA must be designed such that
the magnitude of the down slope of the CA output signal is less than or equal to the magnitude of the up slope of
the PWM ramp.
Charge Algorithm
Trickle Charge State
STAT0 = STAT1 = STATLV = logic 0
When CHGNB is less than VREF (2.3 V - 3.9 mV/°C), STATLV is forced low. This decreases the sense voltage
divider ratio, forcing the battery to overcharge (VOC).
(RS1 + RS2 + RS3
(RS3
RS4)
VOC = (VREF) ·
RS4)
(6)
11
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During the trickle charge state, the output of the voltage error amplifier is high impedance. The trickle control
current is directed into the CA- pin setting the maximum trickle charge current. The trickle charge current is
defined in Equation 5.
Bulk Charge State
STAT1 = STATLV = logic 0, STAT0 = logic 1
As the battery charges, the UC2909 will transition from trickle to bulk charge when CHGENB becomes greater
than 2.3 V. The transition equation is:
(RS1 + RS2 + RS3
(RS2 + RS3 RS4)
RS4)
VT = (VREF) ·
(7)
STATLV is still driven low.
During the bulk charge state, the voltage error amplifier is now operational and is commanding maximum charge
current (IBULK) set by Equation 4. The voltage loop attempts to force the battery to VOC.
Overcharge State
STAT0 = STATLV = logic 0, STAT1 = logic 1
The battery voltage surpasses 95% of VOC indicating the UC2909 is in its overcharge state.
During the overcharge charge state, the voltage loop becomes stable and the charge current begins to taper off.
As the charge current tapers off, the voltage at CSO increases toward its null point of 2.3 V. The center
connection of the two resistors between CSO and VLOGIC sets the overcurrent taper threshold (OVCTAP).
Knowing the desired overcharge terminate current (IOCT), the resistors ROVC1 and ROVC2 can be calculated by
choosing a value of ROVC2 and using the following equation:
ROVC1 = (1.8518) · IOCT · RS · ROVC2
(8)
Float State
STAT0 = STAT1 = STATLV = logic 1
The battery charge current tapers below its OVCTAP threshold, and forces STATLV high increasing the voltage
sense divider ratio. The voltage loop now forces the battery charger to regulate at its float state voltage (VF).
(RS1 + RS2 + RS3)
VF = (VREF) ·
RS3
(9)
If the load drains the battery to less than 90% of VF, the charger goes back to the bulk charge state, STATE 1.
Off Line Applications
For off line charge applications, either Figure 4 or Figure 5 can be used as a baseline. Figure 4 has the
advantage of high frequency operation resulting in a small isolation transformer. Figure 5 is a simpler design, but
at the expense of larger magnetics.
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UC2909
Figure 4. Off Line Charger With Primary Side PWM
Figure 5. Isolated Off Line Charger
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
UC2909MDWREP
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC2909-EP :
Catalog: UC2909
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC2909MDWREP
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
UC2909MDWREP
2000
Pack Materials-Page 2
IMPORTANT NOTICE
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Audio
Applications
www.ti.com/audio
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Copyright © 2012, Texas Instruments Incorporated
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