UC3526M [TI]
Regulating Pulse Width Modulator;
| 型号： | UC3526M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Regulating Pulse Width Modulator |
| 文件： | 总11页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1526A
UC2526A
UC3526A
Regulating Pulse Width Modulator
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
Reduced Supply Current
The UC1526A Series are improved-performance pulse-width modu-
lator circuits intended for direct replacement of equivalent non- “A”
versions in all applications. Higher frequency operation has been
enhanced by several significant improvements including: a more ac-
curate oscillator with less minimum dead time, reduced circuit de-
lays (particularly in current limiting), and an improved output stage
with negligible cross-conduction current. Additional improvements
include the incorporation of a precision, band-gap reference gener-
ator, reduced overall supply current, and the addition of thermal
shutdown protection.
Oscillator Frequency to 600kHz
Precision Band-Gap Reference
7 to 35V Operation
Dual 200mA Source/Sink Outputs
Minimum Output Cross-Conduction
Double-Pulse Suppression Logic
Under-Voltage Lockout
Along with these improvements, the UC1526A Series retains the
protective features of under-voltage lockout, soft-start, digital cur-
rent limiting, double pulse suppression logic, and adjustable
deadtime. For ease of interfacing, all digital control ports are TTL
compatible with active low logic.
Programmable Soft-Start
Thermal Shutdown
TTL/CMOS Compatible Logic Ports
5 Volt Operation (VIN = VC = VREF = 5.0V)
Five volt (5V) operation is possible for “logic level” applications by
connecting VIN, VC and VREF to a precision 5V input supply. Consult
factory for additional information.
BLOCK DIAGRAM
6/93
UC1526A
UC2526A
UC3526A
ABSOLUTE MAXIMUM RATINGS (Note 1, 2)
RECOMMENDED OPERATING CONDITIONS
Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V
Collector Supply Voltage (+VC) . . . . . . . . . . . . . . . . . . . . . +40V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN
Source/Sink Load Current (each output) . . . . . . . . . . . . 200mA
Reference Load Current. . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Power Dissipation at TA = +25°C (Note 2) . . . . . . . . . 1000mW
Power Dissipation at TC = +25°C (Note 2). . . . . . . . . . 3000mW
Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (soldering, 10 seconds) . . . . . . . . . . +300°C
(Note 3)
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +35V
Collector Supply Voltage . . . . . . . . . . . . . . . . . . +4.5V to +35V
Sink/Source Load Current (each output) . . . . . . . . 0 to 100mA
Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 600kHz
Oscillator Timing Resistor. . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ
Oscillator Timing Capacitor. . . . . . . . . . . . . . . . . 400pF to 20µF
Available Deadtime Range at 40kHz . . . . . . . . . . . . 1% to 50%
Operating Ambient Temperature Range
UC1526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
UC2526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
UC3526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Note 1: Values beyond which damage may occur.
Note 2: Consult packaging Section of Databook for thermal
limitations and considerations of package.
Note 3: Range over which the device is functional and
parameter limits are guaranteed.
CONNECTION DIAGRAMS
PLCC-20, LCC-20
(TOP VIEW)
Q and L Packages
DIL-18, SOIC-18 (TOP VIEW)
J or N Package, DW Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
1
N/C
+ERROR
-ERROR
COMP.
2
3
4
CSS
5
RESET
6
- CURRENT SENSE
+ CURRENT SENSE
SHUTDOWN
RTIMING
CT
RD
SYNC
OUTPUT A
VC
N/C
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GROUND
OUTPUT B
+VIN
VREF
2
UC1526A
UC2526A
UC3526A
+VIN = 15V, and over operating ambient temperature, unless otherwise specified TA = TJ.
ELECTRICAL CHARACTERISTICS:
UC1526A / UC2526A
UC3526A
TYP
PARAMETER
TEST CONDITIONS
UNITS
MIN
TYP
MAX
MIN
MAX
Reference Section (Note 4)
Output Voltage
TJ = +25°C
4.95
5.00
2
5.05
10
4.90
5.00
2
5.10
15
V
Line Regulation
+VIN = 7 to 35V
IL = 0 to 20mA
mV
mV
mV
V
Load Regulation
5
20
5
20
Temperature Stability
Over Operating TJ (Note 5)
15
5.00
50
15
5.00
50
Total Output Voltage
Range
Over Recommended Operating
Conditions
4.90
25
5.10
4.85
25
5.15
Short Circuit Current
Under-Voltage Lockout
RESET Output Voltage
VREF = 0V
50
100
0.4
50
100
0.4
mA
VREF = 3.8V
VREF = 4.7V
0.2
4.7
0.2
4.8
V
V
2.4
2.4
Oscillator Section (Note 6)
Initial Accuracy
TJ = +25°C
±3
0.5
2
±8
1
±3
0.5
1
±8
1
%
%
Voltage Stability
+VIN = 7 to 35V
Temperature Stability
Minimum Frequency
Maximum Frequency
Sawtooth Peak Voltage
Sawtooth Valley Voltage
SYNC Pulse Width
Over Operating TJ (Note 5)
RT = 150kΩ, CT = 20µF (Note 5)
RT = 2kΩ, CT = 470pF
+VIN = 35V
6
3
%
1
1
Hz
kHz
V
550
0.5
650
0.5
3.0
1.0
1.1
3.5
3.0
1.0
1.1
3.5
+VIN =7V
V
TJ = 25°C, RL = 2.7kΩ to VREF
µs
Error Amplifier Section (Note 7)
Input Offset Voltage
Input Bias Current
RS ≤ 2kΩ
2
5
2
10
mV
nA
nA
dB
V
-350 -1000
-350 -2000
Input Offset Current
DC Open Loop Gain
HIGH Output Voltage
LOW Output Voltage
35
72
100
35
72
200
RL ≥ 10MΩ
64
60
VPIN 1 - VPIN 2 ≥ 150mV, ISOURCE = 100µA
VPIN 2 - VPIN 1 ≥ 150mV, ISINK = 100µA
3.6
4.2
0.2
94
3.6
4.2
0.2
94
0.4
0.4
V
Common Mode Rejection RS ≤ 2kΩ
Supply Voltage Rejection +VIN = 12 to 18V
PWM Comparator (Note 6)
70
66
70
66
dB
dB
80
80
Minimum Duty Cycle
Maximum Duty Cycle
VCOMPENSATION = +0.4V
VCOMPENSATION = +3.6V
0
0
%
%
45
49
45
49
Digital Ports (SYNC, SHUTDOWN, and RESET)
HIGH Output Voltage
LOW Output Voltage
HIGH Input Current
LOW Input Current
Shutdown Delay
ISOURCE = 40µA
ISINK = 3.6mA
VIH = +2.4V
2.4
4.0
0.2
2.4
4.0
0.2
V
V
0.4
0.4
-125
-225
160
-200
-360
-125
-225
160
-200
-360
µA
µA
ns
VIL = +0.4V
From Pin 8, TJ = 25°C
Current Limit Comparator (Note 8)
Sense Voltage
RS ≤ 50Ω
90
100
-3
110
-10
80
100
-3
120
-10
mV
µA
ns
Input Bias Current
Shutdown Delay
From pin 7, 100mV Overdrive, TJ = 25°C
260
260
Note 4: IL = 0mA.
Note 7: VCM = 0 to +5.2V
Note 8: VCM = 0 to +12V.
Note 9: VC = +15V.
Note 5: Guaranteed by design, not 100% tested in production.
Note 6: FOSC = 40kHz, (RT = 4.12kΩ ± 1%, CT = 0.01µF± 1%,
RD = 0 Ω).
Note 10:VIN = +35V, RT = 4.12kΩ.
3
UC1526A
UC2526A
UC3526A
+VIN = 15V, and over operating ambient temperature, unless otherwise specified TA = TJ.
ELECTRICAL CHARACTERISTICS:
UC1526A
UC2526A
UC3526A
TYP
PARAMETER
TEST CONDITIONS
UNITS
MIN
TYP
MAX
MIN
MAX
Soft-Start Section
Error Clamp Voltage
CS Charging Current
RESET = +0.4V
RESET = +2.4V
0.1
0.4
0.1
0.4
V
50
100
150
50
100
150
µA
Output Drivers (Each Output) (Note 9)
HIGH Output Voltage
LOW Output Voltage
ISOURCE = 20mA
12.5
12
13.5
13
12.5
12
13.5
13
V
V
ISOURCE = 100mA
ISINK = 20mA
0.2
1.2
50
0.3
2.0
150
0.6
0.2
0.2
1.2
50
0.3
2.0
150
0.6
0.2
V
ISINK = 100mA
V
Collector Leakage
Rise Time
VC = 40V
µA
µs
µs
nC
CL = 1000pF (Note 5)
CL = 1000pF (Note 5)
0.3
0.1
8
0.3
0.1
8
Fall Time
Cross-Conduction Charge Per cycle, TJ = 25°C
Power Consumption (Note 10)
Standby Current
SHUTDOWN = +0.4V
14
20
14
20
mA
Note 4: IL = 0mA.
Note 5: Guaranteed by design, not 100% tested in production.
Note 6: FOSC = 40kHz, (RT = 4.12kΩ ± 1%, CT = 0.01µF± 1%,
RD = 0 Ω).
Note 7: VCM = 0 to +5.2V
Note 8: VCM = 0 to +12V.
Note 9: VC = +15V.
Note 10:VIN = +35V, RT = 4.12kΩ.
Open Loop Test Circuit UC1526A
4
UC1526A
UC2526A
UC3526A
APPLICATIONS INFORMATION
Voltage Reference
The reference regulator of the UC1526A is based on a
precision band-gap reference, internally trimmed to ±1%
accuracy. The circuitry is fully active at supply voltages
above +7V, and provides up to 20mA of load current to
external circuitry at +5.0V. In systems where additional
current is required, an external PNP transistor can be
used to boost the available current. A rugged low fre-
quency audio-type transistor should be used, and lead
lengths between the PWM and transistor should be as
short as possible to minimize the risk of oscillations.
Even so, some types of transistors may require collec-
tor-base capacitance for stability. Up to 1 amp of load
current can be obtained with excellent regulation if the
device selected maintains high current gain.
Figure 2. Under-Voltage Lockout Schematic
Soft-Start Circuit
The soft-start circuit protects the power transistors and
rectifier diodes from high current surges during power
supply turn-on. When supply voltage is first applied to
the UC1526A, the under-voltage lockout circuit holds
RESET LOW with Q3. Q1 is turned on, which holds the
soft-start capacitor voltage at zero. The second collector
of Q1 clamps the output of the error amplifier to ground,
guaranteeing zero duty cycle at the driver outputs.
When the supply voltage reaches normal operating
range, RESET will go HIGH. Q1 turns off, allowing the
internal 100µA current source to charge CS. Q2 clamps
the error amplifier output to 1VBE above the voltage on
CS. As the soft-start voltage ramps up to +5V, the duty
cycle of the PWM linearly increases to whatever value
the voltage regulation loop requires for an error null.
Figure 1. Extending Reference Output Current
Under-Voltage Lockout
The under-voltage lockout circuit protects the UC1526A
and the power devices it controls from inadequate sup-
ply voltage, If +VIN is too low, the circuit disables the
output drivers and holds the RESET pin LOW. This pre-
vents spurious output pulses while the control circuitry is
stabilizing, and holds the soft-start timing capacitor in a
discharged state.
The circuit consists of a +1.2V bandgap reference and
comparator circuit which is active when the reference
voltage has risen to 3VBE or +1.8V at 25°C. When the
reference voltage rises to approximately +4.4V, the cir-
cuit enables the output drivers and releases the RESET
pin, allowing a normal soft-start. The comparator has
350mV of hysteresis to minimize oscillation at the trip
point. When +VIN to the PWM is removed and the refer-
ence drops to +4.2V, the under-voltage circuit pulls RE-
SET LOW again. The soft-start capacitor is immediately
discharged, and the PWM is ready for another soft-start
cycle.
Figure 3. Soft-Start Circuit Schematic
Digital Control Ports
The three digital control ports of the UC1526A are bi-di-
rectional. Each pin can drive TTL and 5V CMOS logic di-
rectly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector
TTL, open-drain CMOS, and open-collector voltage
comparators; fan-in is equivalent to 1 low-power Schot-
tky gate. Each port is normally HIGH; the pin is pulled
LOW to activate the particular function. Driving SYNC
LOW initiates a discharge cycle in the oscillator. Pulling
SHUTDOWN LOW immediately inhibits all PWM output
pulses. Holding RESET LOW discharges the soft-start
The UC1526A can operate from a +5V supply by con-
necting the VREF pin to the +VIN pin and maintaining the
supply between +4.8 and +5.2V.
5
UC1526A
UC2526A
UC3526A
APPLICATIONS INFORMATION (cont.)
capacitor. The logic threshold is +1.1V at +25°C. Noise
immunity can be gained at the expense of fan-out with an
external 2k pull-up resistor to +5V.
the SYNC pin will then lock the oscillator to the external
frequency.
Multiple devices can be synchronized together by pro-
gramming one master unit for the desired frequency, and
then sharing its sawtooth and clock waveforms with the
slave units. All CT terminals are connected to the CT pin
of the master and all SYNC terminals are likewise con-
nected to the SYNC pin of the master. Slave RT termi-
nals are left open or connected to VREF. Slave RD
terminal may be either left open or grounded.
Figure 4. Digital Control Port Schematic
Oscillators
The oscillator is programmed for frequency and dead
time with three components: RT, CT and RD. Two wave-
forms are generated: a sawtooth waveform at pin 10 for
pulse width modulation, and a logic clock at pin 12. The
following procedure is recommended for choosing timing
values:
Figure 6. Error Amplifier Connections
Error Amplifier
1. With RD= 0Ω (pin 11 shorted to ground) select values
for RT and CT from the graph on page 4 to give the de-
sired oscillator period. Remember that the frequency at
each driver output is half the oscillator frequency, and the
frequency at the +VC terminal is the same as the oscilla-
tor frequency.
The error amplifier is a transconductance design, with an
output impedance of 2MΩ. Since all voltage gain takes
place at the output pin, the open-loop gain/frequency
characteristics can be controlled with shunt reactance to
ground. When compensated for unity-gain stability with
100pF, the amplifier has an open-loop pole at 800Hz.
2. If more dead time is required, select a larger value of
The input connections to the error amplifier are deter-
mined by the polarity of the switching supply output volt-
age. For positive supplies, the common-mode voltage is
+5.0V and the feedback connections in Figure 6A are
used. With negative supplies, the common-mode voltage
is ground and the feedback divider is connected between
the negative output and the +5.0V reference voltage, as
shown in Figure 6B.
RD. At 40kHz dead time increases by 400ns/Ω.
3. Increasing the dead time will cause the oscillator fre-
quency to decrease slightly. Go back and decrease the
value of RT slightly to bring the frequency back to the
nominal design value.
The UC1526A can be synchronized to an external logic
clock by programming the oscillator to free-run at a fre-
quency 10% slower than the SYNC frequency.
A periodic LOW logic pulse approximately 0.5µs wide at
Figure 5. Oscillator Connections and Waveforms
Figure 7. Push-Pull Configuration
6
UC1526A
UC2526A
UC3526A
APPLICATIONS INFORMATION (cont.)
Output Drivers
+VC terminal to ground during switching; however, im-
proved design has limited this cross-conduction period to
less than 50ns. Capacitor decoupling at VC is recom-
mended and careful grounding of Pin 15 is needed to in-
sure that high peak sink currents from a capacitive load
do not cause ground transients.
The totem pole output drivers of the UC1526A are de-
signed to source and sink 100mA continuously and
200mA peak. Loads can be driven either from the output
pins 13 and 16, or from the +VC, as required.
Since the bottom transistor of the totem-pole is allowed to
saturate, there is a momentary conduction path from the
Figure 8. Single-Ended Configuration
Figure 9. Driving N-Channel Power MOSFETs
TYPICAL CHARACTERISTICS
OSCILLATOR PERIOD vs RT and CT
OUTPUT BLANKING
7
UC1526A
UC2526A
UC3526A
TYPICAL CHARACTERISTICS (Cont.)
Output Driver Deadtime vs. RD Value
Under Voltage Lockout Characteristic
Error Amplifier Open Loop Gain vs. Frequency
Current Limit Transfer Function
Shutdown Delay
Output Driver Saturation Voltage
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
8
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
CDIP
LCCC
LCCC
SOIC
Drawing
85515022A
8551502VA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
18
18
18
20
20
18
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
UC1526AJ
J
UC1526AJ883B
UC1526AL
J
FK
FK
DW
POST-PLATE Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC
UC1526AL883B
UC2526ADW
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2526ADWTR
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
18
18
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2526ADWTRG4
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2526AJ
UC2526AN
ACTIVE
ACTIVE
CDIP
PDIP
J
18
18
1
TBD
A42 SNPB
Level-NC-NC-NC
N
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC2526ANG4
UC2526AQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PLCC
SOIC
SOIC
SOIC
SOIC
N
18
20
18
18
18
18
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
FN
46 Green (RoHS &
no Sb/Br)
CU SN
Level-2-260C-1 YEAR
UC3526ADW
DW
DW
DW
DW
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3526ADWG4
UC3526ADWTR
UC3526ADWTRG4
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3526AJ
UC3526AN
ACTIVE
ACTIVE
CDIP
PDIP
J
18
18
1
TBD
A42 SNPB
Level-NC-NC-NC
N
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC3526ANG4
UC3526AQ
ACTIVE
ACTIVE
PDIP
N
18
20
20 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
PLCC
FN
46 Green (RoHS &
no Sb/Br)
CU SN
Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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