UC3543NG4 [TI]

Power Supply Supervisory Circuit; 电源监控电路
UC3543NG4
型号: UC3543NG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Power Supply Supervisory Circuit
电源监控电路

电源电路 电源管理电路 光电二极管 监控
文件: 总20页 (文件大小:1242K)
中文:  中文翻译
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UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
Power Supply Supervisory Circuit  
Both over- and under-voltage sensing circuits can be  
externally programmed for minimum time duration of  
fault before triggering. All functions contain open  
collector outputs which can be used independently or  
wire-or’ed together, and although the SCR trigger is  
directly connected only to the over-voltage sensing  
circuit, it may be optionally activated by any of the  
other outputs, or from an external signal. The O.V.  
circuit also includes an optional latch and external  
reset capability.  
FEATURES  
Includes Over-Voltage, Under-Voltage, and  
Current Sensing Circuits  
Internal 1% Accurate Reference  
Programmable Time Delays  
SCR “Crowbar” Drive of 300 mA  
Remote Activation Capability  
Optional Over-Voltage Latch  
Uncommitted Comparator Inputs for Low  
Voltage Sensing (UC1544 Series Only)  
The UC1544/2544/3544 devices have the added  
versatility of completely uncommitted inputs to the  
voltage sensing comparators so that levels less than  
2.5 V may be monitored by dividing down the internal  
reference voltage. The current sense circuit may be  
used with external compensation as a linear amplifier  
or as a highgain comparator. Although nominally set  
for zero input offset, a fixed threshold may be added  
with an external resistor. Instead of current limiting,  
this circuit may also be used as an additional voltage  
monitor.  
DESCRIPTION  
The monolithic integrated circuits contain all the  
functions necessary to monitor and control the output  
of  
a
sophisticated power supply system.  
Over-voltage (O.V.) sensing with provision to trigger  
an external SCR “crowbar” shutdown; an  
undervoltage (U.V.) circuit which can be used to  
monitor either the output or to sample the input line  
voltage; and a third op amp/comparator usable for  
current sensing (C.L.) are all included in this device,  
together with an independent, accurate reference  
generator.  
The reference generator circuit is internally trimmed  
to eliminate the need for external potentiometers and  
the entire circuit may be powered directly from either  
the output being monitored or from a separate bias  
voltage.  
BLOCK DIAGRAM  
NOTE:  
For each terminal, first number refers to 1543 series, second to 1544 series.  
*On 1543 series, this function is internally connected to VREF.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
Connection Diagrams  
DIL-18, SOIC-18 (TOP VIEW)  
J or N, DW Package  
DIL-16, SOIC-16 (TOP VIEW)  
J or N, DW Package  
(Also W Package for the UC1543 Only)  
UC 1543  
UC 2543  
UC 3543  
UC 1544  
UC 2544  
UC 3544  
SCR Trigger  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
VIN  
SCR Trigger  
VIN  
1
2
16  
15  
Remote Activate  
Reset  
VREF  
Ground  
Remote Activate  
Reset  
VREF  
Ground  
3
4
5
6
14  
13  
12  
11  
C.L. Output  
Offset/Comp  
C.L. N.I. Input  
C.L. INV. Input  
U.V. Indicate  
U.V. Delay  
O.V. Indicate  
O.V. Delay  
C.L. Output  
O.V. Indicate  
O.V. Delay  
O.V. Input  
U.V. Input  
Offset/Comp  
C.L. N.I. Input  
C.L. INV. Input  
U.V. Indicate  
O.V. N.I. Input  
O.V. Inv. Input  
U.V. N.I. Input  
U.V. Inv. Input  
7
8
10  
9
U.V. Delay  
PACKAGE PIN FUNCTION  
PACKAGE PIN FUNCTION  
PLCC-20, LCC-20  
(TOP VIEW)  
Q or L Package  
PLCC-20, LCC-20  
(TOP VIEW)  
Q or L Package  
FUNCTION  
N/C  
PIN  
FUNCTION  
N/C  
PIN  
1
2
1
2
SCR Trigger  
Remote Activate  
Reset  
SCR Trigger  
Remote Activate  
Reset  
3
3
4
4
O.V. Indicate  
N/C  
5
O.V. Indicate  
N/C  
5
3
2
1
20 19  
3
2
1
20 19  
6
6
4
5
6
7
8
4
5
6
7
8
18  
17  
16  
15  
14  
18  
O.V. Delay  
O.V. Input  
N/C  
7
O.V. Delay  
O.V. N.I. Input  
O.V. INV. Input  
U.V. N.I. Input  
7
17  
16  
15  
14  
8
8
9
9
N/C  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
U.V. Input  
U.V. Delay  
U.V. Indicate  
C.L. INV. Input  
C.L. N.I. Input  
Offset/Comp  
C.L. Output  
Ground  
U.V. INV. Input  
U.V. Delay  
U.V. Indicate  
C.L. INV. Input  
C.L. N.I. Input  
Offset/Comp  
C.L. Output  
Ground  
9
10 11 12 13  
9
10 11 12 13  
VREF  
VREF  
VIN  
VIN  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
VALUE  
40  
UNIT  
VIN  
Input supply voltage  
V
Sense inputs, voltage range  
0 to VIN  
-600  
(2)  
SCR trigger current  
mA  
V
Indicator output voltage  
40  
Indicator output sink current  
Power dissipation (package limitation)  
50  
mA  
mW  
1000  
UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
-55 to 125  
-25 to 85  
0 to 70  
-65 to 150  
TJ  
Operating temperature range  
°C  
Tstg  
Storage temperature range  
(1) Currents are positive-into, negative-out of the specified terminal.  
(2) At higher input voltages, a dissipation limiting resistor, RG, is required.  
2
Submit Documentation Feedback  
UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
ELECTRICAL CHARACTERISTICS  
Unless otherwise stated, these specifications apply for TA = -55°C to 125°C for theUC1543 and UC1544; -25°C to 85°C for  
the UC2543 and UC2544; and 0°C to 70°C for the UC3543 and UC3544. Electrical tests are performed with VIN = 10 V and  
2-kpull-up resistors on all indicator outputs. All electrical specifications for the UC1544, UC2544, and UC3544 devices are  
tested with the inverting over-voltage input and the non-inverting under-voltage input externallyconnected to the 2.5 V  
reference. TA = TJ.  
UC1543/UC1544/UC2543/  
UC3543/UC3544  
UC2544  
TYP  
PARAMETER  
Input voltage range  
Supply current  
TEST CONDITIONS  
UNIT  
V
MIN  
4.5  
MAX  
40  
MIN  
4.5  
TYP  
MAX  
40  
TJ = 25°C to TMAX  
TMIN to TMAX  
VIN  
4.7  
40  
10  
15  
4.7  
40  
10  
15  
VIN = 40 V, output open,  
TJ = 25°C  
7
7
ICC  
mA  
T
MINTJTMAX  
Reference Section  
VOUT Output voltage  
TJ = 25°C  
2.48  
2.45  
2.5  
2.52  
2.55  
5
2.45  
2.40  
2.50  
2.55  
2.60  
5
V
Over temperature range  
VIN = 5 to 30 V  
IREF = 0 to 10 mA  
VREF = 0  
Line regulation  
1
1
1
1
mV  
Load regulation  
10  
10  
Short circuit current  
Temperature stability  
-10  
-20  
50  
-40  
-12  
-20  
50  
-40  
mA  
ppm/°C  
SCR Trigger Section  
Peak output current  
VIN = 5V, RG = 0, VO = 0  
VIN = 15 V, IO = -100 mA  
VIN = 40 V  
-100  
12  
-300  
13  
-600  
-100  
12  
-300  
13  
-600  
mA  
V
Peak output voltage  
Output OFF voltage  
Remote activate current  
Remote activate voltage  
Reset current  
0
0.1  
-0.8  
6
0
0.1  
-0.8  
6
R/A Pin = GND  
-0.4  
2
-0.4  
2
mA  
V
R/A Pin Open  
Reset = GND, R/A = GND  
Reset open, R/A = GND  
RL = 50, TJ = 25°C, CD = 0  
RL = 50, TJ = 25°C, CD = 0  
-0.4  
2
-0.8  
6
-0.4  
2
-0.8  
6
mA  
V
Reset voltage  
Output current rise time  
Prop. delay from R/A  
400  
300  
500  
400  
300  
500  
mA/µs  
ns  
V
Prop. delay from O/V input RL = 50, TJ = 25°C, CD = 0  
Comparator Section  
Input threshold (Input  
TJ = 25°C  
2.45  
2.40  
2.50  
2.55  
2.60  
2.40  
2.35  
2.50  
2.60  
2.65  
voltage rising on O.V. and  
falling on U.V.)  
Over temperature range  
Input hysteresis  
25  
-0.3  
0.2  
25  
-0.3  
0.2  
mV  
Input bias current  
Delay saturation  
Delay high level  
Sense input = 0 V  
-1.0  
0.5  
7
-1.0  
0.5  
7
µA  
V
6
6
Delay charging current  
Indicate saturation  
Indicate leakage  
VO = 0  
-200  
-250  
0.2  
-300  
0.5  
1.0  
-200  
-250  
0.2  
-300  
0.5  
1.0  
µA  
V
IL = 10 mA  
VIND = 40 V  
0.01  
0.01  
µA  
Input over drive = 200 mV,  
TJ = 25°C, CD = 0  
400  
10  
400  
10  
ns  
Propagation delay  
Input over drive = 200 mV,  
TJ = 25°C, CD = 1 µF  
ms  
3
Submit Documentation Feedback  
UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
ELECTRICAL CHARACTERISTICS (continued)  
Unless otherwise stated, these specifications apply for TA = -55°C to 125°C for theUC1543 and UC1544; -25°C to 85°C for  
the UC2543 and UC2544; and 0°C to 70°C for the UC3543 and UC3544. Electrical tests are performed with VIN = 10 V and  
2-kpull-up resistors on all indicator outputs. All electrical specifications for the UC1544, UC2544, and UC3544 devices are  
tested with the inverting over-voltage input and the non-inverting under-voltage input externallyconnected to the 2.5 V  
reference. TA = TJ.  
Current Limit Section  
Input voltage range  
Input Bias Current  
0
VIN -3V  
-1.0  
0
VIN -3V  
-1.0  
V
Offset pin open, VCM = 0  
Offset pin open, VCM = 0  
10k from offset pin to GND  
0 VCM12 V, VIN = 15 V  
-0.3  
0
-0.3  
0
µA  
10  
10  
Input offset voltage  
CMRR  
mV  
dB  
80  
60  
100  
70  
120  
80  
60  
100  
70  
120  
Offset pin open, VCM = 0  
V,  
RL = 10 kto 15 k,  
VOUT = 1 to 6 V  
AVOL  
72  
80  
72  
80  
Output saturation  
Output leakage  
IL = 10 mA  
0.2  
0.01  
5
0.5  
1.0  
0.2  
0.01  
5
0.5  
1.0  
V
VIND = 40 V  
µA  
Small signal bandwidth  
AV = 0dB, TJ = 25°C  
MHz  
VOVERDRIVE = 100 mV,  
TJ = 25°C  
Propagation delay  
200  
200  
ns  
TYPICAL CHARACTERISTICS  
Figure 1.  
Figure 2.  
4
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UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
Current Limit Input Threshold  
ID  
Figure 3.  
Figure 4.  
Current Limit Amplifier Gain  
Current Limit Amplifier Frequency Response  
Figure 5.  
Figure 6.  
5
Submit Documentation Feedback  
UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
APPLICATION INFORMATION  
The values for the external components are determined as follows:  
1000  
VTH  
=
R1  
Current limit input threshold,  
CS is determined by the current loop dynamics  
VTH VO  
+
R2  
æ
ö
IP @  
ç
RSC RSC R2 + R3  
è
÷
ø
Peak current to load,  
Short circuit current,  
VTH  
RSC  
ISC  
=
2.5( R4 + R5+ R6 )  
R5+ R6  
VO( low )  
=
Low output voltage limit,  
High output voltage limit,  
2.5( R4 + R5 + R6 )  
VO( high )  
=
R6  
Voltage sensing delay, tD = 10,000Cd  
VIN -5  
0.2  
RG >  
SCR trigger power limiting resistor,  
Figure 7. Typical Application  
6
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UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
APPLICATION INFORMATION (continued)  
Figure 8. Sensing Multiple Supply Voltages  
Figure 9. Input Line Monitor  
7
Submit Documentation Feedback  
UC1543, UC1544  
UC2543, UC2544  
UC3543, UC3544  
www.ti.com  
SLUS188AAPRIL 1997REVISED FEBRUARY 2007  
APPLICATION INFORMATION (continued)  
Figure 10. Overcurrent Shutdown  
8
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PACKAGE OPTION ADDENDUM  
www.ti.com  
23-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
5962-8774001EA  
5962-8774001FA  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
CDIP  
CFP  
J
16  
16  
1
TBD  
Call TI  
A42  
Call TI  
-55 to 125  
5962-8774001EA  
UC1543J/883B  
ACTIVE  
W
25  
TBD  
N / A for Pkg Type  
5962-8774001FA  
UC1543W/883B  
5962-8774002VA  
UC1543J  
OBSOLETE  
ACTIVE  
CDIP  
CDIP  
J
J
18  
16  
TBD  
TBD  
Call TI  
A42  
Call TI  
-55 to 125  
-55 to 125  
1
1
N / A for Pkg Type  
UC1543J  
UC1543J883B  
ACTIVE  
CDIP  
J
16  
TBD  
A42  
N / A for Pkg Type  
-55 to 125  
5962-8774001EA  
UC1543J/883B  
UC1543L  
ACTIVE  
ACTIVE  
LCCC  
LCCC  
FK  
FK  
20  
20  
1
1
TBD  
TBD  
POST-PLATE  
POST-PLATE  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 125  
-55 to 125  
UC1543L  
UC1543L883B  
UC1543L/  
883B  
UC1543W883B  
ACTIVE  
CFP  
W
16  
25  
TBD  
A42  
N / A for Pkg Type  
5962-8774001FA  
UC1543W/883B  
UC1544J  
UC1544J883B  
UC1544L  
OBSOLETE  
OBSOLETE  
OBSOLETE  
OBSOLETE  
NRND  
CDIP  
CDIP  
LCCC  
LCCC  
SOIC  
J
J
18  
18  
20  
20  
16  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-40 to 85  
FK  
FK  
DW  
Call TI  
Call TI  
UC1544L883B  
UC2543DW  
Call TI  
Call TI  
40  
40  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
UC2543DW  
UC2543DW  
UC2543DWG4  
NRND  
SOIC  
DW  
16  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
-40 to 85  
UC2543J  
UC2543N  
ACTIVE  
NRND  
CDIP  
PDIP  
J
16  
16  
1
TBD  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
-25 to 85  
-40 to 85  
UC2543J  
UC2543N  
N
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
UC2543NG4  
NRND  
PDIP  
N
16  
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
N / A for Pkg Type  
-40 to 85  
UC2543N  
UC2544-W  
UC2544DW  
ACTIVE WAFERSALE  
YS  
0
TBD  
Call TI  
Call TI  
NRND  
NRND  
SOIC  
SOIC  
DW  
18  
40  
40  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
-40 to 85  
-40 to 85  
UC2544DW  
UC2544DW  
UC2544DWG4  
DW  
18  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-Apr-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
UC2544J  
UC2544N  
OBSOLETE  
NRND  
CDIP  
PDIP  
J
18  
18  
TBD  
Call TI  
Call TI  
-40 to 85  
-40 to 85  
N
20  
20  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
N / A for Pkg Type  
UC2544N  
UC2544NG4  
NRND  
PDIP  
N
18  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
N / A for Pkg Type  
-40 to 85  
UC2544N  
UC3543J  
UC3543N  
ACTIVE  
NRND  
CDIP  
PDIP  
J
16  
16  
1
TBD  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
0 to 70  
0 to 70  
UC3543J  
UC3543N  
N
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
UC3543NG4  
NRND  
PDIP  
N
16  
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
N / A for Pkg Type  
0 to 70  
UC3543N  
UC3544J  
UC3544N  
OBSOLETE  
NRND  
CDIP  
PDIP  
J
18  
18  
TBD  
Call TI  
Call TI  
0 to 70  
0 to 70  
N
20  
20  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
N / A for Pkg Type  
UC3544N  
UC3544N  
UC3544NG4  
NRND  
PDIP  
N
18  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
N / A for Pkg Type  
0 to 70  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-Apr-2013  
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OTHER QUALIFIED VERSIONS OF UC1543, UC1544, UC2543, UC2543M, UC3543, UC3543M, UC3544 :  
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Military: UC2543M, UC1543, UC1543, UC1544  
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Addendum-Page 3  
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