UC3548Q [TI]
2.2A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC20, PLASTIC, LCC-20;
| 型号： | UC3548Q |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.2A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PQCC20, PLASTIC, LCC-20 开关 |
| 文件： | 总10页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1548
UC2548
UC3548
Primary Side PWM Controller
FEATURES
BLOCK DIAGRAM
•
Primary Side Voltage Feed-
forward Control of Isolated Power
Supplies
•
Accurate DC Control of
Secondary Side Short Circuit
Current using Primary Side
Average Current Mode Control
•
•
Accurate Programmable
Maximum Duty Cycle Clamp
Maximum Volt-Second Product
Clamp to Prevent Core Saturation
•
•
Practical Operation Up to 1MHz
High Current (2A Pk) Totem Pole
Output Driver
•
•
Wide Bandwidth (8MHz) Current
Error Amplifier
Undervoltage Lockout Monitors
VCC, VIN and VREF
•
•
Output Active Low During UVLO
Low Startup Current (500µA)
UDG-95037
Pin numbers refer to 16-pin DIL and SOIC packages only.
DESCRIPTION
The UC3548 family of PWM control ICs uses voltage feed- driver. The current error amplifier easily interfaces with an
forward control to regulate the output voltage of isolated optoisolator from a secondary side voltage sensing circuit.
power supplies. The UC3548 resides on the primary side
A full featured undervoltage lockout (UVLO) circuit is con-
and has the necessary features to accurately control sec-
tained in the UC3548. UVLO monitors the supply voltage
ondary side short circuit current with average current
to the controller (VCC), the reference voltage (VREF), and
mode control techniques. The UC3548 can be used to
the input line voltage (VIN). All three must be good before
control a wide variety of converter topologies.
soft start commences. If either VCC or VIN is low, the sup-
In addition to the basic functions required for pulse width
modulation, the UC3548 implements a patented technique
of sensing secondary current from the primary side in an
isolated buck derived converter. A current waveform syn-
thesizer monitors switch current and simulates the inductor
current downslope so that the complete current waveform
can be constructed on the primary side without actual sec-
ondary side measurement. This information on the primary
side is used by an average current mode control circuit to
accurately limit maximum output current.
ply current required by the chip is only 500µA and the
output is actively held low.
Two on board protection features set controlled limits to
prevent transformer core saturation. Input voltage is moni-
tored and pulse width is constrained to limit the maximum
volt-second product applied to the transformer. A unique
patented technique limits maximum duty cycle within 3%
of a user programmed value.
These two features allow for more optimal use of trans-
formers and switches, resulting in reduced system size
and cost.
The UC3548 circuitry includes a precision reference, a
wide bandwidth error amplifier for average current control,
an oscillator to generate the system clock, latching PWM
comparator and logic circuits, and a high current output
Both patents embodied in the UC3548 belong to Lambda
Electronics Incorporated and are licensed for use in appli-
cations employing these devices.
4/97
UC1548
UC2548
UC3548
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pin 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Output Current, Source or Sink (Pin 14)
Analog Output Currents, Source or Sink (Pins 5 & 10) . . . 5mA
Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range. . . . . . . . . . . . . . . −65°C to +150°C
Lead Temperature (Soldering 10 seconds) . . . . . . . . . . +300°C
Notes: All voltages are with respect to ground (DIL and SOIC
pin 1). Currents are positive into the specified terminal.
Pin numbers refer to the 16 pin DIL and SOIC packages.
Consult Packaging Section of Databook for thermal
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A
±
Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . 0.2V
Analog Input Voltages
(Pins 3, 4, 7, 8, 12, 16) . . . . . . . . . . . . . . . . . . . . . -0.3 to 7V
Analog Input Currents, Source or Sink
(Pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1mA
limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
J, N, or DW Packages
PLCC-20 & LCC-20 (Top View)
Q & L Packages
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications are over the junction temperature range of
−55°C to +125°C for the UC1548, −40°C to +85°C for the UC2548, and 0°C to +70°C for the UC3548. Test conditions are: VCC =
12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Real Time Current Waveform Synthesizer
Ion Amplifier
Offset Voltage
Slew Rate (Note 1)
lib
0.95
20
1
1.05
-20
V
25
-2
V/µs
µA
IOFF Current Mirror
Input Voltage
Current Gain
Current Error Amplifier
AVOL
0.95
0.9
1
1
1.05
1.1
V
A/A
60
100
dB
mV
µA
Vio
12V ≤ VCC ≤ 20V, 0V ≤ VCM ≤ 5V
10
-3
lib
-0.5
3.3
0.3
1.6
8
Voh
IO = −200µA
IO = 200µA
VO = 1V
3.1
3.5
0.6
2.0
V
Vol
V
Source Current
GBW Product
Slew Rate (Note 1)
Oscillator
1.4
5
mA
MHz
V/µs
f = 200kHz
8
10
Frequency
TA = 25°C
240
235
250
260
265
kHz
kHz
2
UC1548
UC2548
UC3548
ELECTRICAL CHARACTERISTICS (cont.): Unless otherwise stated, all specifications are over the junction
temperature range of −55°C to +125°C for the UC1548, −40°C to +85°C for the UC2548, and 0°C to +70°C for the UC3548. Test
conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER
Duty Cycle Clamp
TEST CONDITIONS
MIN
TYP
MAX UNITS
Max Duty Cycle
VCC Comparator
Turn-on Threshold
Turn-off Threshold
Hysteresis
V(DMAX) = 0.75 • VREF
73.5
76.5
79.5
14
%
13
10
3
V
V
V
9
2.5
3.5
UV Comparator
Turn-on Threshold
RHYSTERESIS
4.1
77
4.35
90
4.6
V
Vuv = 4.2V
103
kΩ
Reference
VREF
TA = 25°C
4.95
4.93
5
5.05
5.07
15
V
0 < IO < 10mA, 12 < VCC < 20
12V < VCC < 20V
0 < IO < 10mA
V
Line Regulation
Load Regulation
4
3
mV
mV
mA
15
Short Circuit Current
Output Stage
VREF = 0V
30
50
70
Rise & Fall Time (Note 1)
Output Low Saturation
Cl = 1nF
20
0.25
1.2
45
0.4
2.2
3.0
1.2
ns
V
IO = 20mA
IO = 200mA
IO = -200mA
IO = 20mA
V
Output High Saturation
2.0
V
UVLO Output Low Saturation
0.8
V
ICC
ISTART
VCC = 12V
0.2
0.5
22
0.4
1
mA
mA
mA
ICC (pre-start)
ICC (run)
VCC = 15V, V(UV) = 0
26
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
CAO: Output of the current error amplifier. Also the
ION: Input pin to inductor current waveform synthesizer.
resistor load for the collector of an optocoupler.
Apply a voltage proportional to switch current to this pin.
CDC: Connect a charge balance integration capacitor
from CDC to GND to achieve an accurate duty cycle
clamp. This capacitor also sets the soft start time.
NI: Noninverting input of the current error amplifier.
OUT: Output driver for the gate of a power FET.
PGND: Power ground pin for the output driver. This
ground circuit should be connected to GND at a single
point.
CI: Output of the inductor current waveform synthesizer.
Requires a capacitor to ground.
CT: A capacitor from CT to GND sets the oscillator
frequency.
UV: Line voltage sense pin to insure the chip only
operates with sufficient line voltage. Program with a
resistive divider from the converter input voltage to UV
to GND.
DMAX: Programs maximum duty cycle with a resistive
divider from VREF to DMAX to GND.
GND: Signal ground.
VCC: Chip supply voltage. Bypass with a 1µF ceramic
capacitor to PGND.
INV: Inverting input of the current error amplifier.
VREF: Precision voltage reference. Bypass with a 1µF
ceramic capacitor to GND.
IOFF: Programs the discharge slope of the capacitor on
CI to emulate the down slope of the inductor current
waveform.
VS: Volt second clamp programming pin and feedforward
ramp waveform for the pulse width modulator. Connect a
resistor to the input line voltage and a capacitor to GND.
3
UC1548
UC2548
UC3548
UNDERVOLTAGE LOCKOUT
The undervoltage lockout block diagram is shown in Fig-
ure 1. The VCC comparator monitors chip supply voltage.
Hysteretic thresholds are set at 13V and 10V to facilitate
off-line applications. If the VCC comparator is low, ICC is
low (<500µA) and the output is low.
When the UV comparator is low, ICC is low (<500µA) and
the output is low.
When both the UV and VCC comparators are high, the in-
ternal bias circuitry for the remainder of the chip is
activated. The CDC pin (see discussion on Maximum Duty
Cycle Control and Soft Start) and the Output are held low
until VREF exceeds the 4.5V threshold of the VREF com-
parator. When VREF is good, control of the output driver is
transferred to the PWM circuitry and CDC is allowed to
charge.
The UV comparator monitors input line voltage (VIN). A
pair of resistors divides the input line to UV. Hysteretic in-
put line thresholds are programmed by Rv1 and Rv2. The
thresholds are
VIN(on) = 4.35V • (1 + Rv1/Rv2′) and
VIN(off) = 4.35V • (1 + Rv1/Rv2) where
Rv2′ = Rv2||90k.
If any of the three UVLO comparators go low, the UVLO
latch is set, the output is held low, and CDC is discharged.
This state will be maintained until all three comparators are
high and the CDC pin is fully discharged.
The resulting hysteresis is
VIN(hys) = 4.35V • Rv1 / 90k.
UDG-95038
Figure 1: Undervoltage Lockout
Frequency Decrease as a Function of RT
Oscillator Frequency as a Function of CT
2000
RT = Open
1000
500
100
20
500
1000
5000
50 100
C (pF)
UDG-95039
Figure 2: Oscillator Frequency
4
UC1548
UC2548
UC3548
OSCILLATOR
A capacitor from the CT pin to GND programs oscillator for the output driver. If the maximum duty cycle control is
frequency, as shown in Figure 2. Frequency is determined defeated by connecting DMAX to VREF, the maximum
by:
duty cycle is limited by the oscillator to 90%. If an adjust-
ment is required, an additional trim resistor RT from CT to
F = 1 / (10k • CT).
The sawtooth wave shape is generated by a charging cur- ground can be used to adjust the oscillator frequency. RT
should not be less than 40kohms. This will allow up to a
22% decrease in frequency.
rent of 200µA and a discharge current of 1800µA. The
discharge time of the sawtooth is guaranteed dead time
UDG-95040
Figure 3: Error Amplifier Gain and Phase Response over Frequency
INDUCTOR CURRENT WAVEFORM SYNTHESIZER
Average current mode control is a very useful technique the input to the follower. The discharge current is pro-
to control the value of any current within a switching con- grammed at IOFF.
verter. Input current, output inductor current, switch
The follower has a one volt offset, so that zero current
current, diode current or almost any other current can be
corresponds to one volt at CI. The best utilization of the
controlled. In order to implement average current mode
UC3548 is to translate maximum average inductor current
control, the value of the current must be explicitly known
to a 4 volt signal level. Given N and Ns (the turns ratio of
at all times. To control output inductor current (IL) in a
the power and current sense transformers respectively),
buck derived isolated converter, switch current provides
proper scaling of IL to V(CI) requires a sense resistor Rs
inductor current information, but only during the on time of
as calculated from:
the switch. During the off time, switch current drops
Rs = 4V • Ns • N / IL(max).
Restated, the maximum average inductor current will be
limited to:
abruptly to zero, but the inductor current actually dimin-
ishes with a slope dIL/dt = −Vo/L. This down slope must
be synthesized in some manner on the primary side to
IL(max) = 4V • Ns • N/Rs.
provide the entire inductor current waveform for the con-
IOFF and CI need to be chosen so that the ratio of
trol circuit.
dV(CI)/dt to dIL/dt is the same during switch off time as
The patented current waveform synthesizer (Figure 4) on time. Recommended nominal off current is 100µA.
consists of a unidirectional voltage follower which forces This requires
the voltage on capacitor CI to follow the on time switch
current waveform. A programmable discharge current
synthesizes the off time portion of the waveform. ION is
CI = (100µA • N • Ns • L) / (Rs • Vo(nom))
where L is the output inductor value and Vo(nom) is the
converter regulated output voltage.
5
UC1548
UC2548
UC3548
INDUCTOR CURRENT WAVEFORM SYNTHESIZER (cont.)
There are several methods to program IOFF. If accurate even during short circuit conditions. Actual inductor
maximum current control is required, IOFF must track out- downslope is closer to zero during a short circuit. The
put voltage. The method shown in Figure 4 derives a penalty is that the average current is understated by an
voltage proportional to VIN • D (where D = duty cycle). In amount approximately equal to the nominal inductor rip-
a buck converter, output voltage is proportional to VIN • ple current. Output short circuit is therefore higher than
D. A resistively loaded diode connection to the bootstrap the designed maximum output current.
winding yields a square wave whose amplitude is propor-
A third method of generating IOFF is to add a second
tional to VIN and is duty cycle modulated by the control
winding to the output inductor core (Figure 6). When the
circuit. Averaging this waveform with a filter generates a
power switch is off and inductor current flows in the free
primary side replica of secondary regulated Vo. A single
wheeling diode, the voltage across the inductor is equal
pole filter is shown, but in practice a two or three pole filter
to the output voltage plus the diode drop. This voltage is
provides better transient response. Filtered voltage is con-
then transformed by the second winding to the primary
verted by ROFF to a current to the IOFF pin to control CI
side of the converter. The advantages to this approach
are its inherent accuracy and bandwidth. Winding the sec-
downslope.
If accurate system maximum current is not a critical re- ond coil on the output inductor core while maintaining the
quirement, Figure 5 shows the simplest method of required isolation makes this a more costly solution. In the
downslope generation: a single resistor (ROFF = 40k)
example, ROFF = Vo / 100µA. The 4 • ROFF resistor is
from IOFF to VREF. The discharge current is then 100µA. added to compensate the one volt input level of the IOFF
The disadvantage to this approach is that the synthesizer pin. Without this compensation, a minor current foldback
continues to generate a down slope when the switch is off behavior will be observed.
UDG-95041
Figure 4: Inductor Current Waveform Synthesizer
UDG-95042
UDG-95043
Figure 6: Second Inductor Winding Generation of IOFF
Figure 5: Fixed IOFF
6
UC1548
UC2548
UC3548
The soft start time constant is approximately:
FEED FORWARD PULSE WIDTH MODULATION
T(ss) = 20k • CDC.
Pulse width modulation is achieved by comparing the out-
put of the current error amplifier to the feed forward ramp
generated at VS (Figure 7). The charge slope of the ramp
is determined by a resistor (RVS) from VS to VIN and a
capacitor (CVS) from VS to GND. In the event that CAO is
at its maximum voltage, typically 3.3V, the UC3548 will
limit the power stage to a volt-second product of:
GROUND PLANES
The output driver on the UC3548 is capable of 2A peak
currents. Careful layout is essential for correct operation
of the chip. A ground plane must be employed (Figure 8).
A unique section of the ground plane must be designated
for high di/dt currents associated with the output stage.
This point is the power ground to which to PGND pin is
connected. Power ground can be separated from the rest
of the ground plane and connected at a single point, al-
though this is not strictly necessary if the high di/dt paths
are well understood and accounted for. VCC should be
bypassed directly to power ground with a good high fre-
quency capacitor. The source of the power MOSFET
should connect to power ground as should the return con-
nection for input power to the system and the bulk input
capacitor. The output should be clamped with a high cur-
rent Schottky diode to both VCC and PGND. Nothing else
should be connected to power ground.
VIN • TON(max) = 3.3V • Rvs • Cvs.
An isolated voltage control loop can be implemented with
a secondary side reference, error amplifier and an opto-
isolator. The optoisolator can be used to override the
current amplifier output which is current limited by a 2.5k
resistor. In overcurrent situations, the voltage loop turns
the optoisolator off and the current error amplifier then as-
sumes duty cycle control resulting in accurately limited
maximum output current.
MAXIMUM DUTY CYCLE AND SOFT START
A patented technique is used to accurately program maxi-
mum duty cycle. Programming is accomplished by a
divider from VREF to DMAX (Figure 7). The value pro-
grammed is:
VREF should be bypassed directly to the signal portion of
the ground plane with a good high frequency capacitor.
Low ESR/ESL ceramic 1µF capacitors are recommended
for both VCC and VREF. The capacitors from CT, CDC, CI
and VS should likewise be connected to the signal ground
plane.
D(max) = Rd1 / (Rd1 + Rd2).
For proper operation, the integrating capacitor, CDC,
should be larger than T(osc) / 80k, where T(osc) is the os-
cillator period. CDC also sets the soft start time constant,
so values of CDC larger than minimum may be desired.
UDG-95044
UDG-95045-1
Figure 7: Duty Cycle Control
7
UC1548
UC2548
UC3548
UDG-95046
Figure 8: Ground Plane Considerations
UDG-95047-1
Figure 9: Typical Application - Voltage Feedforward Control Isolated Forward Converter with Average Current Limiting
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
8
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
UC3548N
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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相关型号：
UC3550G-50-AF5-R
Switching Controller, 360kHz Switching Freq-Max, CMOS, PDSO5, HALOGEN FREE, SOT-25, 5 PIN
UTC
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