UC3824N [TI]
HIGH SPEED PWM CONTROLLER;型号: | UC3824N |
厂家: | TEXAS INSTRUMENTS |
描述: | HIGH SPEED PWM CONTROLLER 开关 光电二极管 |
文件: | 总14页 (文件大小:704K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
HIGH SPEED PWM CONTROLLER
FEATURES
DESCRIPTION
•
Complementary Outputs
The UC1824 family of PWM control devices is
optimized for high frequency switched mode power
supply applications. Particular care was given to
•
Practical Operation Switching Frequencies to
1 MHz
minimizing
propagation
delays
through
the
•
•
50-ns Propagation Delay to Output
comparators and logic circuitry while maximizing
bandwidth and slew rate of the error amplifier. This
controller is designed for use in either current mode
or voltage mode systems with the capability for input
voltage feed-forward.
High Current Dual Totem Pole Outputs (1.5 A
Peak)
•
•
Wide Bandwidth Error Amplifier
Fully Latched Logic With Double Pulse
Suppression
Protection circuitry includes
a
current limit
comparator with a 1-V threshold, a TTL compatible
shutdown port, and a soft-start pin which doubles as
a maximum duty cycle clamp. The logic is fully
latched to provide jitter free operation and prohibit
multiple pulses at an output. An under-voltage
lockout section with 800 mV of hysteresis assures
low start up current. During under-voltage lockout,
the outputs are high impedance.
•
•
•
•
•
Pulse-by-Pulse Current Limiting
Soft Start/Maximum Duty Cycle Control
Under-Voltage Lockout with Hysteresis
Low Start Up Current (1.1 mA)
Trimmed Bandgap Reference (5.1 V ± 1%)
BLOCK DIAGRAM
Clock
RT
4
5
OSC
PWM Latch (Set Dom.)
R
CT
6
1.25V
Ramp
7
3
S
E/A Out
Wide Bandwidth
(Set Dom.)
NI
2
1
+
VIN
Error
Amp
INV
Inhibit
9mA
13 VC
11 Out
Soft Start
8
9
ILIM
CPRTR
14 INVOUT
1V
12 Pwr Gnd
Shutdown
CPRTR
ILIM/SD
1.4V
Output
Inhibit
Internal
Bias
VCC 15
9V
4V
UVLO
VCC Good
VREF Good
REF
GEN
Gnd 10
GATE
10 VREF 5.1V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2007, Texas Instruments Incorporated
UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
DESCRIPTION (CONTINUED)
These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads,
such as the gate of a power MOSFET. The on state is designed as a high level.
ABSOLUTE MAXIMUM RATINGS(1)(2)
VALUE
UNIT
Supply voltage (pins 13, 15)
Output current, source or sink (pins 11, 14)
DC
30
V
0.5
2
A
V
Pulse (0.5 ms)
Analog inputs
(Pins 1, 2, 7)
–0.3 TO 7
(Pin 8, 9)
–0.3 TO 6
Clock output current (pin 4)
Error amplifier output current (pin 3)
Soft start sink current (pin 8)
Oscillator charging current (pin 5)
Power dissipation
–5
5
mA
20
–5
1
W
Storage temperature range
Lead temperature (soldering, 10 seconds)
–65 to 150
300
°C
(1) All voltages are with respect to GND (Pin 10); all currents are positive into, negative out of part; pin numbers refer to DIL-16 package.
(2) Consult Unitrode Integrated Circuit Databook for thermal limitations and considerations of package.
SOIC-16
DW PACKAGE
(TOP VIEW)
DIL-16
J OR N PACKAGE
(TOP VIEW)
2
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UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
PACKAGE PIN FUNCTION
PLCC-20 AND LCC-20
Q AND L PACKAGES
(TOP VIEW)
FUNCTION
N/C
INV
PIN
1
2
NI
3
E/A Out
Clock
N/C
4
5
6
RT
7
CT
8
Ramp
Soft Start
N/C
ILIM/SD
Gnd
Out
Pwr Gnd
N/C
VC
9
10
11
12
13
14
15
16
17
18
19
20
INVOUT
VCC
VREF 5.1V
3
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UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for, RT = 3.65k, CT = 1 nF, VCC = 15 V, –55°C < TA < 125°C for the
UC1824, –40°C < TA < 85°C for the UC2824, and 0°C < TA < 70°C for the UC3824, TA = TJ.
UC1824
UC3824
UC2824
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
TYP
MAX
Reference Section
Output voltage
TJ = 25°C, IO = 1 mA
5.05
5.10
2
5.15
20
5
5.10
2
5.20
20
V
Line regulation
10 V < VCC < 30 V
1 mA < IO < 10 mA
TMIN < TA < TMAX
Line, Load, Temperature
10 Hz < f < 10 kHz
TJ = 125°C, 1000 hrs.
VREF = 0 V
mV mV
Load regulation
5
20
5
20
Temperature stability(1)
Total output variation(1)
Output noise voltage(1)
long term stability(1)
Short circuit current
Oscillator Section
Initial accuracy(1)
Voltage stability(1)
Temperature stability(1)
Total variation(1)
0.2
0.4
5.20
0.2
0.4 mV/°C
5
4.95
5.25
V
50
5
50
5
μV
mV
mA
25
25
–15
360
–50
–100
–15
360
–50
–100
TJ = 25°C
400
0.2%
5%
440
2%
400
0.2%
5%
440
2%
kHz
kHz
V
10 V < VCC < 30 V
TMIN < TA < TMAX
Line, Temperature
340
3.9
460
340
3.9
460
Clock out high
4.5
2.3
2.8
1
4.5
2.3
2.8
1
Clock out low
Ramp peak(1)
Ramp valley(1)
Ramp valley to peak(1)
Error Amplifier Section
Input offset voltage
Input bias current
Input offset current
Open loop gain
2.9
3
2.9
3
2.6
0.7
1.6
2.6
0.7
1.6
1.25
2
1.25
2
1.8
1.8
10
3
15
3
mV
μA
μA
0.6
0.1
95
0.6
0.1
95
1
1
1 V < VO < 4 V
1.5 V < VCM < 5.5 V
10 V < VCC < 30 V
VPIN 3 = 1 V
60
75
85
1
60
75
85
1
CMRR
95
95
dB
PSRR
110
2.5
–1.3
4.7
0.5
5.5
12
110
2.5
–1.3
4.7
0.5
5.5
12
Output sink current
Output source current
Output high voltage
Output low voltage
Unity gain bandwidth(1)
Slew rate(1)
mA
V
VPIN 3 = 4 V
–0.5
4
–0.5
4
IPIN 3 = –0.5 mA
IPIN 3 = 1 mA
5
1
5
1
0
0
3
3
MHz
6
6
V/μs
PWM Comparator Section
Pin 7 bias current
Duty cycle range
Pin 3 zero dc threshold
Delay to output(1)
Soft-Start Section
Charge current
VPIN 7 = 0 V
VPIN 7 = 0 V
–1
–5
80
–1
–5
85
μA
%
V
0
0
1.1
1.25
50
1.1
1.25
50
80
20
80
20
ns
VPIN 8 = 0.5 V
VPIN 8 = 1 V
3
1
9
3
1
9
μA
Discharge current
mA
Current Limit/Shutdown Section
Pin 9 bias current
0 < VPIN 9 < 4 V
15
10
μA
(1) This parameter not 100% tested in production but guaranteed by design.
4
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UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for, RT = 3.65k, CT = 1 nF, VCC = 15 V, –55°C < TA < 125°C for the
UC1824, –40°C < TA < 85°C for the UC2824, and 0°C < TA < 70°C for the UC3824, TA = TJ.
UC1824
UC3824
UC2824
TYP
1
PARAMETER
TEST CONDITIONS
UNIT
MIN
0.9
MAX
1.1
MIN
0.9
TYP
1
MAX
1.1
Current limit threshold
Shutdown threshold
Delay to output
V
1.25
1.40
50
1.55
80
1.25
1.40
50
1.55
80
ns
Output Section
IOUT = 20 mA
0.25
1.2
13.5
13
0.40
2.2
0.25
1.2
13.5
13
0.40
2.2
Output low level
Output high level
IOUT = 200 mA
IOUT = –20 mA
IOUT = –200 mA
VC = 30 V
V
13
12
13
12
Collector leakage
Rise/fall time(2)
100
30
500
60
10
500
60
μA
CL = 1 nF
30
ns
Under-Voltage Lockout Section
Start threshold
8.8
0.4
9.2
0.8
9.6
1.2
8.8
0.4
9.2
0.8
9.6
1.2
V
UVLO hysteresis
Supply Current Section
Start up current
ICC
VCC = 8 V
VPIN 1, VPIN 7, VPIN 9 = 0 V; VPIN 2 = 1 V
1.1
22
2.5
33
1.1
22
2.5
33
mA
(2) This parameter not 100% tested in production but guaranteed by design.
UC1824 Printed Circuit Board Layout Considerations
High speed circuits demand careful attention to layout and component placement. To assure proper
performance of the UC1824 follow these rules:
1. Use a ground plane.
2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output
pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves
this purpose.
3. Bypass VCC, VC, and VREF. Use 0.1-μF monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the
ground plane.
4. Treat the timing capacitor, CT, like a bypass capacitor.
5
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UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
Error Amplifier Circuit
Simplified Schematic
Open Loop Frequency Response
Unity Gain Slew Rate
Synchronized Operation
Two Units in Close Proximity
Generalized Synchronization
6
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UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
Oscillator Circuit
Primary Output Deadtime vs CT
(3k £ RT £ 100k)
Primary Output Deadtime vs Frequency
Timing Resistance vs Frequency
160
1.0 nF
140
120
100
80
470 pF
100k
FREQ (Hz)
10k
1M
Typical Non-Overlap Time (TNO) Over Temperature
80
70
60
50
40
TNO (ns)
30
20
10
0
-75
-50
-25
0
25
T ( C)
50
75
100
125
°
Non-Overlap Time (TNO)
7
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UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
Forward Technique for Off-Line Voltage Mode Application
Constant Volt-Second Clamp Circuit
The circuit shown here will achieve a constant volt-sec-
ond product clamp over varying input voltages. The
ramp generator components, RT and CR are chosen so
that the ramp at Pin 9 crosses the 1V threshold at the
same time the desired maximum volt-second product
is reached. The delay through the functional nor block
must be such that the ramp capacitor can be com-
pletely discharged during the minimum deadtime.
Output Section
Simplified Schematic
Rise/Fall Time (CL=1 nF)
Rise/Fall Time (CL=10 nF)
Saturation Curves
8
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UC1824
UC2824
UC3824
www.ti.com
SLUS326A–MARCH 1997–REVISED JULY 2007
Open-Loop Laboratory Test Fixture
UDG-92036-2
This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and by-
pass procedures should be followed. The use of a
ground plane is highly recommended.
UC1824’s functions and measuring their specifications.
9
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
UC2824DW
UC2824DWG4
UC2824N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
N
16
16
16
16
16
16
16
16
16
16
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
Request Free Samples
Purchase Samples
25
Green (RoHS
& no Sb/Br)
UC2824NG4
UC3824DW
N
25
Green (RoHS
& no Sb/Br)
Purchase Samples
DW
DW
DW
DW
N
40
Green (RoHS
& no Sb/Br)
Request Free Samples
Request Free Samples
Purchase Samples
UC3824DWG4
UC3824DWTR
UC3824DWTRG4
UC3824N
40
Green (RoHS
& no Sb/Br)
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Purchase Samples
Green (RoHS
& no Sb/Br)
Request Free Samples
Request Free Samples
UC3824NG4
N
25
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC3824DWTR
SOIC
DW
16
2000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
UC3824DWTR
2000
Pack Materials-Page 2
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相关型号:
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