UC3834DWTR [TI]
High Efficiency Linear Regulator; 高英法fi效率线性稳压器型号: | UC3834DWTR |
厂家: | TEXAS INSTRUMENTS |
描述: | High Efficiency Linear Regulator |
文件: | 总9页 (文件大小:676K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UC1834
UC2834
UC3834
High Efficiency Linear Regulator
FEATURES
DESCRIPTION
•
Minimum VIN - VOUT Less Than
0.5V At 5A Load With External
Pass Device
The UC1834 family of integrated circuits is optimized for the design of low
input-output differential linear regulators. A high gain amplifier and 200mA
sink or source drive outputs facilitate high output current designs which use
an external pass device. With both positive and negative precision refer-
ences, either polarity of regulator can be implemented. A current sense am-
plifier with a low, adjustable, threshold can be used to sense and limit
currents in either the positive or negative supply lines.
•
•
•
•
Equally Usable For Either Positive
or Negative Regulator Design
Adjustable Low Threshold Current
Sense Amplifier
In addition, this series of parts has a fault monitoring circuit which senses
both under and over-voltage fault conditions. After a user defined delay for
transient rejection, this circuitry provides a fault alert output for either fault
condition. In the over-voltage case, a 100mA crowbar output is activated.
An over-voltage latch will maintain the crowbar output and can be used to
shutdown the driver outputs. System control to the device can be accom-
modated at a single input which will act as both a supply reset and remote
shutdown terminal. These die are protected against excessive power dissi-
pation by an internal thermal shutdown function.
Under And Over-Voltage Fault Alert
With Programmable Delay
Over-Voltage Fault Latch With
100mA Crowbar Drive Output
BLOCK DIAGRAM
6/94
UC1834
UC2834
UC3834
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage, VIN + . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Driver Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA
Driver Source to Sink Voltage . . . . . . . . . . . . . . . . . . . . . . . 40V
Crowbar Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200mA
+1.5V Reference Output Current . . . . . . . . . . . . . . . . . . −10mA
Fault Alert Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Fault Alert Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Error Amplifier Inputs . . . . . . . . . . . . . . . . . . . . . . −0.5V to 35V
Current Sense Inputs . . . . . . . . . . . . . . . . . . . . . . −0.5V to 40V
O.V. Latch Output Voltage . . . . . . . . . . . . . . . . . . −0.5V to 40V
O.V. Latch Output Current . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Power Dissipation at TA = 25°C . . . . . . . . . . . . . . . . . . 1000mW
Power Dissipation at TC = 25°C. . . . . . . . . . . . . . . . . . 2000mW
Operating Junction Temperature. . . . . . . . . . −55°C to +150°C
Storage Temperature. . . . . . . . . . . . . . . . . . . −65°C to +150°C
Lead Temperature (soldering, 10 seconds). . . . . . . . . . . 300°C
Note 1: Voltages are reference to VIN−, Pin 5.
Currents are positive into, negative out of the specified
terminals.
Consult Packaging section of Databook for thermal
limitations and considerations of package.
CONNECTION DIAGRAMS
PLCC-20, LCC-20 (TOP VIEW)
Q, L Packages
DIL-16, SOIC-16 (TOP VIEW)
J or N Package, DW Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
1
N/C
VIN +
2
−2.0V REF
+1.5V REF
Threshold Adjust
N/C
3
4
5
6
VIN−
7
Sense−
8
Sense+
9
N.Inv. Input
N/C
10
11
12
13
14
15
16
17
Inv. Input
Fault Alert
Fault Delay
Driver Sink
N/C
Driver Source
Compensation/ Shutdown 18
O.V. Latch Output/Reset
Crowbar Gate
19
20
2
UC1834
UC2834
UC3834
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for TA=−55°C to +125°C
for the UC1834, −40°C to +85°C for the UC2834, and 0°C to +70°C for the
UC3834. VIN+ = 15V, VIN− = 0V, TA = TJ.
UC1834
UC2834
UC3834
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX MIN
TYP MAX
Turn-on Characteristics
Standby Supply Current
+1.5 Volt Reference
5.5
7
5.5
1.5
10
mA
V
Output Voltage
TJ = 25°C
1.485 1.5 1.515 1.47
1.53
1.545
15
TJ(MIN ≤ TJ ≤ TJ(MAX)
1.47
1.53 1.455
)
Line Regulation
VIN+ = 5 to 35V
IOUT = 0 to 2mA
1
1
10
10
1
1
mV
mV
Load Regulation
15
-2.0 Volt Reference (Note 2)
Output Voltage (Referenced TJ = 25°C
−2.04
−2.06
−2
−1.96 −2.06
−1.94 −2.08
15
−2
−1.94
−1.92
20
V
+
to VIN )
TJ(MIN) ≤ TJ ≤ TJ(MAX)
Line Regulation
VIN+ = 5 to 35V
1.5
2.3
1.5
2.3
mV
Output Impedance
Error Amplifier Section
Input Offset Voltage
Input Bias Current
Input Offset Current
kΩ
VCM = 1.5V
VCM = 1.5V
VCM = 1.5V
1
6
−4
1
1
10
−8
2
mV
µA
µA
dB
−1
0.1
65
−1
0.1
65
Small Signal Open Loop Gain Output @ Pin 14, Pin 12 = VIN+
50
50
Pin 13, 20Ω to VIN−
CMRR
VCM = 0.5 to 33V, VIN+ = 35V
VIN+ = 5 to 35V, VCM = 1.5V
60
70
80
60
70
80
dB
dB
PSRR
100
100
Driver Section
Maximum Output Current
Saturation Voltage
Output Leakage Current
200
0.4
350
0.5
0.1
1
200
350
0.5
0.1
1
mA
V
IOUT = 100mA
1.2
50
1.5
50
Pin 12 = 35V, Pin 13 = VIN−, Pin 14 = VIN−
µA
V
Shutdown Input Voltage
at Pin 14
IOUT ≤ 100µA, Pin 13 = VIN−, Pin 12 =
VIN+
0.4
Shutdown Input Current
at Pin 14
Pin 14 = VIN−, Pin 12 = VIN+
IOUT ≤ 100µA, Pin 13 = VIN−
−100 −150
−100 −150
µA
Thermal Shutdown (Note 3)
165
165
°C
Fault Amplifier Section
Under- and Over-Voltage
Fault Threshold
VCM = 1.5V, @ E/A Inputs
120
150
180
110
150
190
mV
Common Mode Sensitivity
Supply Sensitivity
VIN+ = 35V, VCM = 1.5 to 33V
VCM = 1.5V, VIN+ = 5 to 35V
−0.4 −0.8
−0.5 −1.0
−0.4 −1.0
−0.5 −1.2
%/v
%/V
Fault Delay
30
2
45
5
60
30
2
45
5
60 ms/µF
Fault Alert Output Current
mA
Fault Alert Saturation Voltage IOUT = 1mA
O.V. Latch Output Current
0.2
4
0.5
0.2
4
0.5
V
mA
V
2
2
O.V. Latch Saturation Voltage IOUT = 1mA
1.0
0.4
1.3
0.6
1.0
0.4
1.3
0.6
O.V. Latch Output Reset
Voltage
0.3
0.3
V
Crowbar Gate Current
−100 −175
−0.5
−100 −175
−0.5
mA
Crowbar Gate Leakage
Current
VIN+ = 35V, Pin 16 = VIN−
−50
−50
µA
Note 2: When using both the 1.5V and −2.0V references the current out of pin 3 should be balanced by an equivalent current into
Pin 2. The −2.0V output will change −2.3mV per µA of imbalance.
Note 3: Thermal shutdown turns off the driver. If Pin 15 (O.V. Latch Output) is tied to Pin 14 (Compensation/Shutdown) the
O.V. Latch will be reset.
3
UC1834
UC2834
UC3834
Unless otherwise stated, these specifications apply for TA=−55°C to +125°C
for the UC1834, −40°C to +85°C for the UC2834, and 0°C to +70°C for the
UC3834. VIN+ = 15V, VIN− = 0V. TA = TJ
ELECTRICAL CHARACTERISTICS:
UC1834
UC2834
UC3834
UNITS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX MIN
TYP MAX
Current Sense Amplifier Section
Threshold Voltage
Pin 4 Open, VCM = VIN+ or VIN−
Pin 4 = 0.5V, VCM = VIN+ or VIN−
130
40
150
50
170
60
120
30
150
50
180
70
mV
Threshold Supply Sensitivity Pin 4 Open, VCM = VIN−, VIN+ = 5 to 35V
−0.1 −0.3
−0.1 −0.5
%/V
µA
Adj. Input Current
Pin 4 = 0.5V
VCM = VIN+
VCM = VIN−
−2
−10
−2
−10
Sense Input Bias Current
100
200
100
200
µA
−100 −200
−100 −200
Current Sense Threshold Adjustment
Current Limiting Knee Characteristics
Differential Voltage at Current Sense
Inputs - mV (reference to sense − input)
Error Amplifier Gain and Phase
Frequency Response
Current Sense Amplifier Gain and Phase
Frequency Response
4
UC1834
UC2834
UC3834
APPLICATION INFORMATION
Foldback Current Limiting
Both the current sense and error amplifiers on the UC1834 The crowbar output on the UC1834 is activated following a
are transconductance type amplifiers. As a result, their volt- sustained over-voltage condition. The crowbar output remains
age gain is a direct function of the load impedance at their high as long as the fault condition persists, or, as long as the
shared output pin, Pin 14. Their small signal voltage gain as over-voltage latch is set. The latch is set with an over-voltage
a function of load and frequency is nominally given by;
fault if the voltage at Pin 15 is above the latch reset threshold,
typically 0.4V. When the latch is set, its Q− output will pull Pin
15 low through a series diode. As long as a nominal pull-up
load exists, the series diode prevents Q− from pulling Pin 15
below the reset threshold. However, Pin 15 is pulled low
enough to disable the driver outputs if Pins 15 and 14 are
tied together. With Pin 15 and 14 common, the regulator
will latch off in response to an over-voltage fault. If the
fault condition is cleared and Pins 14 and 15 are momen-
tarily pulled below the latch reset threshold, the driver out-
puts are re-enabled.
ZL (f)
ZL (f)
70Ω
AV E ⁄ A =
and AV C. S. ⁄ A =
700Ω
for: f ≤ 500kHz and |ZL(f)| ≤ 1 MΩ
Where:
AV=Small Signal Voltage Gain to pin 14.
ZL(f) = Load Impedance at Pin 14.
The UC1834 fault delay circuitry prevents the fault outputs
from responding to transient fault conditions. The delay reset
latch insures that the full, user defined, delay passes before an
over-voltage fault response occurs. This prevents unnecessary
crowbar, or latched-off conditions, from occurring following
sharp under-voltage to over-voltage transients.
Setting the Threshold Adjust Voltage (VADJ)
5
UC1834
UC2834
UC3834
TYPICAL APPLICATIONS
5-10 Amp Positive Regulator
5-10 Amp Negative Regulator
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
6
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
LCCC
CDIP
CDIP
CDIP
CDIP
CDIP
LCCC
LCCC
LCCC
SOIC
Drawing
5962-87742012A
5962-8774201EA
5962-8774201V2A
5962-8774201VEA
UC1834J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
20
16
16
16
16
16
20
20
20
16
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
FK
J
Call TI
J
A42 SNPB
Call TI
UC1834J/81025
UC1834J883B
UC1834JQMLV
UC1834L
J
J
1
A42 SNPB
Call TI
Level-NC-NC-NC
Call TI
J
FK
FK
FK
DW
1
1
POST-PLATE Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC
UC1834L883B
UC1834LQMLV
UC2834DW
Call TI
Call TI
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2834DWG4
UC2834DWTR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2834DWTRG4
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2834J
UC2834N
ACTIVE
ACTIVE
CDIP
PDIP
J
16
16
1
TBD
A42 SNPB
Level-NC-NC-NC
N
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC2834NG4
ACTIVE
PDIP
N
16
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC2834Q
UC2834QTR
UC3834DW
ACTIVE
ACTIVE
ACTIVE
PLCC
PLCC
SOIC
FN
FN
20
20
16
46
TBD
TBD
Call TI
Call TI
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
1000
DW
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3834DWG4
UC3834DWTR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3834DWTRG4
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3834J
UC3834N
ACTIVE
ACTIVE
CDIP
PDIP
J
16
16
1
TBD
A42 SNPB
Level-NC-NC-NC
N
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC3834NG4
ACTIVE
PDIP
N
16
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UC3834Q
ACTIVE
ACTIVE
PLCC
PLCC
FN
FN
20
20
46
TBD
TBD
Call TI
Call TI
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
UC3834QTR
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
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