UC3854BDWTR [TI]
Power Factor Controller ; 功率因数控制器\n
| 型号： | UC3854BDWTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Power Factor Controller
|
| 文件： | 总7页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1854A/B
UC2854A/B
UC3854A/B
Enhanced High Power Factor Preregulator
FEATURES
DESCRIPTION
•
Controls Boost PWM to Near Unity
The UC1854A/B products are pin compatible enhanced versions of the
UC1854. Like the UC1854, these products provide all of the functions
necessary for active power factor corrected preregulators. The
controller achieves near unity power factor by shaping the AC input line
current waveform to correspond to the AC input line voltage. To do this
the UC1854A/B uses average current mode control. Average current
mode control maintains stable, low distortion sinusoidal line current
Power Factor
•
•
•
•
Limits Line Current Distortion To <3%
World-Wide Operation Without Switches
Accurate Power Limiting
Fixed Frequency Average Current Mode without the need for slope compensation, unlike peak current mode
Control
control.
•
•
•
High Bandwidth (5MHz), Low Offset
Current Amplifier
The UC1854A/B products improve upon the UC1854 by offering a wide
bandwidth, low offset Current Amplifier, a faster responding and
improved accuracy enable comparator, a VREF "good" comparator,
UVLO threshold options (16/10V for offline, 10.5/10V for startup from
an auxiliary 12V regulator), lower startup supply current, and an
enhanced multiply/divide circuit. New features like the amplifier output
clamps, improved amplifier current sinking capability, and low offset
VAC pin reduce the external component count while improving
performance. Improved common mode input range of the Multiplier
output/Current Amp input allow the designer greater flexibility in
choosing a method for current sensing. Unlike its predecessor, RSET
controls only oscillator charging current and has no effect on clamping
the maximum multiplier output current. This current is now clamped to
Integrated Current and Voltage Amp
Output Clamps
Multiplier Improvements: Linearity,
500mV VAC Offset (eliminates external
resistor), 0-5V Multout Common Mode
Range
•
•
VREF "GOOD" Comparator
Faster and Improved Accuracy ENABLE
Comparator
a maximum of 2 IAC at all times which simplifies the design process
and provides foldback power limiting during brownout and extreme low
line conditions.
*
•
•
UVLO Threshold Options
(16/10V / 10.5/10V)
300µA Startup Supply Current
A 1% 7.5V reference, fixed frequency oscillator, PWM, Voltage
Amplifier with softstart, line voltage feedforward (VRMS squarer), input
supply voltage clamp, and over current comparator round out the list of
features.
UVLO Turn on UVLO Turn off
UC1854A
UC1854B
16V
10V
10V
10.5V
BLOCK DIAGRAM
UDG-93001-1
6/98
UC1854A/B
UC2854A/B
UC3854A/B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
GT Drv Current, Continuous. . . . . . . . . . . . . . . . . . . . . . . 0.5A
GT Drv Current, 50% Duty Cycle. . . . . . . . . . . . . . . . . . . . 1.5A
Input Voltage, VSENSE, VRMS . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage, ISENSE, Mult Out . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Input Current, RSET, IAC, PKLMT, ENA . . . . . . . . . . . . . . 10mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . +300°C
Note 1: All voltages with respect to Gnd (Pin 1).
Note 2: All currents are positive into the specified terminal.
Note 3: ENA imput is internally clamped to approximately 10V.
Note 4: Consult Unitrode Integrated Circuits databook for
information regarding thermal specifications and limitations of
packages.
CONNECTION DIAGRAMS
PACKAGE PIN FUNCTION
DIL–16 & SOIC-16
(Top View)
J, N & DW Packages
PLCC-20 & LCC-20
(Top View)
Q & L Packages
FUNCTION
N/C
PIN
1
Gnd
2
PKLMT
CA Out
ISENSE
N/C
Mult Out
IAC
3
4
5
6
7
8
VA Out
VRMS
N/C
VREF
ENA
VSENSE
RSET
N/C
SS
CT
VCC
GT Drv
9
10
11
12
13
14
15
16
17
18
19
20
Unless otherwise stated, VCC=18V, RT=8.2k, CT=1.5nF, PKLMT=1V, VRMS=1.5V,
IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=3V, –55oC<TA<125oC
for the UC1854A/B, –40oC<TA<85oC for the UC2854A/B, and 0oC<TA<70oC for the
UC3854A/B, and TA=TJ.
ELECTRICAL CHARACTERISTICS
PARAMETER
OVERALL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Supply Current, Off
Supply Current, On
VCC Turn-On Threshold
CAO, VAO = 0V, VCC = UVLO - 0.3V
250
12
400
18
µA
mA
V
UC1854A
16
17.5
11.2
UC1854B
10.5
10
V
VCC Turn-Off Threshold
VCC Clamp
UC1854A / B
I(VCC) = ICC(on) + 5mA
9
V
18
20
22
V
VOLTAGE AMPLIFIER
Input Voltage
2.9
–500
70
3.0
–25
100
6
3.1
V
nA
dB
V
VSENSE Bias Current
Open Loop Gain
500
VOUT = 2 to 5V
VOUT High
ILOAD = –500µA
VOUT Low
ILOAD = 500µA
0.3
1.5
1
0.5
3.5
V
Output Short Circuit Current
Gain Bandwidth Product
VOUT = 0V
mA
mHz
Fin = 100kHz, 10mV p-p, (Note 1)
2
UC1854A/B
UC2854A/B
UC3854A/B
Unless otherwise stated, VCC=18V, RT=8.2k, CT=1.5nF, PKLMT=1V, VRMS=1.5V,
ELECTRICAL
CHARACTERISTICS (cont.)
IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=3V, –55oC<TA<125oC for the
UC1854A/B, –40oC<TA<85oC for the UC2854A/B, and 0oC<TA<70oC for the UC3854A/B,
and TA=TJ.
PARAMETER
CURRENT AMPLIFIER
Input Offset Voltage
TEST CONDITIONS
MIN
TYP
MAX UNITS
VCM = 0V
TA = +25°C
−4
–5.5
–500
80
0
0
mV
mV
nA
dB
V
OverTemp
Input Bias Current(sense)
Open Loop Gain
VCM = 0V
500
VCM = 0V, VOUT = 2 to 6V
ILOAD = –500µA
ILOAD = 500µA
VOUT = 0V
110
8
VOUT High
VOUT Low
0.3
1.5
0.5
3.5
5
V
Output Short Circuit Current
Common Mode Range
Gain Bandwidth Product
REFERENCE
mA
V
–0.3
3
Fin = 100kHz, 10mV p-p, (Note 1)
5
mHz
Output Voltage
IREF = 0mA, TA = 25oC
IREF = 0mA
7.4
7.35
0
7.5
7.5
8
7.6
7.65
20
V
V
Load Regulation
IREF = 1 to 10mA
VCC = 12 to 18V
VREF = 0V
mV
mV
mA
Line Regulation
0
14
35
25
Short Circuit Current
OSCILLATOR
25
60
Initial Accuracy
TA = 25oC
85
100
1
115
kHz
%
Voltage Stability
VCC = 12 to 18V
Line, Temp
Total Variation
80
4.9
0.8
120
5.9
1.3
kHz
V
Ramp Amplitude (p-p)
Ramp Valley Voltage
ENABLE / SOFTSTART / CURRENT LIMIT
Enable Threshold
V
2.35
2.55
500
–2
2.8
600
–5
V
Enable Hysteresis
VFAULT = 2.5V
VENABLE = 0V
mV
µA
ns
Enable Input Bias Current
Propagation Delay to Disable
SS Charge Current
Enable Overdrive = –100mV,(Note 1)
VSOFTSTART = 2.5V
300
14
10
24
15
PKLMT Offset Voltage
PKLMT Input Current
PKLMT Propagation Delay
MULTIPLIER
–15
mV
µA
ns
VPKLMT = –0.1V
(Note 1)
–200 –100
150
Output Current - IAC Limited
Output Current - Zero
Output Current - Power Limited
Output Current
IAC=100µA, VRMS = 1V, RSET = 10k
IAC=0µA, RSET = 10k
–220 –200 –170
–2.0 –0.2 2.0
µA
µA
µA
µA
µA
µA
µA
A/A
VRMS = 1.5V, Va = 6V
–230 –200 –170
VRMS = 1.5V, Va = 2V
–22
–156
–2
VRMS = 1.5V, Va = 5V
VRMS = 5V, Va = 2V
VRMS = 5V, Va = 5V
–14
Gain Constant
(Note 2) VRMS = 1.5V, TJ = 25°C, Va = 6V
–1.1
–1.0
–0.9
Note 1: Guaranteed by design, not 100% tested in production.
IAC × (Va − 1.5V)
VRMS 2 × IMO
Note 2: Gain constant (K) =
3
UC1854A/B
UC2854A/B
UC3854A/B
Unless otherwise stated, VCC=18V, RT=8.2k, CT=1.5nF, PKLMT=1V, VRMS=1.5V, IAC=100µA,
ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=3V, –55oC<TA<125oC for the UC1854A/B,
–40oC<TA<85oC for the UC2854A/B, and 0oC<TA<70oC for the UC3854A/B, and TA=TJ.
ELECTRICAL
CHARACTERISTICS (cont.)
PARAMETER
GATE DRIVER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Output High Voltage
Output Low Voltage
IOUT = –200mA, VCC = 15V
12
12.8
1
V
IOUT = 200mA
2.2
500
1.5
V
mV
V
IOUT = 10mA
300
0.9
35
Output Low (UVLO)
Output Rise / Fall Time
Output Peak Current
IOUT = 50mA, VCC = 0V
CLOAD = 1nF, (Note 1)
CLOAD = 10nF, (Note 1)
ns
A
1.0
Note 1: Guaranteed by design, not 100% tested in production.
IAC × (Va − 1.5V)
VRMS 2 × IMO
Note 2: Gain constant (K) =
FUNCTIONAL DESCRIPTION
The UC1854A/B products were designed as pin VRMS should produce 1.5V at low line (85VAC). This will
compatible upgrades to the industry standard UC1854 put 4.77V on VRMS at high line (27VAC) which is well
active Power Factor correction circuits. The circuit within its operating range.
enhancements allow the user to eliminate in most cases
The Voltage Amplifier output forms the third input to the
several external components currently required to
Multiplier and is internally clamped to 6.0V. This
successfully apply the UC1854. In addition, linearity
eliminates an external zenerclamp often used in UC1854
improvements to the Multiply, Square, and Divide circuitry
designs. The offset voltage at this input to the Multiplier
optimizes overall system performance. Detailed
has been raised on the UC1854A/B to 1.5V.
descriptions of the circuit enhancements are provided
The Multiplier output pin, which is also common to the
Current Amplifier non-inverting input, has a −0.3V to 5.0V
output range,compared to the −0.3 to 2.5V range of the
UC1854. This improvement allows the UC1854A/B to be
used in applications where the current sense signal
amplitude is very large.
below. For in-depth design applications reference data
refer to Unitrode application notes U-134 and DN-44.
MULTIPLY / SQUARE AND DIVIDE
The UC1854A/B Multiplier design maintains the same
gain constant (K = −1), as the UC1854. The relationship
between the inputs and output current is given as:
VOLTAGE AMPLIFIER
2
IMO = IAC(VAO - 1.5V) / K• VRMS
The UC1854A/B Voltage Amplifier design is essentially
similar to the UC1854 with two exceptions. The first is with
the internal connection. The lower voltage reduces the
amount of charge on the compensation capacitor, which
provides improved recovery from large signal events,
such as line dropouts, or power interruption. It also
minimizes the DC current flowing through the feedback.
The output of the Voltage amplifier is also changed. In
addition to a 6.0V temperature compensated clamp, the
output short circuit current has been lowered to 2mA
typical, and an active pull down has replaced the passive
This is nearly the same as the UC1854, but circuit
differences have improved the performance and
application.
The first difference is with the IAC input. The UC1854A/B
regulates this pin voltage to a nominal 500mV over the full
operating temperature range, rather than the 6.0V used
on the UC1854. This low offset voltage eliminates the
need for a line zero crossing compensating resistor to
VREF from IAC that UC1854 designs require. The
maximum current at high line into IAC should be limited to
250µA for best performance. Therefore, if VAC (max) = pulldown of the UC1854.
270V, then RAC = 270(1.414) / 250µA = 1.53MΩ.
CURRENT AMPLIFIER
The VRMS pin linear operating range is improved with the
The Current Amplifier for an average current PFC
UC1854A/B as well. The input range for VRMS extends
from 0 to 5.5V. Since the UC1854A squaring circuit
employs an analog multiplier, rather than a linear
approximation, accuracy is improved, and discontinuities
are eliminated. The external divider network connected to
controller needs a low offset voltage in order to minimize
AC line current distortion. With this in mind, the
UC1854A/B Current Amplifier has improved the input
±
offset voltage from 4mV to 0 to −3mV. The negative
4
UC1854A/B
UC2854A/B
UC3854A/B
FUNCTIONAL DESCRIPTION (cont.)
offset of the UC1854A/B guarantees that the PWM circuit
will not drive the MOSFET if the current command is zero
(both Current amplifier inputs zero.).Previous designs
required an external offset cancellation network to
implement this key feature. The bandwidth of the Current
Amplifier has been improved as well to 5mHz typical.
While this is not generally an issue at 50 or 60Hz inputs, it
is essential for 400Hz input avionics applications.
desired. The lower startup supply current (250µA typical),
substantially reduces the power requirements of an offline
startup resistor. The 10.5/10V UVLO option (UC1854B)
enables the controller to be powered off of an auxiliary
12V supply.
The VREF "GOOD" comparator guarantees that the
MOSFET driver output remains low if the supply or the
7.5V reference are not yet up. This improvement
eliminates the need for external Schottky diodes on the
PKL and CA+ pins that some UC1854 designs require.
The propagation delay of the disable feature has been
improved to 300ns typical. This delay was proportional to
MISCELLANEOUS
Several other important enhancements have been
implemented in the UC1854A/B. A VCC supply voltage
clamp at 20V allows the controller to be current fed if
TYPICAL CHARACTERISTICS at TA = TJ = 25°C
Gate Drive Rise and Fall Time
Gate Drive Maximum Duty Cycle
700
100%
600
95%
90%
Rise Time
500
Fall Time
400
ns
Duty
85%
Cycle
300
200
100
0
80%
75%
70%
0
0.01
0.02
0.03
0.04
0.05
1
10
100
Load Capacitance,
µF
R
SET, k Ω
UC1854A/B Multiplier Linearity
VAOUT = 3.5V
UC1854A/B Multiplier Linearity
VAOUT = 5V
1.2
1.16
1.12
1.08
1.04
1
1.2
1.16
1.12
1.08
1.04
1
V
5.0V
RMS=
V
5.0V
RMS=
V
3.0V
RMS=
V
3.0V
RMS=
V
1.5V
RMS=
V
1.5V
RMS=
K
K
0.96
0.92
0.88
0.84
0.8
0.96
0.92
0.88
0.84
0.8
0
50
100
150
200
250
0
50
100
150
A)
200
250
IAC Current (µA)
I
AC Current (µ
5
UC1854A/B
UC2854A/B
UC3854A/B
TYPICAL CHARACTERISTICS at TA = TJ = 25°C (cont.)
Current Amplifier Frequency Response
Oscillator Frequency vs RSET and CT
1000
5.992 496 516 MHz
120
Gain
-90
100
80
60
40
20
0
Phase
-45 Phase
Degrees
0
100pF
200pF
Frequency
kHz
100
500pF
1nF
2nF
-20
-40
-60
5nF
3nF
10nF
10
10
1
100
10kHz
100kHz
1MHz
log f
10MHz
R
SET, k Ω
Voltage Amplifier Gain and Phase vs Frequency
120
Phase
Margin
100
80
60
40
20
0
degrees
Open-Loop
Gain
dB
-20
0.1
1
10
100
1000
10000
Frequency
kHz
UNITRODE CORPORATION
•
7 CONTINENTAL BLVD. MERRIMACK, NH 03054
These products contain patented circuitry and are sold under license from Pioneer Magnetics, Inc.
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TEL. (603) 424-2410 FAX (603) 424-3460
6
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