UC3870QTR-2 [TI]
1A SWITCHING CONTROLLER, 300kHz SWITCHING FREQ-MAX, PQCC20, PLASTIC, LCC-20;
| 型号： | UC3870QTR-2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A SWITCHING CONTROLLER, 300kHz SWITCHING FREQ-MAX, PQCC20, PLASTIC, LCC-20 开关 |
| 文件： | 总10页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
High Efficiency, Synchronous, Step-down (Buck) Controllers
FEATURES
DESCRIPTION
Not Recommended for New Designs.
• Operation to 36V Input Voltage
The UC3870 family of synchronous step-down (Buck) regulators provides
high efficiency power conversion from an input voltage range of 4.5 to 36
volts. The UC3870 is tailored for battery powered applications such as lap-
top computers, consumer products, communications systems, and aero-
space which demand high performance and long battery life. The
synchronous regulator replaces the catch diode in the standard buck regu-
lator with a low Rds(on) N-channel MOSFET switch allowing for significant
efficiency improvements. The high side N-channel MOSFET switch is
driven out of phase from the low side N-channel MOSFET switch by an
on-chip bootstrap circuit which requires only a single external capacitor to
develop the regulated gate drive. Fixed frequency, average current mode
control provides the regulator with inherent slope compensation, tight regu-
lation of the output voltage, and superior load and line transient response.
Switching frequencies up to 300kHz are possible.
• Fixed Frequency Average Current
Mode Control
• 2V to 3.5V Output Voltage when
Combined with UC3910 Precision
Reference/DAC
• Drives External N-Channel MOSFETs
for Highest Efficiency
• Sleep Mode Current <75mA
• Complementary 1 Amp Outputs with
Regulated Gate Drive Voltage
• LDO (Low Drop Out) Virtual 100%
The UC3870-1,-2 is designed to interface directly with precision references
like the UC3910. When combined with the UC3910, output voltages be-
tween 2V to 3.5V in 100mV increments and ± 1% accuracy are attainable.
This makes the UC3870-1,-2 ideal for powering high performance micro-
processors like the Intel Pentium Pro and others.
Duty Cycle Operation
• Non-Overlapping Gate Drives
(continued)
BLOCK DIAGRAM
UDG-96158
Pin Numbers refer to the DIL-18 Package.
8/98
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
DESCRIPTION (continued)
A low power sleep mode can be invoked through the SS thresholds of 10V and 9V respectively. A precision 2.5V
pin. Quiescent supply current in sleep mode is typically reference can supply 20mA to external circuitry. An error
amplifier with soft start, high bandwidth current amplifier,
and a synchronizable oscillator are additional features.
less than 50mA. Two UVLO options are available. The
UC3870-1 is designed for logic level MOSFETs and has
UVLO turn-on and turn-off thresholds of 4.5V and 4.4V
respectively. The UC3870-2 is designed for standard
power MOSFETs and has UVLO turn-on and turn-off
Available packages include 18-pin plastic and ceramic
DIP (N, J), 18-pin SOIC (DW), and 20-pin plastic and
ceramic leadless chip carriers (Q, L).
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Boost Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V
OUTPUT Drivers (HDRIVE, LDRIVE) Currents
DIL-18 (TOP VIEW)
J or N, DW Packages
(continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.25A
(peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A
VREF Current. . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Inputs (VSNS, SS, COMP, CT) . . . . . . . . . . . . . . . . –0.3 to 10V
Inputs (CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 7.5V
Inputs (ISNS+, ISNS-) . . . . . . . . . . . . . . . . . . . . . . . –0.3 to20V
Outputs (CAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to10V
Soft start Sinking Current . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
All currents are positive into, negative out of the specified ter-
minal. All voltages are referenced to GND. Consult Packaging
Section of Databook for thermal limitations and considerations
of packages.
PLCC-20 (TOP VIEW)
J or N, DW Packages
PLCC-20 (TOP VIEW)
J or N, DW Packages
2
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
ORDERING INFORMATION
UVLO Turn
On/Off
Threshold
Temperature
Range
Package
1: 4.5V/4.4V
2: 10V/9V
J: Ceramic DIL-18
N: Plastic DIL-18
DW: SOIC-18
1: –55°C to +125°C
2: –40°C to +85°C
3: 0°C to +70°C
ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = –55°C to +125°C for
UC1870X; –25°C to +85°C for UC2870X; 0°C to +70°C for UC3870X; VCC = 12V, CT = 680pF, CCAP = 1mF; CBOOT = 0.1mF,
TA = TJ.
PARAMETER
Overall Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Supply Current, Sleep
Supply Current, Operating
VCC Turn-on Threshold
SOFTSTART=0V; TA = 25°C
30
8.5
10
4.5
9
75
12
mA
mA
V
UCX870-2
UCX870-1
UCX870-2
UCX870-1
10.5
4.8
V
VCC Turn-off Threshold
8.5
4.1
V
4.4
V
Voltage Amplifier Section
Input Voltage Offset
VSNS Bias Current
TA = 25°C
–30
–500
400
0
30
mV
nA
25
500
Transconductance
ICOMP = +10mA to –10mA; UC3870 -1, -2;
675
1000 mMho
UC2870 -1, -2;
I
COMP = +5mA to –5mA; UC1870 -1, -2
250
2.9
675
3.1
0.15
35
1250 mMho
VOUT High
3.25
1
V
V
VOUT Low
Output Source Current
VOUT = 1V; UC3870 -1, -2; UC2870 -1, -2;
VOUT = 1V; UC1870 -1, -2
10
5
mA
mA
35
Current Amplifier Section
Input Offset Voltage
Input Bias Current(sense)
Open Loop Gain
VCOMP = 2.5V
–6
–500
80
0
6
mV
nA
dB
V
VCM = 2.5V
500
VCM = 2.5V, VOUT = 1V to 3.5V
RCAOUT = 100k to GND, TA = 25°C
RCAOUT = 100k to VREF, TA = 25°C
VOUT = 0V, TA = 25°C
VCM = 2V to 3V
110
3.7
0.7
100
90
VOUT High
3.6
VOUT Low
0.86
120
V
Output Source Current
Common Mode REJ Ratio
Gain Bandwidth Product
Reference Section
Output Voltage
80
70
2
mA
dB
MHz
FIN = 100kHz, 10mV p-p
3.5
IREF = 0mA, TA = 25°C
IREF = 0mA
2.462
2.437
2.5
2.5
2
2.538
2.563
±15
V
V
Load Regulation
Line Regulation
IREF = 0mA to 5mA
VCC = 12V to 24V
VREF = 0V
mV
mV
mA
2
±15
Short Circuit Current
10
20
25
3
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for TA = –55°C to +125°C for
UC1870X; –25°C to +85°C for UC2870X; 0°C to +70°C for UC3870X; VCC = 12V, CT = 680pF, CCAP = 1mF; CBOOT = 0.1mF,
TA = TJ.
PARAMETER
Oscillator Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Initial Accuracy
TA = 25°C
85
100
1
115
1.5
kHz
%
Voltage Stability
VCC = 12V to 18V
Line, Temperature
TA = 25°C
Total Variation
80
120
2.85
kHz
V
Ramp Amplitude (p-p)
Ramp Valley Voltage
Sleep/Soft Start/Bootstrap Section
Sleep Threshold
2.48
0.86
2.7
TA = 25°C
0.95
V
Measured on SS, TA = 25°C
VSS = 2.5V
0.25
4
0.6
6
0.8
10
V
mA
mA
V
SS Charge Current
SS Discharge Current
Bootstrap Regulation Voltage
VSS = 2.5V
0.5
9.5
6
0.8
10.2
7.5
8
UCX870-2, Low Driver ON
UCX870-1, Low Driver ON
UCX870-2, VCAOUT > VCTpeak
UCX870-1, VCAOUT > VCTpeak
12.5
9
9
4
V
Bootstrap Refresh Voltage
7
V
2.7
3.5
V
High Side Driver Output Section
Output High Voltage
IOUT = –50mA, BOOT = 23V
IOUT = 50mA
21
22.2
1
V
V
Output Low Voltage
2.2
500
1.5
IOUT = 10mA
300
0.9
40
mV
V
Output Low (UVLO)
Output Rise Time
IOUT = 50mA, VCC = 0V
COUT = 1nF
160
100
ns
ns
Output Fall Time
COUT = 1nF
30
Low Side Driver Output Section
Output High Voltage
Output Low Voltage
IOUT = –50mA, VCAP = 11V
IOUT = 50mA
8.8
9.5
1
V
V
2.2
500
1.5
IOUT = 10mA
300
0.9
40
mA
V
Output Low (UVLO)
Output RISE/FALL Time
Output FALL Time
X10 Amplifier Section
Gain
IOUT = 50mA, VCC = 0V
CLOAD = 1nF
160
100
ns
ns
COUT = 1nF
30
VISNS ± VISNS = 20mV to 80mV
9.2
1
10
1.4
3.5
100
10.4
165
V/V
V/ms
V/ms
k/W
Slew Rate Rising
Slew Rate Falling
Input Resistance
TA = 25°C
TA = 25°C
TA = 25°C
2
60
4
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
PIN DESCRIPTIONS
BOOT: This pin provides the high side rail for the COMP: This is the output of the voltage amplifier. It pro-
HDRIVE output. An external capacitor (Cbst) is vides the current command signal to the current ampli-
connected between this pin and the drain of the external fier. The voltage is clamped to approximately 3.2V.
low side MOSFET. When the low side MOSFET is
CMD: This is the non-inverting input of the voltage error
conducting Cbst is charged to 11V (UC3870-2), 7.5V
amplifier. The voltage applied to CMD sets the output
(UC3870-1), via an external diode tied to CAP. When the
voltage of the power converter. The 2V to 3.5V input
low side MOSFET turns off and the high side MOSFET
common mode range allows for direct interfacing to the
turns on, the Cbst bootstraps itself up with the source of
UC3910 DAC/precision reference.
high side MOSFET, ultimately providing a 10V Vgs for the
CT: A capacitor from CT to GND sets the PWM oscillator
frequency according to the following equation:
upper MOSFET. Since this 10V is referenced to the
source of the high side N-channel MOSFET, the actual
voltage on BOOT and HDRIVE is approximately 10V
above VCC while the high side MOSFET is conducting.
The voltage on BOOT is continuously monitored during
low input voltage conditions when the duty cycle equals
approximately 100% to insure that a sufficient gate drive
level is being supplied by the UC3870. If the voltage on
BOOT falls below 8V (UC3870-2) or 3.5V (UC3870-1),
the IC forces the low side driver to cycle itself on for the
few cycles required to replenish Cbst. In this way, virtual
100% duty cycle operation is provided.
1
F =
.
14250·CT
Use a high quality ceramic capacitor with low ESL and
ESR for best results. A minimum CT value of 220pF in-
sures good accuracy and less susceptibility to circuit lay-
out parasitics. The oscillator and PWM are designed to
provide practical operation to 300kHZ.
GND: All voltages are measured with respect to this pin.
All bypass capacitors and timing components except
those listed under the PGND pin description should be
connected to this pin. Component leads should be as
short and direct as possible.
CA-: This is the inverting input to the current amplifier.
Connect a series resistor and capacitor between this pin
and CAO to set the current loop compensation. An input
resistor between this pin and ISOUT provides the induc-
tor current sense signal to the amplifier and also sets the
high frequency gain of the amplifier. The common mode
operating range for this input is between GND and 4V.
The normal range during operation is between 2V and
3V.
HDRIVE, LDRIVE: The outputs of the PWM are totem
pole MOSFET gate drivers on the HDRIVE and LDRIVE
pins. The outputs can sink approximately 1A and source
500mA. This characteristic optimizes the switching tran-
sitions by providing a controlled dV/dT at turn-on and a
lower impedance at turn-off. These are complementary
outputs with a typical deadtime of 200ns. Internal cir-
cuitry prevents the possibility of simultaneous conduction
of the output MOSFETs (shoot through). HDRIVE is the
high side bootstrapped output. Its upper power supply
rail is the BOOT pin which means that its output will fly
approximately 10V above VCC when the upper side of
the totem pole output is conducting. The power supply
rail for LDRIVE is CAP. As a result the Vgs of both gates
are regulated to approximately 10V if VCC is >11V. A
series resistor between these pins and the MOSFET
gates of at least 10 ohms can be used to control ringing.
Additionally, a low VF Schottky diode should be con-
nected between these pins and GND to prevent sub-
strate conduction and possible erratic operation.
CAO: This is the output of the wide bandwidth current
amplifier and one of the inputs to the PWM duty cycle
comparator. The output signal generated by this amplifier
commands the PWM to force the correct duty cycle to
maintain output voltage in regulation. The output can
swing from 0.1V to 4V.
CAP: A capacitor is normally connected between this pin
and GND providing bypass for the internal 11V
(UC3870-2) and 7.5V (UC3870-1) regulator. Charge is
transferred from this capacitor to Cbst via an external di-
ode when the low side MOSFET is conducting. If VCC ≤
10V logic level MOSFETs are generally specified. CAP
should then be shorted to VCC in conjuncton with a low
VF Schottky to BOOT to maximize the gate drive ampli-
tude. This technique provides adequate gate drive signal
amplitudes with VCC as low as 4.5V. For high input volt-
age applications, a simple external shunt zener regulator
circuit can be connected to CAP, thereby offloading
power dissipation requirements from the IC to an external
transistor.
ISNS–: This is the inverting input to the X10 instrumen-
tation amplifier. The common mode input range for this
pin extends from GND to VCC. A low value resistor in se-
ries with the output inductor is connected between this
pin and ISNS+ to develop the current sense signal.
5
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
PIN DESCRIPTIONS (continued)
Once the device has completed its soft start cycle, a low
power sleep mode can be invoked by pulling SS below
0.5V typically. In sleep mode, all of the device functions
are disabled except for those which are required to bring
the device out of sleep mode when SS is released. Typi-
cal sleep mode supply current is less than 50mA.
ISNS+: This is the non-inverting input to the X10 instru-
mentation amplifier. The common mode input range for
this pin extends from GND to VCC.
ISOUT: This is the output of the X10 instrumentation am-
plifier. The output voltage on this pin is level shifted 2V
above GND, such that if a 100mV differential input is ap-
plied across ISNS+ and ISNS–, the output will be 3V.
VCC: Positive supply rail for the IC. Bypass this pin to
GND with a 1mF low ESL/ESR ceramic capacitor. The
maximum voltage for VCC is 36V. The turn on voltage
level on VCC is 4.5V with 100mV of hysteresis for the
UC3870-1 and 10V with 1V of hysteresis for the
UC3870-2.
PGND: This is the high current ground for the IC. The
MOSFET driver transistors are referenced to this ground.
For best performance an external star ground connection
should be made between this pin, the source of the low
side MOSFET, the capacitor on CAP, the anodes of any
external Schottky clamp diodes and the output filter ca-
pacitor. As with all high frequency layouts, a ground plane
and short leads are highly recommended.
VREF: V
is the output of the precision reference.
REF
The output is capable of supplying 20mA to peripheral
circuitry and is internally short circuit current limited.
VREF is disabled and low whenever VCC is below the
UVLO threshold, and when SS is pulled below 0.5V. A
VREF “good” comparator senses VREF and disables the
PWM stage until VREF has attained approximately 90%
of its nominal value. Bypass VREF to GND with a 0.1mF
ceramic capacitor for best performance.
SS: A capacitor from this pin to GND in conjunction with
an internal 10mA current source provides a soft start
function for the IC. The voltage level on SS clamps the
output of the voltage amplifier through an internal buffer,
thus providing a controlled startup. The SS time is ap-
proximately:
VSNS: This pin is the inverting input of the voltage am-
plifier and serves as the output voltage feedback point
for the synchronous regulator. It senses the output volt-
age through a voltage divider which produces a nominal
2V.
æ
ö
V
ç
÷
· 3V
C
·
ç
÷
V
è
ø
10µA
APPLICATIONS INFORMATION
The UC3870 employs a fixed frequency average current drop out (LDO) modes. The output of the X10 instrumen-
mode control buck topology to convert a higher battery tation amplifier is applied to the inverting input of the cur-
voltage down to a tightly regulated output voltage. Spe- rent amplifier through an external resistor. The
cial design techniques allow this bipolar IC to deliver ex- converter’s output voltage feedback is applied to the
ceptional performance while consuming approximately VSNS pin through an external voltage divider. The differ-
6mA of supply current over an input voltage range of 4.5 ence between the voltage at VSNS and the voltage at
to 35 volts. Fixed frequency operation allows synchroni- the non-inverting input is amplified by the voltage ampli-
zation to an existing system clock, and easier filtering. fier and applied to the non-inverting input of the current
Average current mode control provides inherent slope amplifier. This instantaneous reference level forms the
compensation and accurate short circuit current limiting.
current command input for the average current control
loop. The average current amplifier develops the duty cy-
cle command signal by integrating the current feedback
signal with respect to the instantaneous current com-
mand input. This output is compared to the fixed high
amplitude oscillator ramp waveform at the inputs of the
PWM comparator to develop duty cycle information for
the PWM drive. The large amplitude oscillator ramp pro-
vides both high noise margin and built-in slope compen-
sation in average current mode control methodology. The
fixed frequency oscillator is programmed with a single ex-
The output inductor current is sensed by an external low
value shunt resistor (R
). This signal at full load
SENSE
current should be no larger than 100mV in order to mini-
mize sensing losses. The differential voltage across
Rsense is amplified by the internal X10 instrumentation
amplifier. The common mode input range for this ampli-
fier extends from GND to VCC in order to maintain accu-
rate current sensing under normal conditions as well as
abnormal conditions such as output short circuit and low
6
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
APPLICATION INFORMATION (continued)
UDG-96159
Figure 1. Typical Application: UC3870-1, -2 Pentium Pro Power Converter
ternal capacitor connected between CT and GND, and is chronous regulator must be capable of LDO or 100%
capable of switching frequencies up to 300kHz. The duty cycle operation. The UC3870 includes circuitry to
UC3870 can be synchronized to an external clock by ca- insure that this mode of operation is possible even
pacitively coupling the signal to the junction of the ca- though it uses a bootstrapped drive technique for the
pacitor at CT and a low value resistor tied to GND. Refer high side MOSFET. During commanded 100% duty cycle
to Application Note U-111.
operation, the UC3870 monitors the V drive signal ap-
GS
plied to the high side MOSFET, and automatically pro-
vides complementary pulses to refresh the bootstrap
capacitor when this voltage falls below a set threshold. In
this way, near 100% duty cycle operation is possible, with
effective duty cycle dependent only upon the value of
The PWM drive signal is applied to the complementary
output driver stages. Since the high side switch is an
N–channel MOSFET, a means for driving its gate above
VCC is required. This is accomplished via the internal
11V (UC3870-2)/7.5V (UC3870-1) regulator and an ex-
C
.
BST
ternal capacitor (C
). C
is charged through an ex-
BST
BST
ternal diode to VCC or CAP when the low side MOSFET High efficiency is obtained primarily by the low side
is on. The charging level on C is internally regulated MOSFET which replaces the Schottky diode in the stan-
BST
to 11V or 7.5V minus an external diode drop by the dard buck configuration. Its low R
produces a
DS(ON)
UC3870 as long as VCC is above 11V. When the low much lower voltage drop than a low VF Schottky diode.
side MOSFET turns off, C is applied across the gate As output voltages get lower, these improvements be-
BST
to the source of the upper MOSFET allowing it to begin come more evident.
turn-on. As the upper MOSFET turns on, it lifts or boot-
Another efficiency consideration is the the possibility of
straps the low end of C , along with its source. Shortly
thereafter, the source voltage level is reduced by
BST
reverse current in the output inductor. For a non-
synchronous regulator this isn’t a problem since the di-
ode will block reverse current, allowing discontinuous in-
ductor current operation at light loads. Since the
synchronous regulator replaces the diode with a switch,
reverse current can and will flow if the low side switch is
on when the inductor is depleted. The UC3870 includes
circuitry to prevent reverse current from flowing in the in-
RDS(on) · I
below VCC. When VCC < 10V, V for
GS
LOAD
the high side MOSFET is approximately equal to VCC. If
VCC < 8V, logic level MOSFETs are recommended. In
these applications, CAP should be shorted to VCC and
an external Schottky diode is connected between
CAP/VCC and BOOT. For low battery applications, a syn-
7
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
APPLICATION INFOMATION (continued)
ductor by disabling the low side gate drive signal during reduces total standby current to less than 50mA. Short
discontinuous mode operation. This increases efficiency circuit protection is inherent to the average current mode
2
by eliminating unnecessary I R losses in the MOSFET technique with proper compensation of the current
and the inductor.
amplifier. To prevent operation of the MOSFETs with an
inadequete drive signal, an undervoltage lockout circuit
suppresses the output drivers until the input supply
voltage is sufficiently high enough for proper operation.
The UC3870-1 is intended for applications with logic level
MOSFETs and its VCC turn-on and turn-off thresholds
are 4.5V/4.4V respectively. The UC3870-2 is intended for
applications with standard MOSFETs and has UVLO
turn-on and turn-off thresholds of 10V and 9V
respectively. The precision 2.5V reference can provide
10mA to power external circuitry. The reference output is
disabled during UVLO and sleep modes.
Soft start is recommended for Buck converters to reduce
stress on the power components during startup, and to
reduce overshoot of the output voltage. This improves
reliability. The UC3870 includes a user programmable
soft start pin to implement this feature. An internal 10mA
current source charges the external soft start capacitor
which provides a clamp at the output of the voltage
amplifier. An ultra low power sleep mode is also invoked
from the SS pin. A voltage level below 0.5V on this pin
TYPICAL PERFORMANCE INFORMATION
TEMPERATURE °C
Figure 1. Supply Current
Figure 2. Volt Amp GM (IOUT = ± 10mA)
140
130
120
110
100
90
80
-25
25
75
125
-75
TEMPERATURE °C
Figure 3. Oscillator Frequency vs. Temperature
(CT = 680pF)
8
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
TYPICAL PERFORMANCE INFO (continued)
0
70
ROOM
105
100
95
0.16
0.14
0.12
0.1
90
85
80
0.08
75
1
2
3
4
5
-25
25
75
125
0
-75
VCM (V)
TEMPERATURE °C
Figure 4. Short Circuit Limit Voltage Reflected to
Input of Current Amp vs. Current Amp Common
Mode Voltage
Figure 5. High Drive Maximum Duty Cycle
(UC1870-1,-2)
Figure 6. I Limit Voltage Tolerance vs. VCM
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
9
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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