UC3886DG4 [TI]
Average Current Mode PWM Controller IC; 平均电流模式PWM控制器IC
| 型号： | UC3886DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Average Current Mode PWM Controller IC |
| 文件： | 总9页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UC2886
UC3886
available
Average Current Mode PWM Controller IC
FEATURES
DESCRIPTION
• 10.3V - 20V Operating Range
The UC3886 family of PWM controller ICs is designed for DC-to-DC con-
verters with average current mode control. It is designed for use in con-
junction with the UC3910 4-bit DAC and Voltage Monitor. The UC3886
drives an external N-channel MOSFET and can be used to power the In-
tel Pentium® Pro and other high-end microprocessors.
• Low Offset Voltage Amplifier
• High Bandwidth Current and Voltage
Amplifiers
The UC3886 in conjunction with the UC3910 converts 5VDC to an adjust-
able output ranging from 2.0V to 3.5V in 100mV steps with 35mV DC sys-
tem accuracy.
• Low Offset Current Sense Amplifier
• Undervoltage Lockout
• Trimmed 5 Volt Reference
The oscillator is programmed by the user’s selection of an external resis-
tor and capacitor, and is designed for 300kHz typical operation.
• Externally Programmable Oscillator
Charge Current
The voltage and current amplifiers have 3.5MHz gain-bandwidth product
to satisfy high performance system requirements.
• 1.5A Peak Totem Pole Output
The internal current sense amplifier permits the use of a low value current
sense resistor, minimizing power loss. It has inputs and outputs accessi-
ble to allow user-selection of gain-setting resistors, and is internally com-
pensated for a gain of 5 and above. The command voltage input is
buffered and provided for use as the reference for the current sense am-
plifier.
• Available in 16-pin DIL or SOIC
Packages
The output of the voltage amplifier (input to the current amplifier) is
clamped to 1 volt above the command voltage to serve as a current limit.
The gate output can be disabled by bringing the CAO/ENBL pin to below
0.8 volts.
BLOCK DIAGRAM
UDG-95098-2
SLUS231 - JUNE 1998
UC2886
UC3886
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Output Current
DIL-16, SOIC-16 (Top View)
N or D Packages
CAM, COMMAND, VSENSE, ISN, ISP . . . . . . . . . . . . . ± 1A
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 7V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperatue (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 12V, VCOMMAND = 3.0V, CT = 1nF, RT = 10k,
TA = TJ = 0°C < TA < 70°C for the UC3886. (Note: –25°C < TA < 85°C for the UC2886,
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
Overall
Supply Current
VCC = 11V, Gate Open
10
15
5
mA
mA
VCC = 9.3V
Undervoltage Lockout
Start Threshold
9.7
10.3
0.25
10.8
0.4
V
V
UVLO Hysteresis
Voltage Error Amplifier
Input Offset Voltage
VCM = 3.0V (UC3886)
VCM = 3.0V (UC2886)
VCM = 3.0V
4
15
mV
mV
µA
µA
µA
dB
dB
dB
V
Input Bias Current
Input Offset Current
−2
VCM = 3.0V (UC3886)
VCM = 3.0V (UC2886)
2.5V < VCOMP < 3.5V
2V < VCOMP < 4V
11V < VCC < 15V
ICOMP = –100µA (UC3886)
ICOMP = –100µA (UC2886)
ICOMP = 100µA
0.01
0.1
Open Loop Gain
60
60
85
85
85
4
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output High Voltage (Clamp)
60
3.95
3.9
1.9
0.9
4.05
4.1
V
Output Low Voltage (Clamp)
Output Sink Current
Output Source Current
Gain-Bandwidth Product
5.0V Reference
2.7
V
VCOMP = 3.7V
mA
mA
MHz
VCOMP = 2.8V
–0.15 −0.25
F = 100kHz
2
3.5
Output Voltage
IVREF = 1.0mA
4.9
5
5.1
5.175
10
V
Total Variation
Line, Load, Temperature
11V < VCC < 15V
0 < IVREF < 2mA
4.825
V
Line Regulation
mV
mV
mA
Load Regulation
15
Short Circuit Current
–10
−40
2
UC2886
UC3886
ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 12V, VCOMMAND = 3.0V, CT = 1nF, RT = 10k,
TA = TJ = 0°C < TA < 70°C for the UC3886. (Note: –25°C < TA < 85°C for the UC2886,
PARAMETER TEST CONDITIONS
MIN
TYP MAX UNITS
Input Buffer
Gain
IBUF = ± 500µA (UC3886)
0.98
0.95
1
1.02
1.05
V/V
V/V
IBUF = ± 500µA (UC2886)
Current-Sense Amplifier
Input Offset Voltage
VCM = 3.0V (UC3886)
VCM = 3.0V (UC2886)
VCM = 3.0V
2
6
mV
mV
µA
µA
dB
dB
dB
V
Input Bias Current
Input Offset Current
Open Loop Gain
CMRR
-1
0.2
VCM = 3.0V
2V < VISO < 6V
0V < VCM < 4.5V
11V < VCC < 15V
IISO = –100µA
IISO = 1mA
60
60
60
5
85
85
85
PSRR
Output High Voltage
Output Low Voltage
Output Source Current
Gain-Bandwidth Product
Current Amplifier
Input Offset Voltage
1
V
VISO = 2V
−0.2
mA
MHz
F = 100kHz
2
3.5
VCM = 3.0V (UC3886)
VCM = 3.0V (UC2886)
VCM = 3.0V
13
18
1
mV
mV
µA
dB
dB
dB
V
Input Bias Current
Open Loop Gain
CMRR
1V < VCAO < 3V
1.5V < VCM < 4.5V
11V < VCC < 15V
ICAO = –100µA
ICAO = 100µA
60
60
60
3
85
85
85
PSRR
Output High Voltage
Output Low Voltage
Output Source Current
Gain-Bandwidth Product
Oscillator
3.3
1
V
VCAO =1V
−0.1 –0.25
mA
MHz
F = 100kHz
2
3.5
Frequency
RT = 10k, CT = 1nF (UC3886)
RT = 10k, CT = 1nF (UC2886)
11V > VCC > 15V
90
85
100
110
115
1
kHz
kHz
%
Frequency Change With Voltage
CT Peak Voltage
2.6
1.6
2.8
1
V
CT Valley Voltage
1.2
2.0
V
CT Peak-to-Peak Voltage
Output Section
1.8
V
Output Low Voltage
Output High Voltage
Output Low Voltage
IGATE = 200mA
1.6
2.2
V
V
IGATE = –200mA
5V < VCC < 9V, IGATE = 10mA
VCAO < 0.8V, IGATE = 10mA
CL = 1nF
9
10.3
0.5
0.5
V
V
Rise/Fall Time
150
ns
%
%
Maximum Duty Cycle
(UC3886)
90
85
(UC2886)
3
UC2886
UC3886
PIN DESCRIPTIONS
BUF: (Buffer Output) The voltage on COMMAND pin is
buffered and presented to the user here. This voltage is
used to provide the operating bias point for the current
sense amplifier by connecting a resistor between BUF
and ISP. Decouple BUF with 0.01µF or greater to SGND.
GATE: (PWM Output) The output is a 1A totem pole
driver. Use a series resistor of at least 5 to prevent in-
teraction between the gate impedance and the output
driver that might cause excessive overshoot.
ISN: (Current Sense Amplifier Inverting Input) A resistor
to the low side of the average current sense resistor and
a resistor to ISO are applied to this pin to make a differ-
ential sensing amplifier.
CAM: (Current Amplifier Minus Input) The average load
current feedback from ISO is typically applied through a
resistor here.
ISO: (Current Sense Amplifier Output) A feedback resis-
tor to ISN is connected here to make a differential
sensing amplifier. The voltage at this pin is equal to
(VBUF + A • IAVG • RSENSE) where A is the user deter-
mined gain of the differential amplifier, IAVG is the
average load current of the system, and RSENSE is the
average current sensing resistor. For stability, A must be
greater than 5. Set A such that A • ISC • RSENSE = 1.0V
where ISC is the user-determined short circuit current
limit.
CAO/ENBL: (Current Amplifier Output/Chip Enable) The
current loop compensation network is connected be-
tween CAO/ENBL and CAM, the inverting input of the
current amplifier. The voltage at CAO/ENBL is the input
to the PWM comparator and regulates the output voltage
of the system. The GATE output is disabled (held low)
unless the voltage at this pin exceeds 1.0 volts, allowing
the PWM to force zero duty cycle when necessary. The
user can force this pin below 0.8 volts externally with an
open collector, disabling the GATE drive.
ISP: (Current Sense Amplifier Non-Inverting Input) A re-
sistor to the high side of the average current sense
resistor and a resistor to BUF are connected to this pin
to make a differential sensing amplifier.
COMMAND: (Voltage Amplifier Non-Inverting Input) This
input to the voltage amplifier is connected to a command
voltage, such as the output of a DAC. This voltage sets
the switching regulator output voltage.
PGND: (Power Ground) The PWM output current returns
to ground through this pin. This is separated from SGND
to avoid on-chip ground noise generated by the output
current.
COMP: (Compensation, Voltage Amplifier Output) The
system voltage compensation network is applied be-
tween COMP and VSENSE. The voltage at COMP is
clamped to prevent it from going more than 1V above the
COMMAND voltage. This is used to provide an accurate
average current limit. The voltage on COMP is also
clamped to 0.7V below the voltage on COMMAND. This
is done to avoid applying a full charge to capacitors in
the compensation network during transients, allowing
quick recovery time and little overshoot.
RT: (Oscillator Charging Current) This pin is held at 2V.
Resistor RT from this pin to SGND sets the oscillator
charging current. Use 5k < RT < 100k.
SGND: (Signal Ground) For better noise immunity, sig-
nal ground is provided at this pin.
VCC: (Positive Supply Voltage) This pin supplies power
to the chip and to the gate drive output. Decouple to
PGND and separately to SGND for best noise immunity.
The reference (VREF), GATE output, oscillator, and am-
plifiers are disabled until VCC exceeds 10.3V.
CT: (Oscillator Timing Capacitor) A capacitor from CT to
SGND along with the resistor on RT, sets the PWM fre-
quency and maximum duty cycle according to these
formulas:
2.0V
DMAX =1–
VREF: (Voltage Reference Output) An accurate 5V refer-
ence as provided at this pin. The output can deliver 2mA
to external circuitry, and is internally short circuit current
limited. VREF is disabled if VCC is below UVLO. Bypass
5V REF to SGND with an 0.01µF or larger capacitor for
best stability.
RT • 4.0mA
where DMAX is the maximum operating duty cycle, and
RT is in ohms.
(
)
2.0V • ( 4.0mA• RT – 2.0V)
FOSC
=
CT • 1.8V • RT 2 • 4.0mA
VSENSE: (Voltage Sense Input) This input is connected
to COMP through a feedback network and to the power
supply output through a resistor or a divider network.
where FOSC is the UC3886 oscillator switching fre-
quency in Hz, RT is in ohms, and CT is in farads.
4
UC2886
UC3886
APPLICATION INFORMATION
OSCILLATOR
1.00
0.98
0.96
0.94
0.92
0.90
0.88
The UC3886 oscillator is a saw tooth. The rising edge
is governed by a current controlled by RT flowing into
the capacitor CT. The falling edge of the sawtooth sets
the dead time for the output. Selection of RT should be
done first, based on desired maximum duty cycle. CT
can then be chosen based on the desired frequency,
FS, and the value of RT. The design equations are:
2.0V
DMAX =1–
RT • 4.0mA
0
20
40
60
80
100
120
(
)
2.0V • ( 4.0mA• RT – 2.0V)
RT (kΩ)
FOSC
=
CT • 1.8V • RT 2 • 4.0mA
Figure 2. Programming Maximum Duty Cycle with RT
1000
100pF
220pF
470pF
1nF
100
10
UDG-96022
0
20
40
60
80
100
Figure 1. Oscillator
RT (kΩ)
Configuring the Current Sense Amplifier
Figure 3. Programming Switching Frequency with CT
The UC3886 Current Sense Amplifier is used to amplify
a differential current sense signal across a low value
current sense resistor, RSENSE. This amplifier must be
set up as a differential amplifier as shown.
0.600
The Current Sense Amplifier gain, GCSA, is given by the
ratio of R2/R1. The output of the Current Sense Ampli-
fier at the ISO pin is given by
RT = 5k
RT = 100k
0.500
0.400
R2
VISO =VBUF +VSENSE
•
R1
0.300
0.200
0.100
0.000
The Current Sense Amplifier gain, GCSA, must be pro-
grammed to be greater than or equal to 5.0 (14dB), as
this amplifier is not stable with gain below 5.0. The Cur-
rent Sense Amplifier gain is limited on the high side by
its Gain-Bandwidth product of 2.5MHz. Therefore GCSA
must be programmed between
100
300
500
700
900
1100
CT (pF)
G
CSA_MIN = 5.0 and GCSA_MAX = 2.5MHz/FSWITCH
Figure 4. Deadtime vs. CT and RT
5
UC2886
UC3886
APPLICATION INFORMATION (cont.)
Enabling/Disabling the UC3886 Gate Drive
The CAO/ENBL pin can be used to Disable the UC3886
gate drive by forcing this pin below 0.8V, as shown.
Bringing the voltage below the valley of the PWM oscil-
lator ramp will insure a 0% duty cycle, effectively dis-
abling the gate drive. A low noise open collector signal
should be used as an Enable/Disable command.
UDG-96024
UDG-96023
Figure 6. Enabling/Disabling the UC3886
Figure 5. Configuring the Current Sense Amplifier
TYPICAL APPLICATIONS
UDG-96025
Figure 7. The UC3886 Configured in a Buck Regulator
6
UC2886
UC3886
TYPICAL APPLICATIONS (cont.)
UDG-96021
Figure 8. UC3886 Configured with the UC3910 for a Pentium® Pro DC/DC Converter
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
UC2886D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC2886DG4
UC3886D
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
N
N
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UC3886DG4
UC3886N
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UC3886NG4
25 Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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