UC3902DG4 [TI]

具有 0°C 至 70°C 工作温度范围的 20V 负载共享控制器 | D | 8 | 0 to 70;
UC3902DG4
型号: UC3902DG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

具有 0°C 至 70°C 工作温度范围的 20V 负载共享控制器 | D | 8 | 0 to 70

控制器 光电二极管 电源管理电路 电源电路
文件: 总6页 (文件大小:149K)
中文:  中文翻译
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UC1902  
UC2902  
UC3902  
PRELIMINARY  
Load Share Controller  
FEATURES  
DESCRIPTION  
2.7V to 20V Operation  
The UC3902 load share controller is an 8-pin device that balances the cur-  
rent drawn from independent, paralleled power supplies. Load sharing is  
accomplished by adjusting each supply’s output current to a level propor-  
tional to the voltage on a share bus.  
8-Pin Package  
Requires Minimum Number of  
External Components  
The master power supply, which is automatically designated as the supply  
that regulates to the highest voltage, drives the share bus with a voltage  
Compatible with Existing Power  
Supply Designs Incorporating Remote proportional to its output current. The UC3902 trims the output voltage of  
Output Voltage Sensing  
the other paralleled supplies so that they each support their share of the  
load current. Typically, each supply is designed for the same current level  
although that is not necessary for use with the UC3902. By appropriately  
scaling the current sense resistor, supplies with different output current ca-  
pability can be paralleled with each supply providing the same percentage  
of their output current capability for a particular load.  
Differential Share Bus  
Precision Current Sense Amplifier with  
Gain of 40  
UVLO (Undervoltage Lockout)  
Circuitry  
A differential line is used for the share bus to maximize noise immunity and  
accommodate different voltage drops in each power converter’s ground re-  
turn line. Trimming of each converter’s output voltage is accomplished by  
injecting a small current into the output voltage sense line, which requires a  
small resistance (typically 20– 100) to be inserted.  
User Programmable Share Loop  
Compensation  
BLOCK DIAGRAM  
LOAD SHARE CONTROLLER  
GND  
1
8
VCC  
BIAS  
UVLO  
SHARE DRIVE AMPLIFIER  
+
40R  
R
SENSE  
2
+
7
6
SHARE+  
SHARE–  
+
CURRENT SENSE  
AMPLIFIER  
SHARE SENSE AMPLIFIER  
ERROR AMPLIFIER  
+
ADJ  
3
4
+
35mV  
0.6V  
ADJ AMPLIFIER  
+
+
5
COMP  
2.3V  
ADJR  
UDG-99042  
SLUS232 - FEBRUARY 1999  
UC1902  
UC2902  
UC3902  
ABSOLUTE MAXIMUM RATINGS  
CONNECTION DIAGRAM  
Supply Voltage (ADJ and VCC) . . . . . . . . . . . . . . –0.3V to 20V  
SENSE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5V to +5V  
ADJR, COMP Voltage. . . . . . . . . . . . . . . . . . . . . . –0.3V to +4V  
SHARE–, SHARE+ Voltages . . . . . . . . . . . . . . . . –0.3V to 10V  
SHARE+ Current . . . . . . . . . . . . . . . . . . . . . –100mA to +10mA  
ADJ Current . . . . . . . . . . . . . . . . . . . . . . . . . . . –1mA to +30mA  
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature. . . . . . . . . . . . . . . . . . . 55°C to +150°C  
Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C  
DIL-8, SOIC-8 (Top View)  
N, J and D Package  
All voltages are with respect to pin 1. Currents are positive into,  
negative out of the specified terminal. Consult Packaging Sec-  
tion of the Databook for thermal limitations and considerations  
of packages.  
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = –55°C to +125°C for UC1902, –40°C to+85°C for  
UC2902, 0°C to 70°C for UC3902, VCC = 5V, RADJR = 1k, VADJ = 5V, COMP = 5nF capacitor to GND, VSHARE= 0V, TA = TJ.  
PARAMETERS  
Power Supply  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
Supply Current  
SHARE+ = 1V, SENSE = 0V  
4
6
6
mA  
mA  
VCC = 20V  
10  
Undervoltage Lockout  
Startup Voltage  
SHARE+ = 0.2V, SENSE = 0V, COMP = 1V  
SHARE+ = 0.2V, SENSE = 0V, COMP = 1V  
2.3  
60  
2.5  
2.7  
V
Hysteresis  
100  
140  
mV  
Current Sense Amplifier  
Input Offset Voltage  
Gain SENSE to SHARE  
Input Resistance  
0.1V SHARE+ 1.1V  
0.1V SHARE+ 1.1V  
–2.5  
–41  
0.6  
–0.5  
–40  
1
1.5  
-39  
1.5  
mV  
V/V  
kΩ  
Share Drive Amplifier  
SHARE+ High  
VCC = 2.5V, SENSE = –50mV, ISHARE+ = –1mA  
VCC = 12V, SENSE = –250mV, ISHARE+ = –1mA  
VCC = 20V, SENSE = –250mV, ISHARE+ = –1mA  
VCC = 2.5V, SENSE = +10mV, ISHARE+ = –1mA  
VCC = 12V, SENSE = +10mV, ISHARE+ = –1mA  
VCC = 20V, SENSE = +10mV, ISHARE+ = –1mA  
1.2  
9.6  
9.6  
1.4  
10  
10  
20  
20  
20  
20  
V
10.4  
10.4  
50  
V
V
SHARE+ Low  
mV  
mV  
mV  
mV  
50  
50  
SHARE+ Output Voltage  
Measures SHARE+, SENSE = 0mV, RSHARE+ = 200resistor  
40  
SHARE+ to GND  
CMRR  
0 SHARE– 1V , SENSE used as input to amplifier  
50  
90  
0
dB  
Load Regulation  
Load on SHARE+, –1mA ILOAD –20mA, SENSE =  
20  
mV  
–25mV  
Short Circuit Current  
Slew Rate  
SHARE+ = 0V, SENSE = –25mV  
–85  
–50  
–20  
mA  
SENSE = +10mV to –90mV Step, 200resistor SHARE+ to  
0.16  
0.27  
0.37  
V/µs  
GND  
SENSE = –90mV to +10mV Step, 200resistor SHARE+ to  
0.12  
0.24  
0.34  
V/µs  
GND  
2
UC1902  
UC2902  
UC3902  
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = –55°C to +125°C for UC1902, –40°C to+85°C for  
UC2902, 0°C to 70°C for UC3902, VCC = 5V, RADJR = 1k, VADJ = 5V, COMP = 5nF capacitor to GND, VSHARE= 0V, TA = TJ.  
PARAMETERS  
Share Sense Amplifier  
Input Impedance  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
SHARE+ = 1V, SHARE– = 1V, SENSE = +10mV  
10  
15  
15  
17  
kΩ  
kΩ  
200resistor SHARE+ to GND, SHARE– = 1V, SENSE =  
+10mV  
Threshold  
SENSE = 0V  
41  
50  
50  
70  
60  
68  
100  
mV  
dB  
dB  
CMRR SHARE  
0 SHARE– 1V, SENSE = –2.5mV  
AVOL from SHARE+ to ADJR SENSE = –2.5mV, 5nF capacitor COMP to GND, 1k resistor  
ADJR to GND  
SENSE = –2.5mV, 5nF capacitor COMP to GND, 150Ω  
50  
66  
dB  
resistor ADJR to GND  
Slew Rate  
SHARE+ = Step of 0mV to 300mV through a 200resistor,  
RCOMP = 500resistor to 1.5V, SENSE = 10mV  
0.4  
0.7  
1
V/µs  
Error Amplifier Section  
Transconductance, SHARE+  
to COMP  
200resistor SHARE+ to GND  
3.2  
4.5  
5.5  
mS  
IOH  
IOL  
COMP = 1.5V, SHARE+ +300mV, SENSE = +10mV  
–400 –325 –230  
µA  
µA  
200resistor SHARE+ to GND, COMP = 1.5V, SENSE =  
100  
150  
200  
+10mV  
Input Offset Voltage  
VIO/VSENSE  
15  
–6  
35  
0
65  
6
mV  
1k Resistor, ADJR to GND, –2.5mV < SENSE < –25mV  
mV/V  
ADJ Amplifier  
ADJR Low Voltage  
ADJR High Voltage  
Current Gain ADJR to ADJ  
SENSE = +10mV, 200resistor SHARE+ to GND  
–1  
1.4  
0
1
2.1  
1
mV  
V
SENSE = +10mV, SHARE+ = 1V  
1.8  
ADJR Current = –0.5mA, ADJ = 2.5V, SENSE = +10mV,  
SHARE+ = 1V  
0.96  
0.99  
A/A  
ADJR Current = –0.5mA, ADJ = 20V, SENSE = +10mV,  
SHARE+ = 1V  
0.96  
0.96  
0.96  
0.99  
0.99  
0.99  
1
1
1
A/A  
A/A  
A/A  
ADJR Current = –10mA, ADJ = 2.5V, SENSE = +10mV,  
SHARE+ = 1V  
ADJR Current = –10mA, ADJ = 20V, SENSE = +10mV,  
SHARE+ = 1V  
PIN DESCRIPTIONS  
ADJ: Current output of adjust amplifier circuit (NPN GND: Local power supply return and signal ground.  
collector).  
SENSE: Inverting input of current sense amplifier.  
ADJR: Current adjust amplifier range set (NPN emitter).  
SHARE+: Positive input from share bus or drive to share  
COMP: Output of error amplifier, input of adjust amplifier. bus.  
This is where the compensation capacitor is connected.  
SHARE-: Reference for SHARE+.  
VCC: Local power supply (positive).  
3
UC1902  
UC2902  
UC3902  
APPLICATION INFORMATION  
UDG-96200  
Figure 1. Typical application.  
4
UC1902  
UC2902  
UC3902  
APPLICATION INFORMATION (cont.)  
The values of five passive components must be deter-  
R
ADJ  
must be low enough to not affect the normal opera-  
mined to configure the UC3902 load share controller. tion of the converter’s voltage feedback loop. Typical  
The output and return lines of each converter are con-  
nected together at the load, with current sense resistor  
R
values are in the 20to100range depending on  
ADJ  
V , V (max) and the selected I  
O
(max) value.  
O
ADJ  
R
inserted in each negative return line. Another re-  
SENSE  
Step 4.  
sistor, R  
is also inserted in each positive remote  
ADJ,  
GM  
RADJ RSENSE  
sense line. The differential share bus terminals (SHARE+  
and SHARE–) of each UC3902 are connected together  
respectively, and the SHARE– node is also connected to  
the system ground. A typical application is illustrated in  
Figure 1.  
CC  
=
ACSA APWR fC  
( )  
2π fC RG  
RLOAD  
The share loop compensation capacitor, C is calculated  
to produce the desired share loop unity gain crossover  
frequency, fC. The share loop error amplifier’s  
C
The load share controller design can be executed by fol-  
lowing the next few steps:  
transconductance, G is nominally 4.5ms. The values of  
M
the resistors are already known. Typically, fC will be set  
at least an order of magnitude below the converter’s  
closed loop bandwidth. The load share circuit is primarily  
intended to compensate for each converter’s initial output  
voltage tolerance and temperature drift, not differences in  
Step 1.  
VSHARE max  
(
)
RSENSE  
=
ACSA IO max  
(
)
their transient response. The term A (fC) is the gain  
PWR  
where A  
is 40, the gain of the current sense amplifier.  
CSA  
of the power supply measured at the desired share loop  
crossover frequency, fC. This gain can be measured by  
injecting the measurement signal between the positive  
output and the positive sense terminal of the power sup-  
ply.  
At full load, the voltage drop across the R  
resistor  
SENSE  
is I (max) • R  
. Taking into account the gain of the  
O
SENSE  
current sense amplifier, the voltage at full load on the  
current share bus,  
VSHARE max = A  
IO max R  
.
SENSE  
(
)
(
)
CSA  
Step 5.  
This voltage must stay 1.5V below V  
or below 10V  
CC  
1
RC  
=
whichever is smaller. V  
represents an upper limit  
SHARE  
2π fC CC  
but the designer should select the full scale share bus  
voltage keeping in mind that every volt on the load share  
bus will increase the master controller’s supply current by  
approximately 100mA times the number of slave units  
connected parallel.  
A resistor in series with CC is required to boost the phase  
margin of the load share loop. The zero is placed at the  
load share loop crossover frequency, fC.  
When the system is powered up, the converter with the  
highest output voltage will tend to source the most cur-  
rent and take control of the share bus. The other convert-  
ers will increase their output voltages until their output  
currents are proportional to the share bus voltage minus  
50mV. The converter which in functioning as the master  
may change due to warmup drift and differences in load  
and line transient response of each converter.  
Step 2.  
VADJ max  
(
)
RG  
=
IADJ max  
(
)
Care must be taken to ensure that I  
enough to ensure that both the drive current and power  
dissipation are within the UC3902’s capability. For most  
(max) is low  
ADJ  
applications, an I  
(max) current between 5mA and  
ADJ  
ADDITIONAL INFORMATION  
10mA is acceptable. In a typical application, a 360R  
G
Please refer to the following Unitrode topic for additional  
application information.  
resistor from the ADJR pin to ground sets I  
approximately 5mA.  
(max) to  
ADJ  
[1] Application Note U-163, The UC3902 Load Share  
Controller and Its Performance in Distributed Power Sys-  
tems by Laszlo Balogh.  
Step 3.  
VO max – I max R  
(
)
(
)
O
SENSE  
RADJ =  
IADJ max  
(
)
UNITRODE CORPORATION  
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054  
TEL. (603) 424-2410 FAX (603) 424-3460  
5
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pertaining to warranty, patent infringement, and limitation of liability.  
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
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APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
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BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
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Copyright 1999, Texas Instruments Incorporated  

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