UC3965DTR [TI]
Precision Reference with Low Offset Error Amplifier 8-SOIC 0 to 70;![UC3965DTR](http://pdffile.icpdf.com/pdf2/p00296/img/icpdf/UC3965DTR_1791791_icpdf.jpg)
型号: | UC3965DTR |
厂家: | ![]() |
描述: | Precision Reference with Low Offset Error Amplifier 8-SOIC 0 to 70 光电二极管 |
文件: | 总6页 (文件大小:76K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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application
INFO
UC1965
UC2965
UC3965
available
Precision Reference with Low Offset Error Amplifier
FEATURES
DESCRIPTION
• Accessible 2.5V Precision Reference
The UC3965 is suitable for applications needing greater precision and
more functionality than the TL431 type shunt regulators. The wide range
VCC input capability enables the device to be biased from the secondary
side output voltage rail, resulting in closed loop soft start.
• 0.4% Initial Reference Accuracy
• 1% Reference Accuracy over Line,
Load, and Full Temperature Range
The UC3965 includes an accessible 2.5V precision reference which offers
0.4% initial and 1% reference accuracy over line, load, and full tempera-
ture range with a low offset error amplifier, a 2X inverting amplifier/buffer,
and an undervoltage lockout circuit. The IC is ideally suited for applica-
tions where high precision PWM power supply regulation is required.
Typically, the error amplifier is configured to compare a fraction of the to
be regulated power supply voltage to the on-chip 2.5V reference. The 2X
amplifier/buffer output is then used to drive a PWM controller or regulator.
The UC3965 is also capable of driving an optocoupler diode for isolated
applications.
• Low 1mV Offset Error Amplifier
• Supports Closed Loop Soft Start
• 2X Inverting Amplifier / Buffer Output
• 4.1V Undervoltage Lockout
• ICC 2mA at 5V
• 8-Pin SOIC or DIL Package
BLOCK DIAGRAM
OFFSET
VCC
1
2
8
7
6
5
COMP
VFB
VREF
2.5V
UVLO
5k
+
OB
–
VCC
5k
VOUT
GND
3
4
VREF
NI
–
EA
+
15k
7.5k
2k
UDG-98055
SLUS300A - APRIL 1999
UC1965
UC2965
UC3965
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 20V
VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6V
VFB, COMP, NI, VOUT. . . . . . . . . . . . . . . . . . . . . –0.3V TO 6V
Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
DIL-8, SOIC-8 (Top View)
J or N Package, D Package
OFFSET
VCC
8
7
6
5
COMP
VFB
1
2
3
4
Currents are positive into, negative out of the specified terminal.
All voltages are with respect to ground. Consult Packaging Sec-
tion of Databook for thermal limitations and considerations of
packages.
VOUT
GND
VREF
NI
ORDERING INFORMATION
TEMPERATURE RANGE
–55°C to +125°C
PACKAGE
CDIP
UC1965J
UC2965D
UC2965N
UC3965D
UC3965N
–40°C to +85°C
SOIC
PDIP
SOIC
PDIP
0°C to +70°C
ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 5V, TA = TJ.
PARAMETER TEST CONDITIONS
MIN
TYP
MAX UNITS
General
VCC
4.3
1.5
20
4
V
Operating Current
VCC = 5V
2
mA
µA
V
Undervoltage Current
Minimum Voltage to Start
Hysteresis
200
4.3
400
3.9
4.1
200
300
mV
VREF
VREF Initial Accuracy
VREF Over Temperature
Total Output Variation
Line Regulation
+25°C
2.49
2.48
2.5
2.5
2.5
2
2.51
2.52
2.525
10
V
V
–55°C to +125°C
Line, Load, Temperature
VCC = 4.3V to 20V
0µA to 500µA
2.475
V
mV
mV
mA
Load Regulation
2
10
Short Circuit Current
Error Amplifier
VREF = 0V
2
Input Bias
VCM = 2.5V
200
1
400
2
nA
mV
nA
Input Offset Voltage
Input Offset Current
Gain Bandwidth Product
Open Loop Gain
VCM = 2.5V
VCM = 2.5V
–100
80
0
100
VIN = 50mV P-P (Note 1)
VOUT = 1V to 3.75V
6
MHz
dB
100
2
UC1965
UC2965
UC3965
ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 5V, TA = TJ.
PARAMETER
Error Amplifier Section (cont.)
Output Low Level
TEST CONDITIONS
MIN
TYP
MAX UNITS
IOUT = 0µA
IOUT = 100µA
IOUT = 0µA
0.8
1.2
4
V
V
Output High Level
V
IOUT = –500µA
4
V
Short Circuit Circuit
CMRR
VCOMP = 0V
8
mA
dB
dB
V/µs
V/µs
VCM = 1.25V to 3.75V
VCC = 4.3V to 20V
70
70
100
100
2
PSRR
Rising Slew Rate
Falling Slew Rate
Inverting Buffer Amplifier
Input Bias
0.4
VCM = 2.5V
1
0
2
µA
mV
MHz
V/V
V
Output Offset Voltage
Gain Bandwidth Product
Closed Loop Gain
Output Low Level
VCM = 2.5V
–20
20
VIN = 50mV P-P (Note 1)
Inverting Gain
IOUT = 0µA
IOUT = 100µA
IOUT = 0mA
1.5
–2
0.3
0.5
4
–2.04
–1.96
V
Output High Level
V
IOUT = –4mA
4
V
Short Circuit Circuit
CMRR
VOUT = 0V
18
100
100
0.9
0.9
mA
dB
dB
V/µs
V/µs
VCM = 1.25V to 3.75V
VCC = 4.3V to 20V
70
70
PSRR
Rising Slew Rate
Falling Slew Rate
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
COMP: The output of the error amplifier and the input to VFB: The inverting terminal of the error amplifier used as
the inverting terminal of the internal output buffer. This both the voltage sense input to the error amplifier and its
pin is available to compensate the high frequency gain of other compensation point.
the error amplifier.
VOUT: The emitter of the output transistor. This pin is
the output of the inverting buffer. This pin has the capa-
bility to drive an optocoupler or a PWM controller directly.
GND: The reference and power ground for the device.
NI: The non-inverting input to the error amplifier.
VREF: The output of the trimmed precision reference.
This reference maintains within 1% of its initial value over
its entire line, load, and temperature range.
OFFSET: The non-inverting input to the internal output
buffer.
VCC: The power input to the device. The minimum to
maximum operating voltage is 4.3V to 20V.
3
UC1965
UC2965
UC3965
APPLICATION INFORMATION
For designs requiring input-output isolation, the UC3965 that insures accurate regulation of the output. The inter-
is used in secondary side output voltage sensing. As nal error amplifier drives the inverting input of the output
shown in Fig. 1, the precision reference and low offset buffer (OB) which drives an optocoupler diode. The wide
error amplifier can be used in converters, such as the range VCC voltage enables the device to be biased from
isolated flyback, where the primary side error amplifier is the secondary side output voltage rail, resulting in closed
not used or simply not present. In this case, the loop soft start.
UCC3809 is used as the primary side controller.
As the output voltage increases beyond its desired value,
The precision reference of the UC3965 is tied to the the voltage difference at the error amplifier increases.
non-inverting input of the device’s internal error amplifier. This results in less drive at the inverting input of the inter-
The output voltage of the converter is resistively divided nal buffer, increasing its output drive to the optocoupler.
and compared to this reference at the inverting input. If the application does not require input-output isolation,
This error amplifier has a low 1mV input offset voltage this buffer could be used to drive the PWM directly.
+V
OUT
OFFSET
VCC
COMP
1
2
3
8
VREF
2.5V
UVLO
5k
VOUT
+
OB
VFB
VREF
NI
–
VCC
5k
7
6
5
–
EA
+
15k
7.5k
GND
4
+V
IN
2k
UCC3809
1
FB
REF
8
7
–V
OUT
VDD
2
3
4
SS
RT1 OUT
RT2 GND
6
5
–V
IN
UDG-99080
Figure 1. Typical application diagram.
ADDITIONAL INFORMATION
For additional application information biasing the
UC3965, please refer to the following publication:
[1] Application Note U-165, Design Review: Isolated 50W
Flyback with the UCC3809 Primary Side Controller and
the UC3965 Precision Reference and Error Amplifier, by
Lisa Dinwoodie.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
4
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
SOIC
Drawing
UC2965D
UC2965DTR
UC3965D
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
D
D
D
D
8
8
8
8
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
UC3965DTR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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