UCC1807-1J [TI]
1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, CDIP8, DIP-8;
| 型号： | UCC1807-1J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, CDIP8, DIP-8 CD 信息通信管理 开关 |
| 文件： | 总5页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3
Programmable Maximum Duty Cycle PWM Controller
FEATURES
DESCRIPTION
The UCC3807 family of high speed, low power integrated circuits contains all of the
control and drive circuitry required for off-line and DC-to-DC fixed frequency current
mode switching power supplies with minimal external parts count.
•
User Programmable
Maximum PWM
Duty Cycle
•
•
•
100µA Startup Current
These devices are similar to the UCC3800 family, but with the added feature of a
user programmable maximum duty cycle. Oscillator frequency and maximum duty
cycle are programmed with two resistors and a capacitor.The UCC3807 family also
features internal full cycle soft start and internal leading edge blanking of the cur-
rent sense input.
Operation to 1MHz
Internal Full Cycle
Soft Start
The UCC3807 family offers a variety of package options, temperature range
options, and choice of critical voltage levels. The family has UVLO thresholds and
hysteresis levels for off-line and battery powered systems.Thresholds are shown in
the table below.
•
•
Internal Leading Edge
Blanking of Current
Sense Signal
1 Amp Totem Pole
Output
Part Number
UCCx807-1
UCCx807-2
UCCx807-3
Turn-on Threshold
Turn-off Threshold
7.2V
12.5V
4.3V
6.9V
8.3V
4.1V
BLOCK DIAGRAM
UDG-95001-1
6/97
UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
Supply Voltage (IDD ≤ 10mA) . . . . . . . . . . . . . . . . . . . . . . .13.5V
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30mA
OUT Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±1A
Analog Inputs (FB, CS) . . . . . . . . . . . . .−0.3V to (VDD + 0.3V)
Power Dissipation at TA +25°C (N or J packages) . . . . . . . .1W
Power Dissipation at TA +25°C (D package) . . . . . . . . . .0.65W
Storage Temperature . . . . . . . . . . . . . . . . . . . .−65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . .−65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . .+300°C
All currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
DIL-8, SOIC-8 (Top View)
J or N, D Packages
ORDERING INFORMATION
UCC
807
—
UVLO Threshold
Package
Temperature Range
ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for TA = −55°C to +125°C for
UCC1807-1/-2/-3; −40°C to +85°C for UCC2807-1/-2/-3; and 0°C to +70°C for UCC3807-1/-2/-3;VDD = 10V (Note 6), RA = 12kΩ,
RB = 4.7kΩ, CT = 330pF, 1.0µF capacitor from VDD to GND, TA = TJ.
PARAMETER
Oscillator Section
TEST CONDITION
MIN
TYP
MAX UNITS
Frequency
175
202
2.5
228
kHz
%
Temperature Stability
Amplitude
(Note 5)
(Note 1)
1/3VDD
V
Error Amplifier Section
Input Voltage
COMP = 2.0V
1.95
−1
2.00
2.05
1
V
Input Bias Current
Open Loop Voltage Gain
COMP Sink Current
COMP Source Current
PWM Section
µA
dB
mA
mA
60
80
2.5
FB = 2.2V, COMP = 1.0V
FB = 1.3V, COMP = 4.0V
0.3
−0.2
−0.5
Maximum Duty Cycle
Minimum Duty Cycle
Current Sense Section
Gain
75
78
81
0
%
%
COMP = 0V
(Note 2)
1.1
0.9
1.65
1.0
1.8
1.1
V/V
V
Maximum Input Signal
Input Bias Current
CS Blank Time
COMP = 5.0V (Note 3)
−200
50
200
150
1.6
nA
ns
V
100
1.5
1.1
Overcurrent Threshold
COMP to CS Offset
Output Section
1.4
CS = 0V
0.55
1.65
V
OUT Low Level
I = 100mA
0.4
0.4
20
1
1
V
V
OUT High Level
I = –100mA, VDD − OUT
CL = 1nF (Note 5)
Rise/Fall Time
100
ns
2
UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated these specifications apply for TA = −55°C to
+125°C for UCC1807-1/-2/-3; −40°C to +85°C for UCC2807-1/-2/-3; and 0°C to +70°C for UCC3807-1/-2/-3;VDD = 10V (Note 6),
RA = 12kΩ, RB = 4.7kΩ, CT = 330pF, 1.0µF capacitor from VDD to GND, TA = TJ.
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNITS
Undervoltage Lockout Section
Start Threshold
UCCx807-1 (Note 4)
6.6
11.5
4.1
6.3
7.6
3.9
0.1
3.5
0.1
7.2
12.5
4.3
6.9
8.3
4.1
0.3
4.2
0.2
7.8
13.5
4.5
7.5
9.0
4.3
0.5
5.1
0.3
V
V
V
V
V
V
V
V
V
UCCx807-2
UCCx807-3
UCCx807-1 (Note 4)
UCCx807-2
UCCx807-3
UCCx807-1
UCCx807-2
UCCx807-3
Minimum Operating Voltage After Start
Hysteresis
Soft Start Section
COMP Rise Time
Overall Section
Startup Current
FB = 1.8V, From 0.5V to 4.0V
4
ms
VDD < Start Threshold (UCCx807-1,-3)
VDD < Start Threshold (UCCx807-2)
FB = 0V, CS = 0V, No Load (Note 7)
IDD = 10mA
0.1
0.15
1.3
0.2
0.25
2.1
mA
mA
mA
V
Operating Supply Current
VDD Zener Shunt Voltage
Shunt to Start Difference
12.0
0.5
13.5
1.0
15.0
V
Note 1: Measured at TRIG; signal minimum = 1/3 VDD, maximum = 2/3 VDD.
Note 2: Gain is defined by: A = ∆ VCOMP , 0 ≤ VCS ≤ 0.8V
∆ VCS
Note 3: Parameter measured at trip point of latch with FB at 0V.
Note 4: Start Threshold and Zener Shunt thresholds track one another.
Note 5: Guaranteed by design. Not 100% tested in production.
Note 6: Adjust VDD above the start threshold before setting at 10V for UCC3807-2.
Note 7: Does not include current in external timing RC network.
PIN DESCRIPTIONS
COMP: COMP is the output of the error amplifier and the directly affected by the leading edge blanking and the CS
input of the PWM comparator. The error amplifier in the to OUT propagation delay.
UCC3807 is a low output impedance, 2MHz operational
The overcurrent comparator is only intended for fault
amplifier. COMP can both source and sink current. The
sensing. Exceeding the overcurrent threshold causes a
error amplifier is internally current limited, which allows
soft start cycle.
zero duty cycle by externally forcing COMP to GND.
FB: The inverting input to the error amplifier. For best
The UCC3807 family features built-in full cycle soft start.
stability, keep connections to FB as short as possible
Soft start is implemented as a clamp on the maximum
and stray capacitance as small as possible.
COMP voltage.
GND: Reference ground and power ground for all func-
tions of the part.
CS: Current sense input. There are two current sense
comparators on the chip, the PWM comparator and an
OUT: The output of a high current power driver capable
of driving the gate of a power MOSFET with peak cur-
rents exceeding 1A. OUT is actively held low when VDD
is below the UVLO threshold.
overcurrent comparator.
The UCC3807 also contains a leading edge blanking cir-
cuit, which disconnects the external CS signal from the
current sense comparator during the 100ns interval
immediately following the rising edge of the signal at the
OUT pin. In most applications, no analog filtering is
required on CS. Compared to an external RC filtering
technique, leading edge blanking provides a smaller
effective CS to OUT propagation delay. Note, however,
that the minimum non-zero on-time of the OUT signal is
The high current power driver consists of MOSFET out-
put devices in a totem pole configuration.This allows the
output to switch from VDD to GND.The output stage also
provides a very low impedance which minimizes over-
shoot and undershoot. In most cases, external Schottky
clamp diodes are not required.
3
UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3
PIN DESCRIPTIONS (cont.)
TRIG/DISCH: Oscillator control pins. TRIG is the oscilla-
For best performance, keep the lead from CT to GND as
tor timing input, which has an RC-type charge/discharge short as possible. A separate ground connection for CT is
signal controlling the chip’s internal oscillator. DISCH is desirable. The minimum value of RA is 10kΩ, the mini-
the pin which provides the low impedance discharge mum value of RB is 2.2kΩ, and the minimum value of CT
path for the external RC network during normal opera- is 47pF.
tion. Oscillator frequency and maximum duty cycle are
computed as follows:
VDD: The power input connection for this device. Total
VDD current is the sum of quiescent current and the
average OUT current. Knowing the operating frequency
and the MOSFET gate charge (Qg), average OUT cur-
rent can be calculated from
1.4
frequency ≈
(RA + 2RB)CT
RA + RB
duty cycle ≈
IOUT = Qg F, where F is frequency.
·
RA + 2RB
To prevent noise problems, bypass VDD to GND with a
ceramic capacitor as close to the chip as possible in par-
allel with an electrolytic capacitor.
as shown in Figure 1.
UDG-95002-1
Figure 1. Oscillator Block Diagram
APPLICATIONS INFORMATION
T1:
Core:
Primary:
Secondary:
The circuit shown in Figure 2 illustrates the use of the
UCC3807 in a typical off-line application. The 100W,
200kHz, universal input forward converter produces a
regulated 12VDC at 8 Amps. The programmable maxi-
mum duty cycle of the UCC3807 allows operation down
to 80VRMS and up to 265VRMS with a simple RCD
clamp to limit the MOSFET voltage and provide core
reset. In this application the maximum duty cycle is set to
about 65%. Another feature of the design is the use of a
flyback winding on the output filter choke for both boot-
strapping and voltage regulation. This method of loop
closure eliminates the optocoupler and secondary side
regulator, common to most off-line designs, while provid-
ing good line and load regulation.
Magnetics Inc. #P-42625-UG (ungapped)
28 turns of 2x #26AWG
6 turns of 50x0.2mm Litz wire
L1:
Core:
Magnetics Inc. #P-42625-SG-37 (0.020” gap)
Main Winding: 13 turns of 2x #18AWG
Second Winding:11 turns of #26AWG
Magnetics Inc.
900 E. Butler Road
P.O. Box 391
Butler, PA 16003
Tel: (412) 282-8282
Fax: (412) 282-6955
4
UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3
APPLICATIONS INFORMATION (cont.)
UDG-96174
Figure 2.Typical Off-line Application Using UCC3807-2
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
5
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