UCC1857 [TI]
Isolated Boost PFC Preregulator Controller; 隔离升压PFC预调节器控制器
| 型号： | UCC1857 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Isolated Boost PFC Preregulator Controller |
| 文件： | 总10页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC1857
UCC2857
UCC3857
PRELIMINARY
Isolated Boost PFC Preregulator Controller
FEATURES
DESCRIPTION
• PFC With Isolation, V < V
The UCC3857 provides all of the control functions necessary for an Iso-
lated Boost PFC Converter. These converters have the advantage of trans-
former isolation between primary and secondary, as well as an output bus
voltage that is lower than the input voltage. By providing both power factor
correction and down conversion in a single power processing stage, the
UCC3857 is ideal for applications which require high efficiency, integration,
and performance.
O
IN
• Single Power Stage
• Zero Current Switched IGBT
• Programmable ZCS Time
• Corrects PF to >0.99
The UCC3857 brings together the control functions and drivers necessary
to generate overlapping drive signals for external IGBT switches, and pro-
vides a separate output to drive an external power MOSFET which pro-
vides zero current switching (ZCS) for both the IGBTs. Full programmability
is provided for the MOSFET driver delay time with an external RC network.
ZCS for the IGBT switches alleviates the undesirable turn off losses typi-
cally associated with these devices. This allows for higher switching fre-
quencies, smaller magnetic components and higher efficiency. The power
factor correction (PFC) portion of the UCC3857 employs the familiar aver-
age current control scheme used in previous Unitrode controllers. Internal
circuitry changes, however, have simplified the design of the PFC section
and improved performance.
• Fixed Frequency, Average Current
Control
• Improved RMS Feedforward
• Soft Start
• 9V to 18V Supply V Range
• 20-Pin DW, N, J, and L Packages
(continued)
TYPICAL APPLICATION CIRCUIT
+
T1
C
F
RECTIFIED
V
AC INPUT
BIAS
SUPPLY
QA
Q1
Q2
OUT
–
R
S
FEEDBACK
CKT
REF
Z
C
OPTO
R
AC
13
3
PKLMT MOUT
IAC
7
8
4
15
CA–
CAO VIN
VD
1
2
MOSDRV 14
IGDRV1 16
IGDRV2 18
DELAY 12
CRMS
UCC3857
10 VA–
11 VAO
Z
V
REF
REF
5
VREF
SS
20
RT
19
CT
20
PGND
17
AGND
6
UDG-98065
02/99
UCC1857
UCC2857
UCC3857
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION (continued)
Input Supply Voltage (VIN, VD). . . . . . . . . . . . . . . . . . . . . . 18V
General Analog/Logic Inputs
Controller improvements include an internal 6 bit A-D
converter for RMS input line voltage detection, a zero
load power circuit, and significantly lower quiescent op-
erating current. The A-D converter eliminates an external
2 pole low pass filter for RMS detection.
(CRMS, MOUT, CA–, VA–, CT, RT, PKLMT)
(Maximum Forced Voltage). . . . . . . . . . . . . . . . –0.3V to 5V
IAC (Maximum Forced Current) . . . . . . . . . . . . . . . . . . . 300µA
Reference Output Current . . . . . . . . . . . . . . . Internally Limited
Output Current (MOSDRV, IGDRV1, IGDRV2)
Pulsed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . −55°C to +150°C
Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . +300°C
This simplifies the converter design, eliminates 2nd har-
monic ripple from the feedforward component, and pro-
vides an approximate 6 times improvement in input line
transient response. The zero load power comparator
prevents energy transfer during open load conditions
without compromising power factor at light loads. Low
startup and operating currents which are achieved
through the use of Unitrode's BCDMOS process simplify
the auxiliary bootstrap supply design.
Unless otherwise indicated, voltages are reference to ground
and currents are positive into, negative out of the specified ter-
minal. Pulsed is defined as a less than 10% duty cycle with a
maximum duration of 500 s. Consult Packaging Section of
Databook for thermal limitations and considerations of pack-
ages.
Additional features include: under voltage lockout for reli-
able off-line startup, a programmable over current shut-
down, an auxiliary shutdown port, a precision 7.5V
reference, a high amplitude oscillator ramp for improved
noise immunity, softstart, and a low offset analog square,
multiple and divide circuit. Like previous Unitrode PFC
controllers, worldwide operation without range switches
is easily implemented.
CONNECTION DIAGRAMS
DIL-20, SOIC- 20 (Top View)
J, N and DW Packages
PLCC-20 (Top View)
L Package
IAC
IAC
CRMS
MOUT
VIN
20 CT
1
2
3
4
5
6
7
8
9
CRMS
MOUT
CT
RT
19 RT
18 IGDRV2
17 PGND
16 IGDRV1
15 VD
3
2
1
20 19
18
VIN
VREF
AGND
CA–
4
5
6
7
8
IGDRV2
PGND
17
16
15
14
VREF
AGND
CA–
IGDRV1
VD
14 MOSDRV
13 PKLMT
12 DELAY
11 VAO
CAO
MOSDRV
9
10 11 12 13
CAO
SS
PKLMT
DELAY
VAO
SS
VA–
VA– 10
2
UCC1857
UCC2857
UCC3857
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0°C to 70°C for the
UCC3857, –40°C to +85°C for the UCC2857, and –55°C to +125°C for the UCC1857, VVIN, VVD = 12V, RT = 19.2K, CT = 680pF.
TA = TJ.
PARAMETER
Input Supply
TEST CONDITIONS
MIN
TYP
MAX UNITS
Supply Current, Active
Supply Current, Startup
VIN UVLO Threshold
UVLO Threshold Hysteresis
Reference
No Load on Outputs, VVD = VVIN
3.5
60
5
mA
µA
V
No Load on Outputs, VVD = VVIN
TBD
13.75 15.5
3
3.75
TBD
V
Output Voltage (VVREF
)
TJ = 25°C, IREF = 1mA
7.387
7.368
7.313
7.5
7.5
7.5
2
7.613
7.631
7.687
10
V
V
Over Temperature, UCC3857
Over Temperature, UCC1857, UCC2857
IREF = 1mA to 10mA
V
Load Regulation
Line Regulation
Short Circuit Current
Current Amplifier
Input Offset Voltage
Input Bias Current
Input Offset Current
CMRR
mV
mV
mA
VVIN = VVD = 12V to 16V
2
15
V
VREF = 0V
–55
–30
(Note 1)
–3
0
–50
25
3
mV
nA
nA
dB
dB
V
(Note 1)
(Note 1)
VCM = 0V to 1.5V, VCAO = 3V
VCM = 0V, VCAO = 2V to 5V
Load on CAO = 50µA, VMOUT = 1V, VCA– = 0V
Load on CAO = 50µA, VMOUT = 0V, VCA– = 1V
Source : VCA– = 0V, VMOUT = 1V, VCAO = 3V
Sink : VCA– = 1V, VMOUT = 0V, VCAO = 3V
fIN = 100kHz, 10mV p – p
80
AVOL
65
6
85
VOH
7
VOL
0.2
–150
30
V
Maximum Output Current
µA
mA
MHz
5
3
50
Gain Bandwidth Product
Voltage Amplifier
Input Voltage
5
Measured on VVA–, VVAO = 3V
Measured on VVA–, VVAO = 3V
VVAO = 1V to 5V
2.9
5.3
3
3.1
V
nA
dB
V
Input Bias Current
AVOL
–50
75
VOH
Load on VVAO= –50µA, VVA–= 2.8V
Load on VVAO= 50µA, VVA–= 3.2V
Source: VVA– = 2.8V, VVAO = 3V
Sink: VVA– = 3.2V, VVAO= 3V
5.55
0.1
–12
20
5.7
0.45
–5
VOL
V
Maximum Output Current
–20
5
mA
mA
30
Oscillator
Initial Accuracy
TJ = 25°C
42.5
40
50
50
1
57.5
60
kHz
kHz
%
Voltage Stability
CT Ramp Peak-Valley Amplitude
CT Ramp Valley Voltage
Output Drivers
VOH
VVIN = 12V to 18V
4
9
4.5
1.5
5
V
V
IL = –100mA
IL = 100mA
CLOAD = 1nF
CLOAD = 1nF
10
0.1
25
10
V
V
VOL
0.5
Rise Time
TBD
TBD
ns
ns
Fall Time
Trailing Edge Delay
Delay Time
RD = 12k, CD = 200pF, VVAO = 4V
1.6
2
2.4
µs
3
UCC1857
UCC2857
UCC3857
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0°C to 70°C for the
UCC3857, –40°C to +85°C for the UCC2857, and –55°C to +125°C for the UCC1857, VVIN, VVD = 12V, RT = 19.2K, CT = 680pF.
TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Soft Start
Charge Current
10
µA
Shutdown Comparator Threshold
Multiplier
Measured on SS
0
0.4
2
V
Output Current, IAC Limited
Output Current, Power Limited
Output Current, Zero
Gain Constant
IAC = 100µA, VVAO = 5.5V, VCRMS = 0V
IAC = 100µA, VVAO = 5.5V, VCRMS = 1V
IAC = 0
–200
–200
0
µA
µA
µA
1/V
–2
2.5
Zero Power, Peak Current
Zero Power Comparator Threshold Measured on VAO
0.5
0
V
V
Peak Current Limit Comparator
Threshold
Measured on PKLMT
Note 1: Common mode voltages = 0V, VCAO = 3V
PIN DESCRIPTIONS
AGND: Reference point of the internal reference and all IAC: A resistor is connected to the rectified AC input line
thresholds, as well as the return for the remainder of the voltage from IAC. This provides the internal multiplier
device except for the output drivers.
and the RMS detector with instantaneous line voltage in-
formation.
CA–: Inverting input of the inner current loop error ampli-
fier.
IGDRV1: Driver output for one of the two external IGBT
power switches.
CAO: Output of the inner current loop error amplifier.
This output can swing between approximately 0.2V and IGDRV2: Driver output for one of the two external IGBT
6V. It is one of the inputs to the PWM comparator. power switches.
VAO: This is the output of the voltage loop error ampli- MOSDRV: Driver output for the external power MOSFET
fier. It is internally clamped to approximately 5.6V by the switch.
UCC3857 and can swing as low as approximately 0.1V.
MOUT: Output of the analog multiply and divide circuit.
Voltages below 0.5V on VAO will disable the MOSDRV
The output current from MOUT is fed into a resistor to
output and force the IGDRV1 and IGDRV2 outputs to a
the return leg of the input bridge. The resultant waveform
zero overlap condition.
forms the sine reference for the current error amplifier.
CRMS: A capacitor is connected between CRMS and
PKLMT: Inverting input of the peak current limit com-
ground to average the AC line voltage over a half cycle.
parator. The threshold for this comparator is nominally
CRMS is internally connected to the RMS detection cir-
set to 0V. The peak limit comparator terminates the
MOSDRV, IGDRV1 and IGDRV2 outputs when tripped.
cuitry.
CT: A capacitor (low ESR, ESL) is tied between CT and
PGND: Return for all high level currents, internally tied to
ground to set the ramp generator switching frequency in
the output driver stages of the UCC3857.
conjunction with RT. The ramp generator frequency is ap-
RT: A resistor, R is tied between RT and ground to set
T
proximately given by:
the charging current for the internal ramp generator. The
UCC3857 provides a temperature compensated 3.0V at
0.67
fSW
≈
.
RT •CT
RT. The oscillator charging current is therefore: 3.0V/R .
T
Current out of RT should be limited to 250µA for best
performance.
DELAY: A resistor to VREF and a capacitor to AGND are
connected to DELAY to set the overlap delay time for the
MOSDRV output stage. The overlap delay function can
be disabled by removing the capacitor to AGND.
VA–: This is the feedback input for the outer voltage con-
trol loop. An external opto isolator circuit provides the
4
UCC1857
UCC2857
UCC3857
PIN DESCRIPTIONS (continued)
output voltage regulation information to VA– across the VIN can be isolated from each other with an RC lowpass
isolation barrier. filter for better supply noise rejection.
SS: A capacitor is connected between SS and GND to VIN: Input voltage supply to the UCC3857. This voltage
provide the UCC3857 soft start feature. The voltage on must be limited to less than 18VDC. The UCC3857 is en-
VAO, is clamped to approximately the same voltage as abled when the voltage on VIN exceeds 13.75V (nomi-
nal).
SS. An internal 10µA (nominal) current source is pro-
vided by the UCC3857 to charge the soft start capacitor.
VREF: Output of the precision 7.5V reference. A 0.01µF
to 0.1µF low ESR, ESL bypass capacitor is recom-
mended between VREF and AGND for best perform-
VD: Positive supply rail for the three output driver stages.
The voltage applied to VD must be limited to less than
18VDC. VD should be bypassed to PGND with a 0.1µF ance.
to 1.0µF low ESR, ESL capacitor for best results. VD and
VCT (PIN 20) &
CAO (PIN 8)
V
CLOCK
(INTERNAL)
TOGGLE F/F Q
(INTERNAL)
IGDRV1
(PIN 16)
IGDRV2
(PIN 18)
TD1
MOSDRV
(PIN 14)
UDG-98217
Figure 1. Typical control circuit timing diagram.
APPLICATION INFORMATION
UCC3857 is designed to provide a solution for single The circuit shown in the Typical Application Circuit pro-
stage power factor correction and step-down or step-up vides several advantages over a more conventional ap-
function, using an isolated boost converter. The Typical proach of deriving a DC bus voltage from AC line with
Application Circuit shows the implementation of a typical power factor correction. The conventional approach uses
isolated boost converter using IGBTs as main switches in two power conversion stages and has higher cost and
push-pull configuration and using a MOSFET as an auxil- complexity. With the use of UCC3857, the dual function-
iary switch to accomplish soft-switching of IGBTs. Many ality of power factor correction and voltage step-down is
variations of this implementation are possible including combined into a single stage.
bridge-type circuits. The presense of low frequency ripple
The power stage comprises a current-fed push-pull con-
on the output makes this approach practical for distrib-
verter where the ON times of the push-pull switches (Q1
uted bus applications. It will not provide the highly regu-
and Q2) are overlapped to provide effective duty cycle of
lated low ripple outputs typically required by logic level
a conventional PWM boost converter. When only one
supplies.
switch is on, the power is transferred to the output
5
UCC1857
UCC2857
UCC3857
APPLICATION INFORMATION (continued)
BLOCK DIAGRAM
VREF
5
MOUT
CAO
8
DELAY
12
VD
15
3
VIN
IAC
4
1
2
7.5V
REF
ENBL
TRAILING
EDGE
DELAY
UVLO
13.75V / 10V
REF GOOD
PWM
COMP
CURRENT AMP
RMS DETECT
X
÷
CRMS
AND
MULT
CONDITIONING
X
PEAK LIMIT
COMP
14 MOSDRV
DRIVER
R
R
ZERO POWER
VOLTAGE AMP
R
S
VA– 10
Q
3.0V
PWM
LATCH
0.5V
VD
16 IGDRV1
DRIVER
VD
10µA
Q
SD
SD
SS
9
TOGGLE
F/F
1.0V
IGDRV2
18
ENBL
ALWAYS
ON
Q
DRIVER
SD
OSCILLATOR
17 PGND
VAO 11
6
AGND
CA–
7
13
19
20
PKLMT
RT
CT
UDG-98218
through the transformer and the output rectifier. It can (TD1) effectively adds to the boost inductor charge pe-
riod. The voltage stress of the MOSFET is half the stress
of the IGBTs under normal operating conditions. How-
ever, QA can see much higher voltage stress under
start-up and short circuit conditions as the converter oper-
ates in a flyback mode then. For different operating re-
quirements or constraints (e.g. single North American line
operation), the choice of switching components may be
different (e.g. MOSFETs for Q1 and Q2 and no QA) as
the voltage stress is different. In that case, UCC3857 can
still be used without using the MOSDRV output.
be seen that the¸÷ operation on the primary side of the
circuit is that of a boost converter and UCC3857 pro-
vides input current programming using average current
mode control to achieve unity power factor. The trans-
former turns ratio can be used to get the required level
of output voltage (higher or lower than the peak line volt-
age). The transformer also provides galvanic isolation
for the output voltage.
Power stage optimization involves design and selection
of components to meet the performance and cost objec-
tives. These include the power switches, transformer
and inductor design.
Transformer design is very critical in this topology. The
push-pull transformer must have minimal leakage induc-
tance between the primary and secondary windings. Simi-
larly, the leakage between the two primary windings must
be minimized. In practice, it is hard to achieve both tar-
gets without using sophisticated construction techniques
such as interleaving, use of foils etc. In many cases, it
may be beneficial to use a planar transformer to achieve
these objectives. The effects of higher leakage induc-
tance include higher voltage stresses, ringing, power
losses and loss of available duty cycle. The high voltage
levels make it difficult to design effective snubber circuits
for this leakage induced ringing.
The choice of IGBTs is based on their advantage over
MOSFETs at higher voltages. For universal line opera-
tion, the voltage stress on the push-pull switches can
approach 1000V. However, the slow turn-off of IGBTs
can contribute high switching losses and the use of
MOSFET (QA) helps turn the IGBTs off with zero voltage
across them (ZCS turn-off). This is accomplished by
keeping QA on (beyond the turn-off of Q1 or Q2 – see
Fig. 1 for waveforms) to allow the inductor current to di-
vert from IGBT to MOSFET while the IGBT is turning off
and still maintain zero volts. The MOSFET delay time
6
UCC1857
UCC2857
UCC3857
APPLICATION INFORMATION (cont.)
The design of the boost inductor is very similar to the error amplifier output. Unlike prior techniques of RMS
conventional boost converter. However, as shown in the voltage sensing, UCC3857 employs a patent pending
Typical Application Circuit, an additional winding con- technique to simplify the RMS voltage generation and
nected to the output through a diode is required on the eliminate performance degradation caused by the
boost inductor. This winding must have the same turns previous techniques. With the novel technique (shown in
ratio as the transformer and meet the isolation require- Fig. 3), need for external 2-pole filter for V
generation
RMS
ments. This winding is required to provide a discharge is eliminated. Instead, the IAC current is mirrored and
path for the inductor energy when the push-pull switches used to charge an external capacitor (C ) during a
CRMS
are both off. During start-up, when the output voltage is half cycle. The voltage on CRMS takes the integrated si-
zero, the converter can see very high inrush currents. nusoidal shape and is given by equation 2. At the end of
The overcurrent protection circuit of UCC3857 will shut the half-cycle, CRMS voltage is held and converted into
down all the outputs when the set threshold is crossed. a 6-bit digital word for further processing in the ACU.
At that instance, the boost inductor auxiliary winding di-
C
is discharged and readied for integration during
CRMS
rects the energy to the output. This is a preferred manner next half cycle.
of bringing the output voltage up to prevent the main
The advantage of this method is that the second har-
switches from handling the high levels of inrush current.
However, when the auxiliary winding is transferring the
power to the output, the voltage stress across QA be-
comes input voltage plus the reflected output volt-
age–higher than its steady state value of reflected output
voltage.
monic ripple on the V
signal is virtually eliminated.
RMS
Such second harmonic ripple is unavoidable with the lim-
ited roll-off of a conventional 2-pole filter and results in
3rd harmonic distortion in the input current signal. The
dynamic response to the input line variations is also im-
proved as a new V
signal is generated every cycle.
RMS
Chip Bias Supply and Start-up
IAC (pk )
(2)
( )
1−cosωt
VCRMS
=
UCC3857 is implemented using Unitrode’s BCDMOS
process which allows minimization of the start-up (60 A
typical) and operating (3.5mA typical) supply currents. It
results in significantly lower power consumption in the
trickle charge resistor used to start-up the IC.
2• ω • CCRMS
IAC (pk )
(2a)
VCRMS (pk )=
ω • CCRMS
For proper operation, I (pk) should be selected to be
100 A at peak line voltage. For universal input voltage
AC
Oscillator Set-up
The oscillator of UCC3857 is designed to have a wide
ramp amplitude (4.5V p–p) for higher noise immunity.
The CT pin has the sawtooth waveshape and during the
discharge time of C , a clock pulse is generated. During
the discharge period, the effective internal impedance to
GND is 600 . Based on this, the discharge time is given
with peak value of 265 VAC, this means R = 3.6M. The
AC
noise sensitivity of the IC requires a small bypass capaci-
tor for high frequency noise filtering. The value of this ca-
T
pacitor should be limited to 220nF maximum. The V
CRMS
value should be approximately 1V at the peak of low line
(80 VAC) to minimize any digitization errors. The peak
by 831•C . As shown in the waveforms of Fig. 1, the in-
T
value of V
at high line then becomes 3.5V. The de-
CRMS
ternal clock pulse width is equal to the discharge time
and that sets the minimum dead time between IGDRV1
and IGDRV2. The clock frequency is given by
sired C
can be calculated from equation 2 to be
CRMS
75nF for 60Hz line.
The multiplier output current is given by equation (3) with
K = 0.33.
1
1
(1)
fSW
=
≈
(1.5 • RT +831)• CT (1.5 • RT • CT )
(VVAO – 0.5)• IAC • K
(3)
IMULT
=
2
VCRMS
The IGDRV1 and IGDRV2 outputs are switched at half
the clock frequency while MOSDRV is switched at the
clock frequency.
The multiplier peak current is limited to 200 A and the
selected values for I and V should ensure that
AC
CRMS
Reference Signal (I
) generation
MULT
the current is within this range. Another limitation of the
multiplier is that I can not exceed two times the IAC
Like the UC3854 series, the UCC3857 has an analog
computation unit (ACU) which generates a reference cur-
rent signal for the current error amplifier. The inputs to
the ACU are signals proportional to instantaneous line
voltage, input voltage RMS information and the voltage
MULT
current, limiting the minimum voltage on V
.
CRMS
The discrete nature of the RMS voltage feedforward
means that there are regions of operation where the in-
7
UCC1857
UCC2857
UCC3857
APPLICATION INFORMATION (cont.)
R
AC
IAC
1
A
B
C
A•B
C
VAO
CRMS
2
CCRMS
6 BIT
WORD
MULTI
DAC
A
D
REGISTER
(X2)
Figure 3. Novel RMS voltage generation scheme.
put voltage changes, but the V
value fed into the bridge. In such instances, the feedforward effect does
RMS
multiplier does not change. The voltage error amplifier not take place and the controller functionality is compro-
compensates for this by changing its output to maintain mised. For UCC3857, the I current should go below
AC
the required multiplier output current. When the output of
the ADC changes, there is a jump in the output of the er-
ror amplifier. This has minimal impact on the overall con-
verter operation.
10 A for the zero crossing detection to take place. It is
recommended that the capacitor value be kept low
enough for light load operation or that the alternative
scheme shown in Fig. 4 be used for I sense.
AC
Another key consideration with the RMS voltage scheme
is that it relies on the zero-crossing of the Iac signal to be
effective. At very light loads and high line conditions, the
rectified AC does not quite reach zero if a large capacitor
is being used for filtering on the rectified side of the
Gate Drive Considerations
The gate drive circuits in UCC3857 are designed for high
speed driving of the power switches. Each drive circuit
consists of low impedance pull-up and pull-down DMOS
output stages. The UCC3857 provides separate supply
and ground pins (VD and PGND) for the driver stages.
These pins allow better local bypassing of the driver cir-
cuits. VD can also be used to ensure that the SOA limits
of the output stages are not violated when driving high
peak current levels. For this, VD can be kept as low as
possible (e.g. 10V) while VIN can go higher to handle the
UVLO requirements.
BRIDGE
AC LINE
RECTIFIER
Current Amplifier Set-up
Once the multiplier is set-up by choosing the V
RMS
R
AC
UCC3857
range, the current amplifier components can be de-
signed. The maximum multiplier output is at low line, full
load conditions. The inductor peak current also occurs at
the same point. The multiplier terminating resistor can be
determined using equation 4.
1
IAC
Figure 4. Alternative implementation for sensing I
.
AC
8
UCC1857
UCC2857
UCC3857
IL−PK • RSENSE
(4) with line feedforward is indicative of load power. The de-
RMULT
=
lay time is programmed with external components, R
IMULT −PK
D
and C . The sequence of events starts when the inter-
D
The current amplifier can be compensated using a previ- nal CLK signal resets latch U2, causing PWMDEL to go
ously presented techniques (U-134) summarized here. A high and the Q output to go low. C was discharged via
D
simplified high frequency model for inductor current to M1 and is held low until the internal PWM signal goes
duty cycle transfer function is given by
low (indicating turn-off of either of the IGBT drives). At
this point M1 turns off and C charges towards the 7.5V
D
(5)
reference through R . A comparator U1 compares this
iL
d
Vo
SL
D
Gid (s)=
=
voltage to the voltage error amplifier output (V
). When
VAO
the voltage on C is greater than V
, the latch U2 is
VAO
D
set causing PWMDEL to go low. PWMDEL is logically
The gain of the current feedback path at the frequency of
interest (crossover) is given by
7.5V REF
(6)
RZ
d
1
=RSENSE
•
•
RI VSE
iL
R
CLK
D
DELAY
MOSDRV
Where VSE is the ramp amplitude (p-p) which is 4.5V for
UCC3857. Combining equations. 5 and 6 yields the loop
gain of the current loop and equating it to 1 at the de-
sired crossover frequency can result in a design value for
12
S
Q
Q
PWMDEL
C
U2
D
VAO
R
CLK
R . The current loop crossover frequency should be lim-
Z
ited to about 1/3 of the switching frequency of the con-
verter to ensure stability. See Unitrode Application Note
U-140 for further information.
PWM
Trailing Edge Delay
Figure 5. Circuit for adaptive MOSFET delay
generation.
As shown in the waveforms of Fig. 1, the modified iso-
lated boost converter requires drive signals for the two
main (IGBT) switches and the auxiliary (MOSFET) switch
with certain timing relationships. The delay between
turn-off of an IGBT and turn-off of the MOSFET can be
programmed for the UCC1857. In a PFC application, the
input line varies from zero to the AC peak level, resulting
in a wide range of required duty ratios. A fixed delay
time will induce line current distortion at the peaks of the
AC line under high line and/or light load conditions. This
is caused by the minimum controllable duty ratio im-
posed on the modulator by the fixed delay. If the mini-
mum controllable duty ratio is fixed, the inner current
loop can exhibit a limit cycle oscillation at the line peaks,
inducing line current distortion.
ANDed with CLK to produce the signal which commands
the MOSFET driver output (MOSDRV). The delay time,
TD1, is given by
7.5 –VVAO
7.5
(7)
TD1= – RD • CD
•
n
This technique reduces the overlap delay at light loads or
high lines, but maintains a longer delay when the line
voltage is low or the load is heavy. This by definition re-
duces the minimum controllable duty ratio to an accept-
able level, and is programmable by the user. Reducing
the delay time under light current conditions is accept-
able since the IGBT current is directly proportional to
The UCC1857 has an adaptive MOSFET delay genera-
tor, which is directly modulated by load power demand.
Referring to Fig. 5, this circuit directly varies the delay
time based on the output level of the voltage error ampli-
fier, which in an average current mode PFC converter
load current. By providing programming flexibility with R
D
and C , the delay times can be optimized for current and
D
future classes of IGBT switches. The delay can also be
set to zero by removing C from the circuit.
D
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9
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