UCC21520ADW_技术文档

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021

UCC21520 4-A, 6-A, 5.7-kV_RMSIsolated Dual-Channel Gate Driver

1 Features

3 Description

•

Universal: dual low-side, dual high-side or half-

bridge driver

Operating temperature range –40 to +125°C

Switching parameters:

– 19-ns typical propagation delay

– 10-ns minimum pulse width

– 5-ns maximum delay matching

– 6-ns maximum pulse-width distortion

Common-mode transient immunity (CMTI) greater

than 100 V/ns

The UCC21520 and the UCC21520A are isolated

dual-channel gate drivers with 4-A source and 6-A

sink peak current. It is designed to drive power

MOSFETs, IGBTs, and SiC MOSFETs up to 5-MHz

with best-in-class propagation delay and pulse-width

distortion.

•

The input side is isolated from the two output

drivers by a 5.7-kV_RMSreinforced isolation barrier,

with a minimum of 100-V/ns common-mode transient

immunity (CMTI). Internal functional isolation between

the two secondary-side drivers allows a working

•

Surge immunity up to 12.8 kV

Isolation barrier life >40 years

voltage of up to 1500 V_DC

.

4-A peak source, 6-A peak sink output

TTL and CMOS compatible inputs

3-V to 18-V input VCCI range to interface with both

digital and analog controllers

Up to 25-V VDD output drive supply

– 5-V and 8-V VDD UVLO options

Programmable overlap and dead time

Rejects input pulses and noise transients shorter

than 5 ns

Every driver can be configured as two low-side

drivers, two high-side drivers, or a half-bridge driver

with programmable dead time (DT). A disable pin

shuts down both outputs simultaneously when it is set

high, and allows normal operation when left open or

grounded. As a fail-safe measure, primary-side logic

failures force both outputs low.

•

Device Information⁽¹⁾

•

Fast disable for power sequencing

Industry standard wide body SOIC-16 (DW)

package

PART NUMBER

UCC21520DW

UCC21520ADW

PACKAGE

BODY SIZE (NOM)

DW SOIC (16) 10.30 mm × 7.50 mm

•

Safety-related certifications:

– 8000-V_PKreinforced Isolation per DIN V VDE V

0884-11:2017-01

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

– 5.7-kV_RMSisolation for 1 minute per UL 1577

– CSA certification per IEC 60950-1, IEC

62368-1, IEC 61010-1 and IEC 60601-1 end

equipment standards

VCCI 3,8

16 VDDA

15 OUTA

14 VSSA

Driver

DEMOD UVLO

MOD

INA

DIS

NC

DT

1

5

7

6

– CQC certification per GB4943.1-2011

2 Applications

Disable,

UVLO

and

13 NC

12 NC

Functional Isolation

•

HEV and BEV battery chargers

Isolated converters in DC-DC and AC-DC power

supplies

Server, telecom, it and industrial infrastructures

Motor drive and DC-to-AC solar inverters

LED lighting

Deadtime

11 VDDB

10 OUTB

Driver

INB

2

4

•

MOD

DEMOD UVLO

GND

9

VSSB

Inductive heating

Uninterruptible power supply (UPS)

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC21520, UCC21520A

SLUSCJ9E – JUNE 2016 – REVISED DECEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................4

7.4 Thermal Information....................................................5

7.5 Power Ratings.............................................................5

7.6 Insulation Specifications............................................. 5

7.7 Safety-Related Certifications...................................... 6

7.8 Safety-Limiting Values................................................ 6

7.9 Electrical Characteristics.............................................7

7.10 Switching Characteristics..........................................8

7.11 Insulation Characteristics Curves..............................9

7.12 Typical Characteristics............................................10

8 Parameter Measurement Information..........................14

8.1 Propagation Delay and Pulse Width Distortion.........14

8.2 Rising and Falling Time.............................................14

8.3 Input and Disable Response Time............................14

8.4 Programable Dead Time...........................................15

8.5 Power-up UVLO Delay to OUTPUT..........................15

8.6 CMTI Testing.............................................................16

9 Detailed Description......................................................17

9.1 Overview...................................................................17

9.2 Functional Block Diagram.........................................17

9.3 Feature Description...................................................18

9.4 Device Functional Modes..........................................21

10 Application and Implementation................................22

10.1 Application Information........................................... 22

10.2 Typical Application.................................................. 23

11 Power Supply Recommendations..............................34

12 Layout...........................................................................35

12.1 Layout Guidelines................................................... 35

12.2 Layout Example...................................................... 36

13 Device and Documentation Support..........................38

13.1 Third-Party Products Disclaimer............................. 38

13.2 Documentation Support.......................................... 38

13.3 Certifications........................................................... 38

13.4 Receiving Notification of Documentation Updates..38

13.5 Support Resources................................................. 38

13.6 Trademarks.............................................................38

13.7 Electrostatic Discharge Caution..............................38

13.8 Glossary..................................................................38

14 Mechanical, Packaging, and Orderable

Information.................................................................... 38

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (March 2020) to Revision E (December 2021)

Page

•

Updated Features ..............................................................................................................................................1

Changed t_PWDin Switching Characteristics .......................................................................................................8

Changes from Revision C (December 2019) to Revision D (March 2020)

Page

•

Added cross reference to table note1 ................................................................................................................4

Added VDDx power-up delay typ and max values ............................................................................................ 8

Changed DT pin configuration recommendations ........................................................................................... 21

Added update to bootstrap circuit recommendations....................................................................................... 24

Added update to gate resistor selection recommendations .............................................................................25

Added gate to source resistor recommendation ..............................................................................................26

Added update to Cboot selection recommendations .......................................................................................28

2

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5 Description (continued)

Each device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the

driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under

voltage lock-out (UVLO) protection.

With all these advanced features, the UCC21520 and the UCC21520A enable high efficiency, high power

density, and robustness in a wide variety of power applications.

6 Pin Configuration and Functions

INA

INB

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDDA

OUTA

VSSA

NC

VCCI

GND

DISABLE

DT

NC

VDDB

OUTB

VSSB

NC

VCCI

Not to scale

Figure 6-1. DW Package 16-Pin SOIC Top View

Table 6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled

low internally if left open. It is recommended to tie this pin to ground if not used to achieve

better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when

connecting to a micro controller with distance.

DISABLE

5

I

Programmable dead time function.

Tying DT to VCCI allows the outputs to overlap. Placing a 500-Ω to 500-kΩ resistor (RDT)

between DT and GND adjusts dead time according to: DT (in ns) = 10 x R_DT(in kΩ). It is

recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with R_DT

to achieve better noise immunity. It is not recommended to leave DT floating.

DT

6

GND

INA

4

1

P

I

Primary-side ground reference. All signals in the primary side are referenced to this ground.

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

INB

2

I

NC

7

–

No Internal connection.

NC

12

13

15

10

No internal connection.

NC

–

No internal connection.

OUTA

OUTB

O

Output of driver A. Connect to the gate of the A channel FET or IGBT.

Output of driver B. Connect to the gate of the B channel FET or IGBT.

Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor

located as close to the device as possible.

VCCI

VDDA

3

8

P

Primary-side supply voltage. This pin is internally shorted to pin 3.

Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL

capacitor located as close to the device as possible.

16

Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL

capacitor located as close to the device as possible.

VDDB

11

P

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Table 6-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

VSSA

VSSB

NO.

14

9

P

Ground for secondary-side driver A. Ground reference for secondary side A channel.

Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1) P = Power, G = Ground, I = Input, O = Output

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

20

UNIT

V

Input bias pin supply voltage

Driver bias supply

VCCI to GND

VDDA-VSSA, VDDB-VSSB

30

V

V_VDDA+0.3,

V_VDDB+0.3

OUTA to VSSA, OUTB to VSSB

–0.3

–2

V

Output signal voltage

OUTA to VSSA, OUTB to VSSB,

Transient for 200 ns

V_VDDA+0.3,

V_VDDB+0.3

INA, INB, DIS, DT to GND

INA, INB Transient for 50 ns

VSSA-VSSB, VSSB-VSSA

–0.3

–5

V_VCCI+0.3

1500

V

Input signal voltage

Channel to channel voltage

V

(2)

Junction temperature, T_J

–40

–65

150

°C

Storage temperature, T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) To maintain the recommended operating conditions for T_J, see the Section 7.4.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCCI

VCCI Input supply voltage

Driver output bias supply

3

18

V

VDDA,

VDDB

UCC21520ADW – 5-V UVLO version

UCC21520DW – 8-V UVLO version

6.5

25

V

VDDA,

VDDB

Driver output bias supply

9.2

T_A

T_J

Ambient Temperature

Junction Temperature

–40

125

130

°C

4

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7.4 Thermal Information

UCC21520,

THERMAL METRIC⁽¹⁾

UNIT

UCC21520A

DW-16 (SOIC)

67.3

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

34.4

32.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

18.0

ψ_JB

31.6

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics Application

Report.

7.5 Power Ratings

VALUE

1.05

UNIT

P_D

Power dissipation by UCC21520 or UCC21520A

W

P_DI

Power dissipation by transmitter side of

UCC21520 or UCC21520A

VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3

V, 3 MHz 50% duty cycle square wave 1-nF

load

0.05

P_DA, P_DB

Power dissipation by each driver side of

UCC21520 or UCC21520A

0.5

W

7.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

> 8

UNIT

mm

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance through air

Shortest pin-to-pin distance across the package surface

> 8

mm

Minimum internal gap (internal clearance) of the double

insulation (2 × 10.5 µm)

DTI

CTI

Distance through insulation

>21

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

> 600

I

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category per

IEC 60664-1

DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage (bipolar)

2121

V_PK

AC voltage (sine wave); time dependent dielectric breakdown

(TDDB), test (see Figure 7-1)

1500

2121

8000

V_RMS

V_DC

V_PK

Maximum working isolation

voltage

V_IOWM

DC voltage

Maximum transient isolation V_TEST= V_IOTM, t = 60 sec (qualification)

V_IOTM

V_IOSM

voltage

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

Maximum surge isolation

voltage⁽³⁾

Test method per IEC 62368-1, 1.2/50 µs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

8000

<5

V_PK

Method a, After Input/Output safety test subgroup 2/3.

V_ini= V_IOTM, t_ini= 60s;

V_pd(m)= 1.2 X V_IORM= 2545 V_PK, t_m= 10s

Method a, After environmental tests subgroup 1.

V_ini= V_IOTM, t_ini= 60s;

V_pd(m)= 1.6 X V_IORM= 3394 V_PK, t_m= 10s

<5

q_pd

Apparent charge⁽⁴⁾

pC

Method b1; At routine test (100% production) and

preconditioning (type test)

V_ini= 1.2 × V_IOTM; t_ini= 1s;

V_pd(m)= 1.875 * V_IORM= 3977 V_PK, t_m= 1s

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7.6 Insulation Specifications (continued)

PARAMETER

TEST CONDITIONS

VALUE

UNIT

Barrier capacitance, input to

C_IO

V_IO= 0.4 sin (2πft), f =1 MHz

V_IO= 500 V at T_A= 25°C

1.2

pF

output⁽⁵⁾

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output⁽⁵⁾

R_IO

V_IO= 500 V at 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S=150°C

Ω

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 sec. (qualification),

V_TEST= 1.2 × V_ISO= 6840V_RMS, t = 1 sec (100% production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of

the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become

equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

7.7 Safety-Related Certifications

VDE

CSA

UL

CQC

Certified according to DIN V VDE V

0884-11:2017-01,

and DIN EN 60950-1 (VDE 0805 Teil 62368-1, IEC 61010-1 and IEC 60601-1

1):2014-08

Recognized under

UL 1577 Component

Recognition Program

Certified according to IEC 60950-1, IEC

Certified according to GB

4943.1-2011

Reinforced insulation per CSA

60950-1-07+A1+A2 and IEC 60950-1 2nd

Ed.+A1+A2, 800 V_RMSmaximum working

voltage (pollution degree 2, material group I)

Reinforced Insulation Maximum

Transient Isolation voltage, 8000

Reinforced insulation per CSA 62368-1-14

and IEC 62368-1 2nd Ed., 800 V_RMS

maximum working voltage (pollution degree

Reinforced Insulation,

Single protection, 5700 Altitude ≤ 5000 m,

V_PK

;

Maximum Repetitive Peak Isolation 2, material group I);

V_RMS

Tropical Climate 660 V_RMS

maximum working voltage

Voltage, 2121 V_PK

;

Basic insulation per CSA 61010-1-12+A1

and IEC 61010-1 3rd Ed., 600 V_RMS

maximum working voltage (pollution degree

2, material group III);

Maximum Surge Isolation Voltage,

8000 V_PK

2 MOPP (Means of Patient Protection) per

CSA 60601- 1:14 and IEC 60601-1 Ed.3+A1,

250 V_RMSmaximum working voltage

Certificate number:

CQC16001155011

Certification number: 40040142

Master contract number : 220991

File number: E181974

7.8 Safety-Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

SIDE

MIN

TYP

MAX

UNIT

R_θJA= 67.3°C/W, VDDA/B = 12 V, T_A=

25°C, T_J= 150°C

See Figure 7-2.

DRIVER A,

DRIVER B

75

mA

Safety output supply

current

I_S

R_θJA= 67.3°C/W, VDDA/B = 25 V, T_A=

25°C, T_J= 150°C

See Figure 7-2.

DRIVER A,

DRIVER B

36

mA

6

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7.8 Safety-Limiting Values (continued)

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

SIDE

MIN

TYP

MAX

UNIT

mW

°C

INPUT

50

DRIVER A

DRIVER B

TOTAL

900

1850

150

R_θJA= 67.3°C/W, T_A= 25°C, T_J= 150°C

See Figure 7-3.

P_S

T_S

Safety supply power

Safety temperature⁽¹⁾

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The

I_Sand P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Section 7.4 table is that of a device installed on a high-K test board for leaded

surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

7.9 Electrical Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENTS

I_VCCI

VCCI quiescent current

V_INA= 0 V, V_INB= 0 V

1.5

1.0

2.0

1.8

mA

I_VDDA

I_VDDB

,

VDDA and VDDB quiescent current V_INA= 0 V, V_INB= 0 V

(f = 500 kHz) current per channel,

C_OUT= 100 pF

I_VCCI

VCCI operating current

2.0

2.5

mA

I_VDDA

I_VDDB

(f = 500 kHz) current per channel,

C_OUT= 100 pF

VDDA and VDDB operating current

VCCI UVLO THRESHOLDS

V_{VCCI_ON}

V_{VCCI_OFF}

V_{VCCI_HYS}

Rising threshold

2.55

2.35

2.7

2.5

0.2

2.85

2.65

V

Falling threshold VCCI_OFF

Threshold hysteresis

UCC21520ADW VDD UVLO THRESHOLDS (5-V UVLO Version)

V_{VDDA_ON}

V_{VDDB_ON}

,

Rising threshold VDDA_ON,

VDDB_ON

5.7

5.4

6.0

5.7

0.3

6.3

6

V

V_{VDDA_OFF}

V_{VDDB_OFF}

,

Falling threshold VDDA_OFF,

VDDB_OFF

V_{VDDA_HYS}

V_{VDDB_HYS}

,

Threshold hysteresis

UCC21520DW VDD UVLO THRESHOLDS (8-V UVLO Version)

V_{VDDA_ON,}

V_{VDDB_ON}

Rising threshold VDDA_ON,

VDDB_ON

8.3

7.8

8.7

8.2

0.5

9.2

8.7

V

V_{VDDA_OFF,}

V_{VDDB_OFF}

Falling threshold VDDA_OFF,

VDDB_OFF

V_{VDDA_HYS,}

V_{VDDB_HYS}

Threshold hysteresis

INA, INB AND DISABLE

V_INAH, V_INBH

V_DISH

,

Input high voltage

1.6

1.8

2

V

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7.9 Electrical Characteristics (continued)

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_INAL, V_INBL

V_DISL

,

Input low voltage

0.8

1

1.2

V

V_{INA_HYS}

V_{INB_HYS}

V_{DIS_HYS}

,

Input hysteresis

0.8

V

Negative transient, ref to GND, 50 ns Not production tested, bench test

pulse

V_INA, V_INB

OUTPUT

I_OA+, I_OB+

–5

only

C_VDD= 10 µF, C_LOAD= 0.18 µF, f =

1 kHz, bench measurement

Peak output source current

Peak output sink current

4

6

A

C_VDD= 10 µF, C_LOAD= 0.18 µF, f =

1 kHz, bench measurement

I_OA-, I_OB-

I_OUT= –10 mA, T_A= 25°C, R_OHA

,

R_OHBdo not represent drive pull-up

performance. See t_RISEin Section

7.10 and Section 9.3.4 for details.

R_OHA, R_OHB

Output resistance at high state

5

Ω

R_OLA, R_OLB

V_OHA, V_OHB

Output resistance at low state

Output voltage at high state

I_OUT= 10 mA, T_A= 25°C

0.55

Ω

V

V_VDDA, V_VDDB= 12 V, I_OUT= –10

mA, T_A= 25°C

11.95

V_VDDA, V_VDDB= 12 V, I_OUT= 10

mA, T_A= 25°C

V_OLA, V_OLB

Output voltage at low state

5.5

mV

DEADTIME AND OVERLAP PROGRAMMING

Pull DT pin to VCCI

Overlap determined by INA INB

-

DT pin is left open, min spec

characterized only, tested for

outliers

Dead time

0

8

15

ns

R_DT= 20 kΩ

160

200

240

7.10 Switching Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_RISE

Output rise time, 20% to 80%

measured points

6

16

ns

C_OUT= 1.8 nF

t_FALL

Output fall time, 90% to 10%

measured points

7

12

20

30

ns

C_OUT= 1.8 nF

t_PWmin

t_PDHL

t_PDLH

Minimum pulse width

Output off for less than minimum,

C_OUT= 0 pF

Propagation delay from INx to OUTx

falling edges

14

19

Propagation delay from INx to OUTx

rising edges

t_PWD

t_DM

Pulse width distortion |t_PDLH– t_PDHL

|

6

5

ns

Propagation delays matching

between VOUTA, VOUTB

f = 100 kHz

t_{VDD+ to OUT}VDDA, VDDB Power-up Delay Time:

UVLO Rise to OUTA, OUTB. See

Figure 8-6

50

100

us

INA or INB tied to VCCI

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V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level common-mode transient

immunity

INA and INB both are tied to VCCI;

V_CM=1500V; (See Section 8.6)

|CM_H|

|CM_L|

100

V/ns

Low-level common-mode transient

immunity

INA and INB both are tied to GND;

V_CM=1500V; (See Section 8.6)

100

7.11 Insulation Characteristics Curves

1.E+11

1.E+10

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

87.5%

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

1.E+2

1.E+1

20%

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

Figure 7-1. Reinforced Isolation Capacitor Life Time Projection

100

80

60

40

20

0

2000

I_VDDA/Bfor VDD=12V

I_VDDA/Bfor VDD=25V

1600

1200

800

400

0

50

100

Ambient Temperature (°C)

150

200

0

50

100

Ambient Temperature (°C)

150

200

D001

Figure 7-3. Thermal Derating Curve for Safety-

Related Limiting Power

Figure 7-2. Thermal Derating Curve for Safety-

Related Limiting Current (Current in Each Channel

with Both Channels Running Simultaneously)

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7.12 Typical Characteristics

VDDA = VDDB= 12 V, VCCI = 3.3 V, T_A= 25°C, No load unless otherwise noted.

20

16

12

8

50

40

30

20

10

0

4

VDD=12v

VDD=25v

VDD= 12V

VDD= 25V

0

800

1600

2400 3200

Frequency (kHz)

4000

4800

5600

0

500

1000

1500

Frequency (kHz)

2000

2500

3000

D001

Figure 7-4. Per Channel Current Consumption vs

Frequency (No Load, VDD = 12 V or 25 V)

Figure 7-5. Per Channel Current Consumption

(I_VDDA/B) vs Frequency (1-nF Load, VDD = 12 V or

25 V)

30

24

18

12

6

50kHz

250kHz

500kHz

1MHz

5

4

3

2

1

0

VDD= 12V

VDD= 25V

0

10

25

40

55

Frequency (kHz)

70

85 100

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (èC)

D001

Figure 7-6. Per Channel Current Consumption

(I_VDDA/B) vs Frequency (10-nF Load, VDD = 12 V or

25 V)

Figure 7-7. Per Channel (I_VDDA/B) Supply Current

Vs. Temperature (No Load, Different Switching

Frequencies)

2

1.6

1.2

0.8

0.4

2

1.8

1.6

1.4

1.2

VDD= 12V

VDD= 25V

VCCI= 3.3V

VCCI= 5V

0

-40

1

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 7-8. Per Channel (I_VDDA/B) Quiescent Supply

Current vs Temperature (No Load, Input Low, No

Switching)

Figure 7-9. I_VCCIQuiescent Supply Current vs

Temperature (No Load, Input Low, No Switching)

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25

10

8

20

15

10

5

6

Output Pull-Up

Output Pull-Down

4

2

t_RISE

t_FALL

0

-40

2

4

6

8

10

-20

0

20

40

60

80

100 120 140

Load (nF)

Temperature (èC)

D001

Figure 7-10. Rising and Falling Times vs Load

(VDD = 12 V)

Figure 7-11. Output Resistance vs Temperature

28

24

20

16

12

20

19

18

17

16

Rising Edge (t_PDLH

Falling Edge (t_PDHL

)

Rising Edge (t_PDLH)

Falling Edge (t_PDHL

)

8

15

-40

-20

0

20

40

60

80

100 120 140

3

6

9

12

15 18

Temperature (èC)

VCCI (V)

D001

Figure 7-12. Propagation Delay vs Temperature

Figure 7-13. Propagation Delay vs VCCI

5

3

1

2.5

0

-2.5

-5

-1

-3

-5

Rising Edge

Falling Edge

10

13

16

19

22

25

-40

-20

0

20

40

60

80

100 120 140

VDDA/B (V)

Temperature (èC)

D001

Figure 7-15. Propagation Delay Matching (t_DM) vs

VDD

Figure 7-14. Pulse Width Distortion vs Temperature

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5

2.5

0

350

330

310

290

270

250

-2.5

Rising Edge

Falling Edge

-5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 7-16. Propagation Delay Matching (t_DM) vs

Temperature

Figure 7-17. VDD 5-V UVLO Hysteresis vs

Temperature

6.5

550

530

510

490

470

450

6

5.5

V_{VDD_ON}

V_{VDD_OFF}

5

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 7-19. VDD 8-V UVLO Hysteresis vs

Temperature

Figure 7-18. VDD 5-V UVLO Threshold vs

Temperature

10

900

860

820

780

9

8

7

740

6

VCC=3.3V

VCC=5V

VCC=12V

V_{VDDA_ON}

V_{VDDA_OFF}

700

-40

5

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 7-21. IN/DIS Hysteresis vs Temperature

Figure 7-20. VDD 8-V UVLO Threshold vs

Temperature

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1.2

2

1.92

1.84

1.76

1.68

1.6

1.14

1.08

1.02

0.96

0.9

VCC=3.3V

VCC= 5V

VCC=12V

VCC=3.3V

VCC= 5V

VCC=12V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 7-22. IN/DIS Low Threshold

Figure 7-23. IN/DIS High Threshold

1500

1200

900

600

300

0

5

-6

R_DT= 20kW

R_DT= 100kW

-17

-28

-39

-50

R_DT= 20kW

R_DT= 100kW

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Temperature (èC)

D001

Figure 7-24. Dead Time vs Temperature (with R_DT

20 kΩ and 100 kΩ)

=

Figure 7-25. Dead Time Matching vs Temperature

(with R_DT= 20 kΩ and 100 kΩ)

18

14

10

6

2

-2

-6

1 nF Load

10 nF Load

0

100

200

300

400

Time (ns)

500

600

700

800

D001

Figure 7-26. Typical Output Waveforms

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8 Parameter Measurement Information

8.1 Propagation Delay and Pulse Width Distortion

Figure 8-1 shows how one calculates pulse width distortion (t_PWD) and delay matching (t_DM) from the

propagation delays of channels A and B. It can be measured by ensuring that both inputs are in phase and

disabling the dead time function by shorting the DT Pin to VCC.

INA/B

tPDHLA

tPDLHA

tDM

OUTA

tPDLHB

tPDHLB

tPWDB = |tPDLHB t tPDHLB|

OUTB

Figure 8-1. Overlapping Inputs, Dead Time Disabled

8.2 Rising and Falling Time

Figure 8-2 shows the criteria for measuring rising (t_RISE) and falling (t_FALL) times. For more information on how

short rising and falling times are achieved see Section 9.3.4.

90%

80%

t_RISE

t_FALL

20%

10%

Figure 8-2. Rising and Falling Time Criteria

8.3 Input and Disable Response Time

Figure 8-3 shows the response time of the disable function. It is recommended to bypass using a ≈1nF low

ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance. For more

information, see Section 9.4.1.

INA

DIS High

Response Time

DIS

DIS Low

Response Time

OUTA

t_PDLH

90%

t_PDHL

10%

Figure 8-3. Disable Pin Timing

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8.4 Programable Dead Time

Leaving the DT pin open or tying it to GND through an appropriate resistor (R_DT) sets a dead-time interval. For

more details on dead time, refer to Section 9.4.2.

INA

INB

90%

OUTA

10%

tPDHL

tPDLH

90%

OUTB

10%

tPDHL

Dead Time

(Set by RDT

Dead Time

(Determined by Input signals if

)

longer than DT set by RDT

)

Figure 8-4. Dead-Time Switching Parameters

8.5 Power-up UVLO Delay to OUTPUT

Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising

edge to output and it is defined as t_{VCCI+ to OUT}for VCCI UVLO (typically 40us) and t_{VDD+ to OUT}for VDD UVLO

(typically 50us). It is recommended to consider proper margin before launching PWM signal after the driver's

VCCI and VDD bias supply is ready. Figure 8-5 and Figure 8-6 show the power-up UVLO delay timing diagram

for VCCI and VDD.

If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will

not update until t_{VCCI+ to OUT}or t_{VDD+ to OUT}after VCCI or VDD crossing its UVLO rising threshold. However, when

either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1µs delay, depending on

the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to

ensure safe operation during VCCI or VDD brownouts.

VCCI,

INx

VCCI,

INx

V_{VCCI_ON}

V_{VCCI_OFF}

VDDx

OUTx

t_{VCCI+ to OUT}

t_{VDD+ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

OUTx

Figure 8-5. VCCI Power-up UVLO Delay

Figure 8-6. VDDA/B Power-up UVLO Delay

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8.6 CMTI Testing

Figure 8-7 is a simplified diagram of the CMTI testing configuration.

VCC

VDD

VDDA

OUTA

VSSA

INA

1

16

15

14

OUTA

INB

2

VCC

VCCI

3

GND

Functional

Isolation

4

5

6

8

DIS

DT

VDDB

11

10

9

OUTB

VSSB

VCCI

GND

VSS

Common Mode Surge

Generator

Figure 8-7. Simplified CMTI Testing Setup

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9 Detailed Description

9.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are

often placed between the output of control devices and the gates of power transistors. There are several

instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.

This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V

logic signal capable of only delivering a few mA.

The UCC21520, UCC21520A are flexible dual gate drivers which can be configured to fit a variety of power

supply and motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. The

UCC21520, UCC21520A have many features that allow it to integrate well with control circuitry and protect the

gates it drives such as: resistor-programmable dead time (DT) control, a DISABLE pin, and under voltage lock

out (UVLO) for both input and output voltages. The UCC21520 and the UCC21520A also hold its outputs low

when the inputs are left open or when the input pulse is not wide enough. The driver inputs are CMOS and

TTL compatible for interfacing to digital and analog power controllers alike. Each channel is controlled by its

respective input pins (INA and INB), allowing full and independent control of each of the outputs.

9.2 Functional Block Diagram

INA

1

16 VDDA

200 kW

Driver

MOD

DEMOD

VCCI

15 OUTA

14 VSSA

UVLO

VCCI 3,8

UVLO

GND

DT

4

6

5

13 NC

12 NC

Deadtime

Control

Functional Isolation

DIS

11 VDDB

200 kW

Driver

MOD

DEMOD

UVLO

10 OUTB

INB

NC

2

7

9

VSSB

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9.3 Feature Description

9.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)

The UCC21520 and the UCC21520A have an internal undervoltage lock out (UVLO) protection feature on the

supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower

than V_{VDD_ON}at device start-up or lower than V_{VDD_OFF}after start-up, the VDD UVLO feature holds the effected

output low, regardless of the status of the input pins (INA and INB).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low

by an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 9-1 ). In this

condition, the upper PMOS is resistively held off by R_Hi-Zwhile the lower NMOS gate is tied to the driver output

through R_CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower

NMOS device, typically around 1.5 V, when no bias power is available.

VDD

R_{HI_Z}

Output

Control

OUT

R_CLAMP

R_CLAMPis activated

during UVLO

VSS

Figure 9-1. Simplified Representation of Active Pulldown Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is

ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is

bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC21520 and the UCC21520A also has an internal undervoltage lock out (UVLO)

protection feature. The device isn't active unless the voltage, VCCI, is going to exceed V_{VCCI_ON}on start up. And

a signal will cease to be delivered when that pin receives a voltage less than V_{VCCI_OFF}. And, just like the UVLO

for VDD, there is hysteresis (V_{VCCI_HYS}) to ensure stable operation.

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All versions of the UCC21520 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

Table 9-1. UCC21520 and UCC21520A VCCI UVLO Feature Logic

CONDITION

INPUTS

OUTPUTS

INA

INB

OUTA

OUTB

VCCI-GND < V_{VCCI_ON}during device start up

H

L

H

L

VCCI-GND < V_{VCCI_ON}during device start up

VCCI-GND < V_{VCCI_OFF}after device start up

H

L

H

L

H

L

H

L

Table 9-2. UCC21520 and UCC21520A VDD UVLO Feature Logic

CONDITION

INPUTS

OUTPUTS

INA

INB

OUTA

OUTB

VDD-VSS < V_{VDD_ON}during device start up

H

L

H

L

VDD-VSS < V_{VDD_ON}during device start up

VDD-VSS < V_{VDD_OFF}after device start up

H

L

H

L

H

L

H

L

9.3.2 Input and Output Logic Table

Table 9-3. INPUT/OUTPUT Logic Table⁽¹⁾

Assume VCCI, VDDA, VDDB are powered up. See Section 9.3.1 for more information on UVLO operation modes.

INPUTS

OUTPUTS

DISABLE

NOTE

INA

L

INB

L

OUTA

OUTB

L or Left Open

L

H

L

If Dead Time function is used, output transitions occur after the

dead time expires. See Section 9.4.2

L

H

L

H

L

H

L

DT is left open or programmed with R_DT

H

L

H

L

DT pin pulled to VCCI

Left Open Left Open L or Left Open

-

X

H

L

(1) "X" means L, H or left open.

9.3.3 Input Stage

The input pins (INA, INB, and DIS) of the UCC21520 and the UCC21520A are based on a TTL and CMOS

compatible input-threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy

to drive with logic-level control signals (Such as those from 3.3-V micro-controllers), since the UCC21520 and

the UCC21520A have a typical high threshold (V_INAH) of 1.8 V and a typical low threshold of 1 V, which vary

little with temperature (see Figure 7-22,Figure 7-23). A wide hysterisis (V_{INA_HYS}) of 0.8 V makes for good noise

immunity and stable operation. If any of the inputs are ever left open, internal pull-down resistors force the pin

low. These resistors are typically 200 kΩ (See Section 9.2). However, it is still recommended to ground an input

if it is not being used.

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Since the input side of the UCC21520 and the UCC21520A is isolated from the output drivers, the input signal

amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows

greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient

VDD for their chosen gate. That said, the amplitude of any signal applied to INA or INB must never be at a

voltage higher than VCCI.

9.3.4 Output Stage

The UCC21520 and the UCC21520A output stages feature a pull-up structure which delivers the highest peak-

source current when it is most needed, during the Miller plateau region of the power-switch turn on transition

(when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features

a P-channel MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel

MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by

briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to

high. The on-resistance of this N-channel MOSFET (R_NMOS) is approximately 1.47 Ω when activated.

The R_OHparameter is a DC measurement and it is representative of the on-resistance of the P-channel device

only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on

only for a brief instant when the output is changing states from low to high. Therefore the effective resistance

of the UCC21520 and the UCC21520A pull-up stage during this brief turn-on phase is much lower than what is

represented by the R_OHparameter. Therefore, the value of R_OHbelies the fast nature of the UCC21520 and the

UCC21520A's turn-on time.

The pull-down structure in the UCC21520 and the UCC21520A is simply composed of an N-channel MOSFET.

The R_OLparameter, which is also a DC measurement, is representative of the impedance of the pull-down

state in the device. Both outputs of the UCC21520 and the UCC21520A are capable of delivering 4-A peak

source and 6-A peak sink current pulses. The output voltage swings between VDD and VSS provides rail-to-rail

operation, thanks to the MOS-out stage which delivers very low drop-out.

VDD

R_OH

Shoot-

R_NMOS

Input

Signal

Through

Prevention

Circuitry

OUT

VSS

R_OL

Pull Up

Figure 9-2. Output Stage

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9.3.5 Diode Structure in the UCC21520 and the UCC21520A

Figure 9-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21520 and the

UCC21520A. This provides a pictorial representation of the absolute maximum rating for the device.

VCCI

3,8

VDDA

16

30 V

15 OUTA

14 VSSA

20 V 20 V

INA

INB

DIS

DT

1

2

5

6

11 VDDB

10 OUTB

30 V

4

9

GND

VSSB

Figure 9-3. ESD Structure

9.4 Device Functional Modes

9.4.1 Disable Pin

Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE

pin allows the UCC21520 and the UCC21520A to operate normally. The DISABLE response time is in the range

of 20 ns and quite responsive, which is as fast as propagation delay. The DISABLE pin is only functional (and

necessary) when VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the

DISABLE pin is not used to achieve better noise immunity, and it is recommended to bypass using a ≈1-nF low

ESR/ESL capacitor close to DIS pin when connecting DIS pin to a micro controller with distance.

9.4.2 Programmable Dead-Time (DT) Pin

The UCC21520 and the UCC21520A allow the user to adjust dead time (DT) in the following ways:

9.4.2.1 Tying the DT Pin to VCC

Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.

9.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins

One can program t_DTby placing a resistor, R_DT, between the DT pin and GND. The appropriate R_DTvalue can

be determined from Equation 1, where R_DTis in kΩ and t_DTis in ns:

9.4.2.3

t_DT» 10 ´ R_DT

(1)

The steady state voltage at DT pin is around 0.8 V, and the DT pin current will be less than 10uA when

R_DT=100kΩ. When using R_DT> 5kΩ, it is recommended to parallel a ceramic capacitor, 2.2nF or above, close to

the chip with R_DTto achieve better noise immunity and better dead time matching between two channels. It is

not recommended to leave the DT pin floating.

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An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’ dead

time is always set to the longer of either the driver’s programmed dead time or the input signal’s own dead time.

If both inputs are high simultaneously, both outputs will immediately be set low. This feature is used to prevent

shoot-through, and it doesn’t affect the programmed dead time setting for normal operation. Various driver dead

time logic operating conditions are illustrated and explained in Figure 9-4:

INA

INB

DT

OUTA

OUTB

A

B

C

D

E

F

Figure 9-4. Input and Output Logic Relationship With Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead

time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed

dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead

time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,

when INA goes high, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead

time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it

immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls

OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to

OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls

OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to

OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

The UCC21520 or the UCC21520A effectively combines both isolation and buffer-drive functions. The flexible,

universal capability of the UCC21520 and the UCC21520A (with up to 18-V VCCI and 25-V VDDA/VDDB) allows

the device to be used as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or

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SiC MOSFETs. With integrated components, advanced protection features (UVLO, dead time, and disable) and

optimized switching performance; the UCC21520 and the UCC21520A enable designers to build smaller, more

robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market.

10.2 Typical Application

The circuit in Figure 10-1 shows a reference design with the UCC21520 driving a typical half-bridge configuration

which could be used in several popular power converter topologies such as synchronous buck, synchronous

boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.

VDD

VCC

R_BOOT

HV DC-Link

VCC

VDDA

INA

INB

R_OFF

R_ON

16

15

14

PWM-A

1

2

3

4

5

6

8

R_IN

OUTA

VSSA

C_IN

PWM-B

R_GS

C_BOOT

C_IN

VCCI

GND

DIS

mC

C_VCC

SW

Functional

Isolation

VDD

Analog

or

Digital

Disable

VDDB

R_OFF

R_ON

11

10

9

C_DT

≥2.2nF

R_DIS

C_DIS

DT

OUTB

VSSB

R_GS

C_VDD

VCCI

R_DT

VSS

Figure 10-1. Typical Application Schematic

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10.2.1 Design Requirements

Table 10-1 lists reference design parameters for the example application: UCC21520 driving 1200-V SiC-

MOSFETs in a high side-low side configuration.

Table 10-1. UCC21520 Design Requirements

PARAMETER

VALUE

UNITS

Power transistor

VCC

C2M0080120D

-

V

5.0

20

VDD

V

Input signal amplitude

Switching frequency (f_s)

DC link voltage

3.3

100

800

V

kHz

V

10.2.2 Detailed Design Procedure

10.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)

the signal at the output. However, a small input R_IN-C_INfilter can be used to filter out the ringing introduced by

non-ideal layout or long PCB traces.

Such a filter should use an R_INin the range of 0 Ω to100 Ω and a C_INbetween 10 pF and 100 pF. In the

example, an R_IN= 51 Ω and a C_IN= 33 pF are selected, with a corner frequency of approximately 100 MHz.

When selecting these components, it is important to pay attention to the trade-off between good noise immunity

and propagation delay.

10.2.2.2 Select External Bootstrap Diode and its Series Resistor

The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side

transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation

in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.

Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver

circuit.

When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes

or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the

loss introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage

is 800 V_DC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good

margin. Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example.

When designing a bootstrap supply, it is recommended to use a bootstrap resistor, R_BOOT. A bootstrap resistor,

is also used to reduce the inrush current in D_BOOTand limit the ramp up slew rate of voltage of VDDA-VSSA

during each switching cycle.

Failure to limit the voltage to VDDx-VSSx to less than the Absolute Maximum Ratings of the FET and UCC21520

may result in permanent damage to the device in certain cases.

The recommended value for R_BOOTis between 1 Ω and 20 Ω depending on the diode used. In the example, a

current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode. The estimated worst

case peak current through D_Bootis,

V_DD- V_BDF

R_Boot

20V - 2.5V

2.2W

I_{DBoot pk}

=

ö 8A

(

)

(2)

where

•

V_BDFis the estimated bootstrap diode forward voltage drop at 8 A.

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10.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, R_ON/R_OFF, are used to:

1. Limit ringing caused by parasitic inductances/capacitances.

2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.

3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.

4. Reduce electromagnetic interference (EMI).

As mentioned in Section 9.3.4, the UCC21520 has a pull-up structure with a P-channel MOSFET and an

additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak

source current can be predicted with:

≈

∆

«

’

V_DD- V_BDF

R_NMOS||R_OH+R_ON+R_{GFET _Int}

I_OA+= min 4A,

∆

÷

◊

(3)

(4)

≈

∆

«

’

V_DD

I_OB+= min 4A,

∆

÷

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}

◊

where

•

R_ON: External turn-on resistance.

R_{GFET_INT}: Power transistor internal gate resistance, found in the power transistor datasheet.

I_O+= Peak source current – The minimum value between 4 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

In this example:

V_DD- V_BDF

20V - 0.8V

I_OA+

=

ö 2.4A

ö 2.5A

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

(5)

(6)

V_DD

20V

I_OB+

=

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak

sink current can be calculated with:

≈

∆

«

’

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET_Int}

I_OA-= min 6A,

∆

÷

◊

(7)

(8)

≈

∆

«

’

V_DD- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

I_OB-= min 6A,

∆

÷

◊

where

•

R_OFF: External turn-off resistance;

V_GDF: The anti-parallel diode forward voltage drop which is in series with R_OFF. The diode in this example is

an MSS1P4.

•

I_O-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated

value based on the gate drive loop resistance.

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In this example,

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

20V - 0.8V - 0.75V

0.55W + 0W + 4.6W

I_OA-

=

ö 3.6A

(9)

V_DD- V_GDF

20V-0.75V

I_OB-=

=

ö 3.7A

R_OL+ R_OFF||R_ON+ R_{GFET _Int}0.55W + 0W + 4.6W

(10)

Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other

hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C_ISS) of the

power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close

to the parasitic ringing period.

Failure to control OUTx voltage to less than the Absolute Maximum Ratings in the datasheet (including

transients) may result in permanent damage to the device in certain cases. To reduce excessive gate ringing,

it is recommended to use a ferrite bead near the gate of the FET. External clamping diodes can also be added

in the case of extended overshoot/undershoot, in order to clamp the OUTx voltage to the VDDx and VSSx

voltages.

10.2.2.4 Gate to Source Resistor Selection

A gate to source resistor, R_GS, is recommended to pull down the gate to the source voltage when the gate driver

output is unpowered and in an indeterminate state. This resistor also helps to mitigate the risk of dv/dt induced

turn-on due to Miller current before the gate driver is able to turn on and actively pull low. This resistor is typically

sized between 5.1kΩ and 20kΩ, depending on the Vth and ratio of C_GDto C_GSof the power device.

10.2.2.5 Estimate Gate Driver Power Loss

The total loss, P_G, in the gate driver subsystem includes the power losses of the UCC21520 (P_GD) and the

power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not

included in P_Gand not discussed in this section.

P_GDis the key power loss which determines the thermal safety-related limits of the UCC21520, and it can be

estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well

as driver self-power consumption when operating with a certain switching frequency. P_GDQis measured on the

bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and

ambient temperature. Figure 7-4 shows the per output channel current consumption vs operating frequency

with no load. In this example, V_VCCI= 5 V and V_VDD= 20 V. The current on each power supply, with INA/INB

switching from 0 V to 3.3 V at 100 kHz is measured to be I_VCCI= 2.5 mA, and I_VDDA= I_VDDB= 1.5 mA. Therefore,

the P_GDQcan be calculated with

P

= V_VCCIìI_VCCI+ V_VDDAìI_DDA+ V_VDDBìI_DDBö 72mW

GDQ

(11)

The second component is switching operation loss, P_GDO, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_GSW

can be estimated with

,

P_GSW= 2 ì V_DDì Q_Gì f_SW

(12)

where

•

Q_Gis the gate charge of the power transistor.

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If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail

to the negative rail.

So, for this example application:

P_GSW= 2 ì 20V ì 60nC ì100kHz = 240mW

(13)

Q_Grepresents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change

with different testing conditions. The UCC21520 gate driver loss on the output stage, P_GDO, is part of P_GSW

.

P_GDOwill be equal to P_GSWif the external gate driver resistances are zero, and all the gate driver loss is

dissipated inside the UCC21520. If there are external turn-on and turn-off resistances, the total loss will be

distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the

pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A,

however, it will be non-linear if the source/sink current is saturated. Therefore, P_GDOis different in these two

scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

≈

’

P_GSW

2

R_OH||R_NMOS

R_OL

P_GDO

=

ì

+

∆

«

÷

◊

R_OH||R_NMOS+R_ON+R_{GFET _Int}R_OL+R_OFF||R_ON+ R_{GFET _Int}

(14)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21520

gate driver loss can be estimated with:

≈

∆

«

’

÷

◊

240mW

2

5W ||1.47W

0.55W

P_GDO

=

ì

+

ö 30mW

5W ||1.47W + 2.2W + 4.6W 0.55W + 0W + 4.6W

(15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

T_{R _ Sys}

T_{F_ Sys}

»

ÿ

Ÿ

P_GDO= 2 ì f_SWì 4A ì

V - V

t dt + 6A ì

( )

V_OUTA/Bt dt

( )

…

(

)

DD

OUTA/B

—

…

Ÿ

⁄

0

(16)

where

•

V_OUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be

simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load

capacitor. Then, the V_OUTA/B(t) waveform will be linear and the T_{R_Sys}and T_{F_Sys}can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the

P_GDOwill be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up

and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver

UCC21520, P_GD, is:

P_GD= P + P

GDQ

GDO

(17)

which is equal to 102 mW in the design example.

10.2.2.6 Estimating Junction Temperature

The junction temperature (T_J) of the UCC21520 can be estimated with:

T_J= T_C+ Y_JT´ P_GD

(18)

where

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•

T_Cis the UCC21520 case-top temperature measured with a thermocouple or some other instrument, and

Ψ_JTis the Junction-to-top characterization parameter from the Section 7.4 table.

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_ΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

R_ΘJCcan only be used effectively when most of the thermal energy is released through the case, such as with

metal packages or when a heatsink is applied to an IC package. In all other cases, use of R_ΘJCwill inaccurately

estimate the true junction temperature. Ψ_JTis experimentally derived by assuming that the amount of energy

leaving through the top of the IC will be similar in both the testing environment and the application environment.

As long as the recommended layout guidelines are observed, junction temperature estimates can be made

accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package

Thermal Metrics Application Report.

10.2.2.7 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is

recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC)

with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an

MLCC will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only

500 nF when a DC bias of 15 V_DCis applied.

10.2.2.7.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total

current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for

this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or

electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

10.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for

gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

I_VDD@100kHz No Load

(

f_SW

)

1.5mA

Q_Total= Q_G+

= 60nC +

= 75nC

100kHz

(19)

where

•

Q_Total: Total charge needed

Q_G: Gate charge of the power transistor.

I_VDD: The channel self-current consumption with no load at 100kHz.

f_SW: The switching frequency of the gate driver

Therefore, the absolute minimum C_Bootrequirement is:

Q_Total

75nC

C_Boot

=

= 150nF

DV_VDDA0.5V

(20)

where

ΔV_VDDAis the voltage ripple at VDDA, which is 0.5 V in this example.

•

In practice, the value of C_Bootis greater than the calculated value. This allows for the capacitance shift caused by

the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.

Therefore, it is recommended to include a safety-related margin in the C_Bootvalue and place it as close to the

VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

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C_Boot= 1ꢀF

(21)

Care should be taken when selecting the bootstrap capacitor to ensure that the VDD to VSS voltage does not

drop below the recommended minimum operating level listed in section 6.3. The value of the bootstrap capacitor

should be sized such that it can supply the initial charge to switch the power device, and then continuously

supply the gate driver quiescent current for the duration of the high-side on-time.

If the high-side supply voltage drops below the UVLO falling threshold, the high-side gate driver output will turn

off and switch the power device off. Uncontrolled hard-switching of power devices can cause high di/dt and high

dv/dt transients on the output of the driver and may result in permanent damage to the device.

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor

placed very close to VDDx - VSSx pins with a low ESL/ESR. In this example a 100 nF, X7R ceramic capacitor, is

placed in parallel with C_Bootto optimize the transient performance.

Note

Too large C_BOOTis not good. C_BOOTmay not be charged within the first few cycles and V_BOOTcould

stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during

initial C_BOOTcharging cycles, the bootstrap diode has highest reverse recovery current and losses.

10.2.2.7.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as C_VDD

in Figure 10-1) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply

current for VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for

C_VDD. If the bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic

capacitor, with a value over 10 µF, should be used in parallel with CVDD.

10.2.2.8 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor

is important for preventing shoot-through during dynamic switching.

The UCC21520 dead time specification in the electrical table is defined as the time interval from 90% of one

channel’s falling edge to 10% of the other channel’s rising edge (see Figure 8-4). This definition ensures that

the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.

However, this dead time setting may not reflect the dead time in the power converter system, since the dead

time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as

well as the input capacitance of the load transistor.

Here is a suggestion on how to select an appropriate dead time for UCC21520:

DT_Setting= DT_Req+ T_{F_Sys}+ T_{R _Sys}- T_{D on}

(

)

(22)

where

•

DT_setting: UCC21520 dead time setting in ns, DT_Setting= 10 × RDT(in kΩ).

DT_Req: System required dead time between the real V_GSsignal of the top and bottom switch with enough

margin, or ZVS requirement.

•

T_{F_Sys}: In-system gate turn-off falling time at worst case of load, voltage/current conditions.

T_{R_Sys}: In-system gate turn-on rising time at worst case of load, voltage/current conditions.

T_D(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.

In the example, DT_Settingis set to 250 ns.

It should be noted that the UCC21520 dead time setting is decided by the DT pin configuration (See Section

9.4.2), and it cannot automatically fine-tune the dead time based on system conditions. It is recommended to

parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with R_DTto achieve better noise immunity.

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10.2.2.9 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (for example,

TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the power

transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of

unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep

such ringing below the threshold. Below are a few examples of implementing negative gate drive bias.

Figure 10-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on

the isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power

supply, V_A, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V.

The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for

a half-bridge configuration, and there will be steady state power consumption from R_Z.

HV DC-Link

VDDA

R_OFF

16

1

C_A1

+

V_A

œ

C_IN

R_Z

25 V

R_ON

OUTA

VSSA

15

14

2

3

4

5

6

8

C_A2

V_Z= 5.1 V

SW

Functional

Isolation

VDDB

11

10

9

OUTB

VSSB

Figure 10-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

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Figure 10-3 shows another example which uses two supplies (or single-input-double-output power supply).

Power supply V_A+determines the positive drive output voltage and V_A–determines the negative turn-off voltage.

The configuration for channel B is the same as channel A. This solution requires more power supplies than the

first example, however, it provides more flexibility when setting the positive and negative rail voltages.

HV DC-Link

VDDA

OUTA

R_OFF

R_ON

16

15

1

2

3

4

5

6

8

C_A1

+

V_A+

œ

C_IN

C_A2

+

V_A-

œ

VSSA

14

Functional

Isolation

SW

VDDB

11

10

9

OUTB

VSSB

Figure 10-3. Negative Bias with Two Iso-Bias Power Supplies

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The last example, shown in Figure 10-4, is a single power supply configuration and generates negative bias

through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply

and the bootstrap power supply can be used for the high side drive. This design requires the least cost and

design effort among the three solutions. However, this solution has limitations:

1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which

means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a

fixed duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors favor this

solution.

2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,

which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)

diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%

duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in

the other two example circuits.

VDD

R_BOOT

HV DC-Link

VDDA

C_Z

V_Z

R_OFF

R_ON

16

15

14

1

2

3

4

5

6

8

OUTA

VSSA

C_IN

C_BOOT

R_GS

SW

Functional

Isolation

VDD

VDDB

C_Z

V_Z

R_OFF

R_ON

11

10

9

OUTB

VSSB

C_VDD

R_GS

VSS

Figure 10-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

32

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10.2.3 Application Curves

Figure 10-5 and Figure 10-6 shows the bench test waveforms for the design example shown in Figure 10-1

under these conditions: VCC = 5 V, VDD = 20 V, f_SW= 100 kHz, V_DC-Link= 0 V.

Channel 1 (Yellow): UCC21520 INA pin signal.

Channel 2 (Blue): UCC21520 INB pin signal.

Channel 3 (Pink): Gate-source signal on the high side power transistor.

Channel 4 (Green): Gate-source signal on the low side power transistor.

In Figure 10-5, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on

the power transistor have a 250-ns dead time, shown in the measurement section of Figure 10-5. The dead-time

matching is less than 1 ns with the 250-ns dead-time setting.

Figure 10-6 shows a zoomed-in version of the waveform of Figure 10-5, with measurements for propagation

delay and rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is

measured between the power transistors’ gate and source pins, and is not measured directly from the driver

OUTA and OUTB pins. Due to the split on and off resistors (R_on,R_off) and different sink and source currents,

different rising (16 ns) and falling time (9 ns) are observed in Figure 10-6.

Figure 10-5. Bench Test Waveform for INA/B and

OUTA/B

Figure 10-6. Zoomed-In bench-test waveform

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11 Power Supply Recommendations

The recommended input supply voltage (VCCI) for the UCC21520 and the UCC21520A is between 3 V and 18

V. The output bias supply voltage (VDDA/VDDB) range depends on which version of UCC21520 one is using.

The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection

feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more

information on UVLO see Section 9.3.1). The upper end of the VDDA/VDDB range depends on the maximum

gate voltage of the power device being driven by the UCC21520 and the UCC21520A. The UCC21520 and the

UCC21520A have a recommended maximum VDDA/VDDB of 25 V.

A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned

as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further

suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional

≤100-nF capacitor in parallel for high frequency filtering.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount

of current drawn by the logic circuitry within the input side of the UCC21520 and the UCC21520A, this bypass

capacitor has a minimum recommended value of 100 nF.

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12 Layout

12.1 Layout Guidelines

One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21520 and the

UCC21520A. Below are some key points.

Component Placement:

•

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins

and between the VDD and VSS pins to support high peak currents when turning on the external power

transistor.

•

To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the

source of the top transistor and the source of the bottom transistor must be minimized.

It is recommended to place the dead-time setting resistor, R_DT, and its bypassing capacitor close to DT pin of

the UCC21520 or the UCC21520A.

It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, C_DIS, close to DIS pin when connecting to

a µC with distance.

Grounding Considerations:

•

It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal

physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the

transistors. The gate driver must be placed as close as possible to the transistors.

•

Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-

referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor

is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This

recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and

area on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:

•

To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB

traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination

that may compromise the UCC21520’s and the UCC21520A’s isolation performance.

For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could

operate with a DC-link voltage up to 1500 V_DC, one should try to increase the creepage distance of the PCB

layout between the high and low-side PCB traces.

•

Thermal Considerations:

•

A large amount of power may be dissipated by the UCC21520 or the UCC21520A if the driving voltage is

high, the load is heavy, or the switching frequency is high (refer to Section 10.2.2.5 for more details). Proper

PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal

impedance (θ_JB).

•

Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority

on maximizing the connection to VSSA and VSSB (see Figure 12-2 and Figure 12-3). However, high voltage

PCB considerations mentioned above must be maintained.

If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and

VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind

that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

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12.2 Layout Example

Figure 12-1 shows a 2-layer PCB layout example with the signals and key components labeled.

Figure 12-1. Layout Example

Figure 12-2 and Figure 12-3 shows top and bottom layer traces and copper.

Note

There are no PCB traces or copper between the primary and secondary side, which ensures isolation

performance.

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the

creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node

VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

Figure 12-3. Bottom Layer Traces and Copper

Figure 12-2. Top Layer Traces and Copper

Figure 12-4 and Figure 12-5 are 3D layout pictures with top view and bottom views.

Note

The location of the PCB cutout between the primary side and secondary sides, which ensures

isolation performance.

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Figure 12-4. 3-D PCB Top View

Figure 12-5. 3-D PCB Bottom View

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13 Device and Documentation Support

13.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

•

Semiconductor and IC Package Thermal Metrics Application Report

Isolation Glossary

13.3 Certifications

UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate

Number: 20160516-E181974,

VDE Pruf- und Zertifizierungsinstitut Certification, Certificate of Conformity with Factory Surveillance

CQC Online Certifications Directory, "GB4943.1-2011, Digital Isolator Certificate" Certificate

Number:CQC16001155011

CSA Online Certifications Directory, "CSA Certificate of Compliance" Certificate Number:70097761, Master

Contract Number:220991

13.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.5 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.8 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38

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GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC21520ADW
厂家：	TEXAS INSTRUMENTS
描述：	具有双输入、禁用引脚、8V UVLO 功能、采用 DW 封装的 5.7kVrms、4A/6A 双通道隔离式栅极驱动器 \| DW \| 16 \| -40 to 125 栅极驱动驱动器
文件：	总48页 (文件大小：2563K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21520ADW [TI]

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