UCC21530QDWKQ1_技术文档

UCC21530-Q1

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UCC21530-Q1 4-A, 6-A, 5.7-kV_RMSIsolated Dual-Channel Gate Driver

with 3.3-mm Channel-to-Channel Spacing

1 Features

3 Description

•

AEC-Q100 qualified with:

The UCC21530-Q1 is an isolated dual-channel gate

driver with 4-A source and 6-A sink peak current. It

is designed to drive IGBTs, Si MOSFETs, and SiC

MOSFETs up to 5-MHz with best-in-class propagation

delay and pulse-width distortion.

– Device temperature grade 1

– Device HBM ESD classification level H2

– Device CDM ESD classification level C6

Functional Safety Quality-Managed

– Documentation available to aid functional safety

system design

Universal: dual low-side, dual high-side or half-

bridge driver

Wide body SOIC-14 (DWK) package

3.3-mm spacing between driver channels

Switching parameters:

•

The input side is isolated from the two output

drivers by a 5.7-kV_RMSreinforced isolation barrier,

with a minimum of 100-V/ns common-mode transient

immunity (CMTI). Internal functional isolation between

the two secondary-side drivers allows a working

voltage of up to 1850 V.

•

This driver can be configured as two low-side drivers,

two high-side drivers, or a half-bridge driver with

programmable dead time (DT). The EN pin pulled low

shuts down both outputs simultaneously and allows

for normal operation when left open or pulled high. As

a fail-safe measure, primary-side logic failures force

both outputs low.

– 19-ns typical propagation delay

– 10-ns minimum pulse width

– 5-ns maximum delay matching

– 6-ns maximum pulse-width distortion

Common-mode transient immunity (CMTI) greater

than 100-V/ns

•

Isolation barrier life >40 years

4-A peak source, 6-A peak sink output

TTL and CMOS compatible inputs

3-V to 18-V input VCCI range

Up to 25-V VDD output drive supply

– 8-V and 12-V VDD UVLO options

Programmable overlap and dead time

Rejects input pulses and noise transients shorter

than 5 ns

The device accepts VDD supply voltages up to 25 V.

A wide input VCCI range from 3 V to 18 V makes

the driver suitable for interfacing with both analog and

digital controllers. All the supply voltage pins have

under voltage lock-out (UVLO) protection.

•

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

UCC21530-Q1

DWK SOIC (14) 10.30 mm × 7.50 mm

•

Operating temperature range –40 to +125°C

Safety-related certifications:

UCC21530B-Q1 DWK SOIC (14) 10.30 mm × 7.50 mm

– 8000-V_PKisolation per DIN V VDE V

0884-11 :2017-01

– 5.7-kV_RMSisolation for 1 minute per UL 1577

– CSA certification per IEC 60950-1, IEC

62368-1, IEC 61010-1 and IEC 60601-1 end

equipment standards

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

– CQC certification per GB4943.1-2011

2 Applications

•

HEV and BEV battery chargers

Solar string and central inverters

AC-to-DC and DC-to-DC charging piles

AC inverter and servo drive

AC-to-DC and DC-to-DC power delivery

Energy storage systems

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 6

6.7 Safety-Related Certifications...................................... 7

6.8 Safety-Limiting Values................................................ 7

6.9 Electrical Characteristics.............................................8

6.10 Switching Characteristics..........................................9

6.11 Insulation Characteristics Curves............................10

6.12 Typical Characteristics............................................ 11

7 Parameter Measurement Information..........................16

7.1 Propagation Delay and Pulse Width Distortion.........16

7.2 Rising and Falling Time.............................................16

7.3 Input and Enable Response Time.............................16

7.4 Programable Dead Time...........................................17

7.5 Power-Up UVLO Delay to OUTPUT......................... 17

7.6 CMTI Testing.............................................................18

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................23

9 Layout.............................................................................37

9.1 Layout Guidelines..................................................... 37

9.2 Layout Example........................................................ 38

10 Device and Documentation Support..........................40

10.1 Documentation Support.......................................... 40

10.2 Receiving Notification of Documentation Updates..40

10.3 Community Resources............................................40

10.4 Trademarks.............................................................40

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (November 2018) to Revision C (March 2019)

Page

•

Initial release.......................................................................................................................................................1

Changes from Revision C (March 2019) to Revision D (April 2021)

Page

•

Added 8-V UVLO option to features, description, and device information sections .......................................... 1

Added information to pin 7 in Pin function table................................................................................................. 3

Added VDE certification, CSA master contract, and CQC certificate numbers to Safety-Related Certifications

table ...................................................................................................................................................................7

Added 8-V UVLO thresholds to EC table ...........................................................................................................8

Added 8-V UVLO thresholds and hysteresis across temperature ................................................................... 11

•

2

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5 Pin Configuration and Functions

Figure 5-1. DWK Package 14-Pin SOIC Top View

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

DT pin configuration:

•

Tying DT to VCCI disables the DT feature and allows the outputs to overlap.

Placing a resistor (R_DT) between DT and GND adjusts dead time according to the

equation: DT (in ns) = 10 × R_DT(in kΩ). TI recommends bypassing this pin with a

ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity.

DT

6

I

Enable both driver outputs if asserted high, disable the output if set low. It is recommended

to tie this pin to VCCI if not used to achieve better noise immunity. Bypass using a ≈ 1-nF

low ESR/ESL capacitor close to EN pin when connecting to a micro controller with distance.

EN

5

4

1

I

P

I

GND

INA

Primary-side ground reference. All signals in the primary side are referenced to this ground.

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

INB

2

I

NC

7

–

No internal connection. This pin can be left floating, tied to VCCI, or tied to GND.

Output of driver A. Connect to the gate of the A channel FET or IGBT.

Output of driver B. Connect to the gate of the B channel FET or IGBT.

OUTA

OUTB

15

10

O

Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor

located as close to the device as possible.

VCCI

VDDA

3

8

P

Primary-side supply voltage. This pin is internally shorted to pin 3.

Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL

capacitor located as close to the device as possible.

16

Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL

capacitor located as close to the device as possible.

VDDB

11

P

VSSA

VSSB

14

9

P

Ground for secondary-side driver A. Ground reference for secondary side A channel.

Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1) P =Power, I= Input, O= Output

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

20

UNIT

V

Input bias pin supply voltage

Driver bias supply

VCCI to GND

VDDA-VSSA, VDDB-VSSB

30

V

V_VDDA+0.5,

V_VDDB+0.5

OUTA to VSSA, OUTB to VSSB

–0.5

–2

V

Output signal voltage

OUTA to VSSA, OUTB to VSSB,

Transient for 200 ns

V_VDDA+0.5,

V_VDDB+0.5

INA, INB, EN, DT to GND

INA, INB Transient for 200ns

|VSSA-VSSB|

–0.5

–2

V_VCCI+0.5

1850

V

Input signal voltage

Channel to channel internal isolation voltage

V

(2)

Junction temperature, T_J

–40

–65

150

°C

Storage temperature, T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) To maintain the recommended operating conditions for T_J, see the Section 6.4.

6.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

VCCI

VCCI Input supply voltage

3

18

25

V

8-V UVLO version -

UCC21530B-Q1

VDDA-

VSSA,

VDDB-

VSSB

9.2

Driver output bias supply refer to Vss

12-V UVLO version -

UCC21530-Q1

14.7

25

V

T_A

T_J

Ambient Temperature

Junction Temperature

–40

125

130

°C

4

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6.4 Thermal Information

UCC21530-Q1

UNIT

DWK-14 (SOIC)

THERMAL METRIC⁽¹⁾

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

68.3

31.7

27.6

17.7

27

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

VALUE

1810

50

UNIT

mW

P_D

Power dissipation by UCC21530-Q1

P_DI

Power dissipation by transmitter side of

UCC21530-Q1

VCCI = 18 V, VDDA/B = 15 V, INA/B = 3.3 V,

3.9 MHz 50% duty cycle square wave 1-nF

load

mW

P_DA, P_DB

Power dissipation by each driver side of

UCC21530-Q1

880

mW

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6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

Shortest pin-to-pin distance through air

VALUE

> 8

UNIT

mm

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance across the package surface

> 8

mm

Minimum internal gap (internal clearance) of the double

insulation (2 × 10.5 µm)

DTI

CTI

Distance through insulation

>21

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

> 600

I

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category per

IEC 60664-1

DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage (bipolar)

2121

V_PK

AC voltage (sine wave); time dependent dielectric breakdown

(TDDB), test (See Figure 6-1)

1500

2121

8000

V_RMS

V_DC

V_PK

Maximum working isolation

voltage

V_IOWM

DC voltage

Maximum transient isolation V_TEST= V_IOTM, t = 60 sec (qualification)

V_IOTM

V_IOSM

voltage

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

Maximum surge isolation

voltage⁽³⁾

Test method per IEC 62368-1, 1.2/50 µs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

8000

<5

V_PK

Method a, After Input/Output safety test subgroup 2/3.

V_ini= V_IOTM, t_ini= 60s;

V_pd(m)= 1.2 X V_IORM= 2545 V_PK, t_m= 10s

Method a, After environmental tests subgroup 1.

V_ini= V_IOTM, t_ini= 60s;

V_pd(m)= 1.6 X V_IORM= 3394 V_PK, t_m= 10s

<5

q_pd

Apparent charge⁽⁴⁾

pC

Method b1; At routine test (100% production) and

preconditioning (type test)

<5

V_ini= 1.2 × V_IOTM; t_ini= 1s;

V_pd(m)= 1.875 * V_IORM= 3977 V_PK, t_m= 1s

Barrier capacitance, input to

output⁽⁵⁾

C_IO

R_IO

V_IO= 0.4 sin (2πft), f =1 MHz

1.2

pF

Ω

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output⁽⁵⁾

V_IO= 500 V at 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S=150°C

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 sec. (qualification),

V_TEST= 1.2 × V_ISO= 6840V_RMS, t = 1 sec (100% production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of

the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become

equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

6

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6.7 Safety-Related Certifications

VDE

CSA

UL

CQC

Certified according to

DIN V VDE V

0884-11:2017-01 and

DIN EN 60950-1 (VDE

0805 Tiel 1):2014-08

Recognized under UL

1577 Component Recognition Certified according to GB 4943.1-2011

Program

Certified according to IEC 60950-1, IEC

62368-1, IEC 61010-1 and IEC 60601-1

Reinforced Insulation

Maximum Transient

Isolation voltage,

Reinforced insulation per CSA 60950-1- Single protection, 5700 V_RMSReinforced Insulation, Altitude ≤ 5000

07+A1+A2 and IEC 60950-1 2nd

Ed.+A1+A2, 800 VRMS maximum

working voltage (pollution degree 2,

m, Tropical Climate 660 VRMS

maximum working voltage

8000 VPK; Maximum

Repetitive Peak Isolation material group I) Reinforced insulation

Voltage, 2121 VPK;

Maximum Surge

Isolation Voltage, 8000

VPK

per CSA 62368-1-14 and IEC 62368-1

2nd Ed., 800 VRMS maximum working

voltage (pollution degree 2, material

group I); Basic insulation per CSA

61010-1-12+A1 and IEC 61010-1 3rd

Ed., 600 VRMS maximum working

voltage (pollution degree 2, material

group III); 2 MOPP (Means of Patient

Protection) per CSA 60601- 1:14 and

IEC 60601-1 Ed.3+A1, 250 VRMS

maximum working voltage

Certification number:

40040142

Master contract number: 220991

File number: E181974

Certificate number: CQC16001155011

6.8 Safety-Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of

the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

SIDE

MIN

TYP

MAX

UNIT

R_θJA= 68.3°C/W, VDDA/B = 15 V, T_A=

25°C, T_J= 150°C

See Figure 6-2

DRIVER A,

DRIVER B

58

mA

Safety output supply

current

I_S

R_θJA= 68.3°C/W, VDDA/B = 25 V, T_A=

25°C, T_J= 150°C

See Figure 6-2

DRIVER A,

DRIVER B

35

mA

INPUT

DRIVER A

DRIVER B

TOTAL

50

880

R_θJA= 68.3°C/W, T_A= 25°C, T_J= 150°C

See Figure 6-3

P_S

T_S

Safety supply power

Safety temperature⁽¹⁾

mW

°C

880

1810

150

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The

I_Sand P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Section 6.4 table is that of a device installed on a high-K test board for leaded

surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

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6.9 Electrical Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12V or 15V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, DT pin tied to VCCI, C_L= 0 pF, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENTS

I_VCCI

VCCI quiescent current

V_INA= 0 V, V_INB= 0 V

1.5

1.0

2.0

1.8

mA

I_VDDA

I_VDDB

,

VDDA and VDDB quiescent current V_INA= 0 V, V_INB= 0 V

I_VCCI

VCCI per operating current

(f = 500 kHz) current per channel

(f = 500 kHz) current per channel,

VDDA and VDDB operating current C_OUT= 100 pF,

V_VDDA, V_VDDB= 15 V

I_VDDA

I_VDDB

3.0

mA

VCCI TO GND UNDERVOLTAGE THRESHOLDS

V_{VCCI_ON}

V_{VCCI_OFF}

V_{VCCI_HYS}

UVLO Rising threshold

UVLO Falling threshold

UVLO Threshold hysteresis

2.55

2.35

2.7

2.5

0.2

2.85

2.65

V

UCC21530B-Q1 VDD to VSS UNDERVOLTAGE THRESHOLDS

V_{VDDA_ON}

V_{VDDB_ON}

,

UVLO Rising threshold

UVLO Falling threshold

UVLO Threshold hysteresis

8

8.5

8

9

V

V_{VDDA_OFF,}

V_{VDDB_OFF}

7.5

8.5

V_{VDDA_HYS,}

V_{VDDB_HYS}

0.5

UCC21530-Q1 VDD TO VSS UNDERVOLTAGE THRESHOLDS

V_{VDDA_ON}

V_{VDDB_ON}

,

UVLO Rising threshold

UVLO Falling threshold

UVLO Threshold hysteresis

12.5

11.5

13.5

12.5

1.0

14.5

13.5

V

V_{VDDA_OFF,}

V_{VDDB_OFF}

V_{VDDA_HYS,}

V_{VDDB_HYS}

INA and INB

V_INAH, V_INBHInput high threshold voltage

1.6

0.8

1.8

1

2

V

V_INAL, V_INBL

V_{INA_HYS}

V_{INB_HYS}

Input low threshold voltage

1.2

,

Input threshold hysteresis

0.8

V

Negative transient, ref to GND, 50 ns Not production tested, bench test

pulse

V_INA, V_INB

–5

only

EN THRESHOLDS

V_ENH

V_ENL

Enable high voltage

2.0

V

Enable low voltage

0.8

8

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V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12V or 15V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, DT pin tied to VCCI, C_L= 0 pF, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

C_VDD= 10 µF, C_LOAD= 0.18 µF, f =

1 kHz, bench measurement

I_OA+, I_OB+

Peak output source current

Peak output sink current

4

6

A

C_VDD= 10 µF, C_LOAD= 0.18 µF, f =

1 kHz, bench measurement

I_OA-, I_OB-

I_OUT= –10 mA, T_A= 25°C, R_OHA

,

R_OHBdo not represent drive pull-up

performance. See t_RISEin Section

6.10 and Section 8.3.4 for details.

R_OHA, R_OHB

Output resistance at high state

5

Ω

R_OLA, R_OLB

V_OHA, V_OHB

Output resistance at low state

Output voltage at high state

I_OUT= 10 mA, T_A= 25°C

0.55

Ω

V

V_VDDA, V_VDDB= 15 V, I_OUT= –10

mA, T_A= 25°C

14.95

V_VDDA, V_VDDB= 15 V, I_OUT= 10

mA, T_A= 25°C

V_OLA, V_OLB

Output voltage at low state

5.5

mV

DEADTIME AND OVERLAP PROGRAMMING

DT pin tied to VCCI

R_DT= 20 kΩ

Overlap determined by INA INB

160 200 240

-

Dead time

ns

6.10 Switching Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12V or 15V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_RISE

Output rise time, 20% to 80%

measured points

6

16

ns

C_OUT= 1.8 nF

t_FALL

Output fall time, 90% to 10%

measured points

7

12

20

30

ns

C_OUT= 1.8 nF

t_PWmin

t_PDHL

t_PDLH

Minimum pulse width

Output off for less than minimum,

C_OUT= 0 pF

Propagation delay from INx to OUTx

falling edges

14

19

Propagation delay from INx to OUTx

rising edges

t_PWD

t_DM

Pulse width distortion |t_PDLH– t_PDHL

|

6

5

ns

Propagation delays matching

between VOUTA, VOUTB

f = 100 kHz

t_{VCCI+ to OUT}VCCI Power-up Delay Time: UVLO

Rise to OUTA, OUTB,

40

50

INA or INB tied to VCCI

See Figure 7-5

µs

t_{VDD+ to OUT}VDDA, VDDB Power-up Delay Time:

UVLO Rise to OUTA, OUTB

See Figure 7-6

INA or INB tied to VCCI

Slew rate of GND vs. VSSA/B, INA

and INB both are tied to GND or

VCCI; V_CM=1500 V;

High-level common-mode transient

|CM_H|

100

immunity (See Section 7.6)

V/ns

Slew rate of GND vs. VSSA/B, INA

and INB both are tied to GND or

VCCI; V_CM=1500 V;

Low-level common-mode transient

|CM_L|

immunity (See Section 7.6)

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6.11 Insulation Characteristics Curves

1.E+11

1.E+10

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

87.5%

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

1.E+2

1.E+1

20%

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

Figure 6-1. Reinforced Isolation Capacitor Life Time Projection

70

60

50

40

30

20

10

0

2000

VDD=15V

VDD=25V

1600

1200

800

400

0

25

50

75

Ambient Temperature (°C)

100

125

150

175

0

25

50

75

Ambient Temperature (°C)

100

125

150

175

D001

D002

Figure 6-2. Thermal Derating Curve for Safety-

Related Limiting Current (Current in Each Channel

with Both Channels Running Simultaneously)

Figure 6-3. Thermal Derating Curve for Safety-

Related Limiting Power

10

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6.12 Typical Characteristics

VDDA = VDDB = 15 V, VCCI = 3.3 V, T_A= 25°C, No load. (unless otherwise noted)

16

12

8

60

50

40

30

20

10

0

4

VDD=15V

VDD=25V

VDD=15V

VDD=25V

0

1000

2000 3000

Frequency (kHz)

4000

5000

0

500

1000

1500

Frequency (kHz)

2000

2500

3000

D003

D004

Figure 6-4. Per Channel Current Consumption vs.

Frequency (No Load, VDD = 15 V or 25 V)

Figure 6-5. Per Channel Current Consumption

(I_VDDA/B) vs. Frequency (1-nF Load, VDD = 15 V or

25 V)

27.5

25

6

50kHz

250kHz

500kHz

5

22.5

20

1MHz

4

17.5

15

3

2

1

0

12.5

10

7.5

5

VDD=15V

VDD=25V

2.5

0

10

20

30

40

50

60

Frequency (kHz)

70

80 90 100

-40 -20

0

20

40

60

80 100 120 140 160

D005

Temperature (èC)

D001

Figure 6-6. Per Channel Current Consumption

(I_VDDA/B) vs. Frequency (10-nF Load, VDD = 15 V

or 25 V)

Figure 6-7. Per Channel (I_VDDA/B) Supply Current

Vs. Temperature (VDD=15V, No Load, Different

Switching Frequencies)

1.6

1.2

0.8

0.4

2

1.8

1.6

1.4

1.2

VDD=15V

VDD=25V

VCCI= 3.3V

VCCI= 5V

0

-40

1

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-20

0

20

40

60

80

100 120 140

D006

Temperature (èC)

D001

Figure 6-8. Per Channel (I_VDDA/B) Quiescent Supply

Current vs Temperature (No Load, Input Low, No

Switching)

Figure 6-9. I_VCCIQuiescent Supply Current vs

Temperature (No Load, Input Low, No Switching)

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25

20

15

10

5

10

8

6

Output Pull-Up

Output Pull-Down

4

2

t_RISE

t_FALL

0

2

4

6

8

10

-40

-20

0

20

40

60

80

100 120 140

Load (nF)

Temperature (èC)

D001

Figure 6-10. Rising and Falling Times vs. Load

Figure 6-11. Output Resistance vs. Temperature

28

20

24

20

16

12

19

18

17

16

Rising Edge (t_PDLH

Falling Edge (t_PDHL

)

Rising Edge (t_PDLH)

Falling Edge (t_PDHL

)

8

15

-40

-20

0

20

40

60

80

100 120 140

3

6

9

12

15 18

Temperature (èC)

VCCI (V)

D001

Figure 6-12. Propagation Delay vs. Temperature

Figure 6-13. Propagation Delay vs. VCCI

5

3

1

2.5

0

-2.5

-5

-1

-3

-5

Rising Edge

Falling Edge

10

13

16

19

22

25

-40

-20

0

20

40

60

80

100 120 140

VDDA/B (V)

Temperature (èC)

D001

Figure 6-15. Propagation Delay Matching (t_DM) vs.

VDD

Figure 6-14. Pulse Width Distortion vs.

Temperature

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5

550

530

510

490

470

450

2.5

0

-2.5

Rising Edge

Falling Edge

-5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 6-16. Propagation Delay Matching (t_DM) vs.

Temperature

Figure 6-17. 8-V UVLO Hysteresis vs. Temperature

10

1100

1080

1060

1040

1020

1000

980

9

8

7

960

940

6

920

V_{VDD_ON}

V_{VDD_OFF}

900

5

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Temperature (èC)

D001

Figure 6-19. 12-V UVLO Hysteresis vs.

Temperature

Figure 6-18. 8-V UVLO Threshold vs. Temperature

15

900

860

820

780

740

700

14

13

12

11

VCC=3.3V

VCC=5V

VCC=12V

V_{VDD_ON}

V_{VDD_OFF}

10

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 6-21. INA/B Hysteresis vs. Temperature

Figure 6-20. 12-V UVLO Threshold vs. Temperature

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1.2

1.14

1.08

1.02

0.96

0.9

2

1.92

1.84

1.76

1.68

1.6

VCC=3.3V

VCC= 5V

VCC=12V

VCC=3.3V

VCC= 5V

VCC=12V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 6-22. INA/B Low Threshold

Figure 6-23. INA/B High Threshold

1200

1000

800

1.1

VCC=3.3V

VCC=5V

VCC=18V

1

600

0.9

400

VCC=3.3V

VCC=5.0V

VCC=18V

200

-40

0.8

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D001

Figure 6-24. EN Threshold Hysteresis vs.

Temperature

Figure 6-25. EN Low Threshold

2

1500

1200

900

600

300

0

R_DT= 20kW

R_DT= 100kW

1.8

1.6

1.4

1.2

1

VCC=3.3V

VCC=5.0V

VCC=18V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

Temperature (èC)

D001

Figure 6-27. Dead Time vs. Temperature (with R_DT

= 20 kΩ and 100 kΩ)

Figure 6-26. EN High Threshold

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5

-6

-17

-28

-39

-50

R_DT= 20kW

R_DT= 100kW

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Figure 6-28. Dead Time Matching vs. Temperature (with R_DT= 20 kΩ and 100 kΩ)

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7 Parameter Measurement Information

7.1 Propagation Delay and Pulse Width Distortion

Figure 7-1 shows how one calculates pulse width distortion (t_PWD) and delay matching (t_DM) from the

propagation delays of channels A and B. It can be measured by ensuring that both inputs are in phase and

disabling the dead time function by shorting the DT Pin to VCC.

INA/B

tPDHLA

tPDLHA

tDM

OUTA

tPDLHB

tPDHLB

tPWDB = |tPDLHB t tPDHLB|

OUTB

Figure 7-1. Overlapping Inputs, Dead Time Disabled

7.2 Rising and Falling Time

Figure 7-2 shows the criteria for measuring rising (t_RISE) and falling (t_FALL) times. For more information on how

short rising and falling times are achieved see Section 8.3.4.

90%

80%

t_RISE

t_FALL

20%

10%

Figure 7-2. Rising and Falling Time Criteria

7.3 Input and Enable Response Time

Figure 7-3 shows the response time of the enable function. For more information, see Section 8.4.1 .

INx

EN

EN Low

Response Time

EN High

Response Time

OUTx

t_PDLH

90%

t_PDHL

10%

Figure 7-3. Enable Pin Timing

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7.4 Programable Dead Time

Tying DT to VCCI disables DT feature and allows the outputs to overlap. Placing a resistor (R_DT) between DT pin

and GND can adjust the dead time. For more details on dead time, refer to Section 8.4.2 .

INA

INB

90%

OUTA

10%

tPDHL

tPDLH

90%

OUTB

10%

tPDHL

Dead Time

(Set by RDT

Dead Time

(Determined by Input signals if

)

longer than DT set by RDT

)

Figure 7-4. Dead-Time Switching Parameters

7.5 Power-Up UVLO Delay to OUTPUT

Whenever the supply voltage VCCI crosses from below the falling threshold V_{VCCI_OFF}to above the rising

threshold V_{VCCI_ON}, and whenever the supply voltage VDDx crosses from below the falling threshold V_{VDDx_OFF}

to above the rising threshold V_{VDDx_ON}, there is a delay before the outputs begin responding to the inputs. For

VCCI UVLO this delay is defined as t_{VCCI+ to OUT}, and is typically 40 µs. For VDDx UVLO this delay is defined as

t_{VDD+ to OUT}, and is typically 50 µs. TI recommends allowing some margin before driving input signals, to ensure

the driver VCCI and VDD bias supplies are fully activated. Figure 7-5 and Figure 7-6 show the power-up UVLO

delay timing diagram for VCCI and VDD.

Whenever the supply voltage VCCI crosses below the falling threshold V_{VCCI_OFF}, or VDDx crosses below

the falling threshold V_{VDDx_OFF}, the outputs stop responding to the inputs and are held low within 1 µs. This

asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.

VCCI,

INx

VCCI,

INx

V_{VCCI_ON}

V_{VCCI_OFF}

VDDx

OUTx

VDDx

OUTx

t_{VCCI+ to OUT}

t_{VDD+ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

Figure 7-5. VCCI Power-Up UVLO Delay

Figure 7-6. VDDA/B Power-Up UVLO Delay

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7.6 CMTI Testing

Figure 7-7 is a simplified diagram of the CMTI testing configuration.

Figure 7-7. Simplified CMTI Testing Setup

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8 Detailed Description

8.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are

often placed between the output of control devices and the gates of power transistors. There are several

instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.

This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V

logic signal capable of only delivering a few mA.

The UCC21530-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and

motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs. UCC21530-Q1 has

many features that allow it to integrate well with control circuitry and protect the transistors it drives such as:

resistor-programmable dead time (DT) control, an EN pin, and under voltage lock out (UVLO) for both input and

output voltages. The UCC21530-Q1 also holds its outputs low when the inputs are left open or when the input

pulse is not wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and analog

power controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and

independent control of each of the outputs.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC21530-Q1 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks

between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V_{VDD_ON}at device

start-up or lower than V_{VDD_OFF}after start-up, the VDD UVLO feature holds the effected output low, regardless of

the status of the input pins (INA and INB).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by

an active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in Figure 8-1). In this condition,

the upper PMOS is resistively held off by R_Hi-Zwhile the lower NMOS gate is tied to the driver output through

R_CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS

device, typically less than 1.5V, when no bias power is available.

VDD

R_{HI_Z}

Output

Control

OUT

R_CLAMP

R_CLAMPis activated

during UVLO

VSS

Figure 8-1. Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is

ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is

bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC21530-Q1 also has an internal under voltage lock out (UVLO) protection feature. The

device isn't active unless the voltage, VCCI, is going to exceed V_{VCCI_ON}on start up. The signal will cease to

be delivered once the pin receives a voltage less than V_{VCCI_OFF}. In the same way as the VDD UVLO, there is

hysteresis (V_{VCCI_HYS}) to ensure stable operation.

UCC21530-Q1 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

Table 8-1. UCC21530-Q1 VCCI UVLO Feature Logic

CONDITION

INPUTS

OUTPUTS

INA

INB

OUTA

OUTB

VCCI-GND < V_{VCCI_ON}during device start up

H

L

H

L

VCCI-GND < V_{VCCI_ON}during device start up

VCCI-GND < V_{VCCI_OFF}after device start up

H

L

H

L

H

L

H

L

Table 8-2. UCC21530-Q1 VDD UVLO Feature Logic

CONDITION

INPUT: INx

OUTPUT: OUTx

VDDx-VSSx < V_{VDD_ON}during device start up

L

H

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CONDITION

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Table 8-2. UCC21530-Q1 VDD UVLO Feature Logic (continued)

INPUT: INx

OUTPUT: OUTx

VDDx-VSSx < V_{VDD_OFF}after device start up

L

H

8.3.2 Input and Output Logic Table

Table 8-3. INPUT/OUTPUT Logic Table⁽¹⁾

Assume VCCI, VDDA, VDDB are powered up. See Section 8.3.1 for more information on UVLO operation modes.

INPUTS

OUTPUTS

EN

NOTE

INA

L

INB

L

OUTA

OUTB

H or Left Open

L

H

L

If Dead Time function is used, output transitions occur after the

dead time expires. See Section 8.4.2

L

H

L

H

L

H

L

DT is left open or programmed with R_DT

H

L

H

L

DT pin pulled to VCCI

-

Left Open Left Open H or Left Open

Bypass using a ≥ 1-nF low ESR/ESL capacitor close to EN pin

when connecting to a µC with distance

X

L

(1) "X" means L, H or left open.

8.3.3 Input Stage

The input signal pins (INA and INB) of UCC21530-Q1 are based on a TTL and CMOS compatible input-

threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with

logic-level control signals (Such as those from 3.3-V micro-controllers), since UCC21530-Q1 has a typical high

threshold (V_INA/BH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see Figure

6-22,Figure 6-23). A wide hysterisis (V_{INA/B_HYS}) of 0.8 V makes for good noise immunity and stable operation.

If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically

200 kΩ (See Section 8.2). However, it is still recommended to ground an input if it is not being used.

Since the input side of UCC21530-Q1 is isolated from the output drivers, the input signal amplitude can be larger

or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when

integrating with control signal sources, and allows the user to choose the most efficient VDD for their chosen

gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than VCCI.

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8.3.4 Output Stage

The UCC21530-Q1’s output stages features a pull-up structure which delivers the highest peak-source current

when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the power

switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel

MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to

provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning

on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The

on-resistance of this N-channel MOSFET (R_NMOS) is approximately 1.47 Ω when activated.

The R_OHparameter is a DC measurement and it is representative of the on-resistance of the P-channel device

only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only

for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the

UCC21530-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the R_OH

parameter.

The pull-down structure in UCC21530-Q1 is simply composed of an N-channel MOSFET. The R_OLparameter,

which is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both

outputs of the UCC21530-Q1 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The

output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out stage which

delivers very low drop-out.

VDD

R_OH

Shoot-

R_NMOS

Input

Signal

Through

Prevention

Circuitry

OUT

VSS

R_OL

Pull Up

Figure 8-2. Output Stage

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8.3.5 Diode Structure in UCC21530-Q1

Figure 8-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21530-Q1. This

provides a pictorial representation of the absolute maximum rating for the device.

Figure 8-3. ESD Structure

8.4 Device Functional Modes

8.4.1 Enable Pin

Setting the EN pin low, i.e. V_EN≤0.8V, shuts down both outputs simultaneously. Pull the EN pin high (or left

open), i.e. V_EN≥2.0V, allows UCC21530-Q1 to operate normally. The EN pin is quite responsive, as far as

propagation delay and other switching parameters are concerned, the delay between EN are OUTA and OUTB

is about 40ns. The EN pin is only functional (and necessary) when VCCI stays above the UVLO threshold. It is

highly recommended to tie EN to VCCI directly to achieve better noise immunity.

8.4.2 Programmable Dead Time (DT) Pin

UCC21530-Q1 allows the user to adjust dead time (DT) in the following ways:

8.4.2.1 DT Pin Tied to VCC

Outputs completely match inputs, so no minimum dead time is asserted. This allows outputs to overlap. It is

recommended to connect this pin to VCCI directly if it is not used to achieve better noise immunity.

8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins

Program t_DTby placing a resistor, R_DT, between the DT pin and GND. TI recommends bypassing this pin with a

ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity. The appropriate R_DTvalue

can be determined from:

t_DTö 10ìR_DT

where

(1)

•

t_DTis the programmed dead time, in nanoseconds.

R_DTis the value of resistance between DT pin and GND, in kilo-ohms.

The steady state voltage at the DT pin is about 0.8 V. R_DTprograms a small current at this pin, which sets the

dead time. As the value of R_DTincreases, the current sourced by the DT pin decreases. The DT pin current will

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be less than 10 µA when R_DT= 100 kΩ. For larger values of R_DT, TI recommends placing R_DTand a ceramic

capacitor, 2.2 nF or greater, as close to the DT pin as possible to achieve greater noise immunity and better

dead time matching between both channels.

The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed

dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may

also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a

dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs

will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it

does not affect the programmed dead time setting for normal operation. Various driver dead time logic operating

conditions are illustrated and explained in .

INA

INB

DT

OUTA

OUTB

A

B

C

D

E

F

Figure 8-4. Input and Output Logic Relationship With Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead

time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed

dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead

time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,

when INA goes high, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead

time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it

immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls

OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to

OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls

OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to

OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

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Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The UCC21530-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal

capability of the UCC21530-Q1 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used

as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With

integrated components, advanced protection features (UVLO, dead time, and enable) and optimized switching

performance; the UCC21530-Q1 enables designers to build smaller, more robust designs for enterprise,

telecom, automotive, and industrial applications with a faster time to market.

9.2 Typical Application

The circuit in Figure 9-1 shows a reference design with UCC21530-Q1 driving a typical half-bridge configuration

which could be used in several popular power converter topologies such as synchronous buck, synchronous

boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. This circuit uses two

supplies (or single-input-double-output power supply). Power supply V_A+determines the positive drive output

voltage and V_A–determines the negative turn-off voltage. The configuration for channel B is the same as

channel A.

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and

TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during

high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on

and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below

the threshold. This solution has two separate power supplies for each driver channel, so it provides flexibility

when setting the positive and negative rail voltages.

Figure 9-1. Typical Application Schematic with Dual Power Supplies

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9.2.1 Design Requirements

Table 9-1 lists reference design parameters for the example application: UCC21530-Q1 driving 1000-V SiC-

MOSFETs in a high side-low side configuration.

Table 9-1. UCC21530-Q1 Design Requirements

PARAMETER

VALUE

UNITS

Power transistor

C3M0065100K

–

V

VCC

5.0

15

VDD

VSS

V

–4

V

R_ON

2.2

0

Ω

R_OFF

Ω

Input signal amplitude

Switching frequency (f_s)

DC link voltage

3.3

100

600

V

kHz

V

9.2.2 Detailed Design Procedure

9.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)

the signal at the output. However, a small input R_IN-C_INfilter can be used to filter out the ringing introduced by

non-ideal layout or long PCB traces.

Such a filter should use an R_INin the range of 0 Ω to 100 Ω and a C_INbetween 10 pF and 100 pF. In the

example, an R_IN= 51 Ω and a C_IN= 33 pF are selected, with a corner frequency of approximately 100 MHz.

When selecting these components, it is important to pay attention to the trade-off between good noise immunity

and propagation delay.

9.2.2.2 Select Dead Time Resistor and Capacitor

From Equation 1, a 10-kΩ resistor is selected to set the dead time to 100 ns. A 2.2-nF capacitor is placed in

parallel close to the DT pin to improve noise immunity.

9.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, R_ON/R_OFF, are used to:

1. Limit ringing caused by parasitic inductances/capacitances.

2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.

3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.

4. Reduce electromagnetic interference (EMI).

As mentioned in Section 8.3.4, the UCC21530-Q1 has a pull-up structure with a P-channel MOSFET and an

additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak

source current can be predicted with:

(2)

where

•

R_ON: External turn-on resistance,R_ON=2.2 Ω in this example;.

R_{GFET_INT}: Power transistor internal gate resistance, found in the power transistor datasheet.

I_O+= Peak source current – The minimum value between 4 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

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In this example:

(3)

Therefore, the driver peak source current is 2.4 A for each channel. Similarly, the peak sink current can be

calculated with:

(4)

where

•

R_OFF: External turn-off resistance, R_OFF=0 in this example;

V_GDF: The anti-parallel diode forward voltage drop which is in series with R_OFF. The diode in this example is

an MSS1P4.

•

I_O-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated

value based on the gate drive loop resistance.

In this example,

(5)

Therefore, the driver peak sink current is 3.5 A for each channel.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other

hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C_ISS) of the

power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close

to the parasitic ringing period.

9.2.2.4 Estimate Gate Driver Power Loss

The total loss, P_G, in the gate driver subsystem includes the power losses of the UCC21530-Q1 (P_GD) and

the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not

included in P_Gand not discussed in this section.

P_GDis the key power loss which determines the thermal safety-related limits of the UCC21530-Q1, and it can be

estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well

as driver self-power consumption when operating with a certain switching frequency. P_GDQis measured on the

bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and

ambient temperature. Figure 6-4 shows the per output channel current consumption vs. operating frequency with

no load. In this example, V_VCCI= 5 V and V_VDD-V_VSS= 19 V. The current on each power supply, with INA/INB

switching from 0 V to 3.3 V at 100 kHz is measured to be I_VCCI≈ 2.5 mA, and I_VDDA= I_VDDB≈ 1.5 mA. Therefore,

the P_GDQcan be calculated with

(6)

The second component is switching operation loss, P_GDO, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_GSW

can be estimated with

,

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(7)

where

•

Q_Gis the gate charge of the power transistor.

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail

to the negative rail.

So, for this example application:

(8)

Q_Grepresents the total gate charge of the power transistor switching 600 V at 20 A, and is subject to change

with different testing conditions. The UCC21530-Q1 gate driver loss on the output stage, P_GDO, is part of P_GSW

.

P_GDOwill be equal to P_GSWif the external gate driver resistances are zero, and all the gate driver loss is

dissipated inside the UCC21530-Q1. If there are external turn-on and turn-off resistances, the total loss will

be distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the

pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A,

however, it will be non-linear if the source/sink current is saturated. Therefore, P_GDOis different in these two

scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

(9)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21530-Q1

gate driver loss can be estimated with:

(10)

Case 2 - Nonlinear Pull-Up/Down Resistor:

(11)

where

•

V_OUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be

simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load

capacitor. Then, the V_OUTA/B(t) waveform will be linear and the T_{R_Sys}and T_{F_Sys}can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the

P_GDOwill be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up

and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver

UCC21530-Q1, P_GD, is:

(12)

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which is equal to 103 mW in the design example.

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9.2.2.5 Estimating Junction Temperature

The junction temperature of the UCC21530-Q1 can be estimated with:

T_J= T_C+ Y_JTìP_GD

(13)

where

•

T_Jis the junction temperature.

T_Cis the UCC21530-Q1 case-top temperature measured with a thermocouple or some other instrument.

ψ_JTis the junction-to-top characterization parameter from the Section 6.4 table.

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_ΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

R_ΘJCcan only be used effectively when most of the thermal energy is released through the case, such as with

metal packages or when a heatsink is applied to an IC package. In all other cases, use of R_ΘJCwill inaccurately

estimate the true junction temperature. Ψ_JTis experimentally derived by assuming that the amount of energy

leaving through the top of the IC will be similar in both the testing environment and the application environment.

As long as the recommended layout guidelines are observed, junction temperature estimates can be made

accurately to within a few degrees Celsius. For more information, see the Section 9.1 and Semiconductor and IC

Package Thermal Metrics application report.

9.2.2.6 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is

recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC)

with sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an

MLCC will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only

500 nF when a DC bias of 15 V_DCis applied.

9.2.2.6.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total

current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for

this application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or

electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

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9.2.2.7 Other Application Example Circuits

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and

TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during

high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on

and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below

the threshold. Below are a few examples of implementing negative gate drive bias.

Instead of using two separate power for generating positive and negative drive voltage Figure 9-2 shows the

example with negative bias turn-off on the channel-A driver using a Zener diode on the isolated power supply

output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply, V_A, is equal to 19

V, the turn-off voltage will be –3.9 V and turn-on voltage will be 19 V -– 3.9 V ≈ 15 V. The channel-B driver circuit

is the same as channel-A, therefore, this configuration needs only one power supply for each driver channel, and

there will be steady state power consumption from R_Z.

Figure 9-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

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Figure 9-3 shows another example which uses bootstrap to provide power for the channel A, this solution

doesn't have negative rail voltage, it is only suitable for circuits with less ringing or the power device has high

threshold voltage.

Figure 9-3. Bootstrap Power Supply for the High Side Device

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The last example, shown in Figure 9-4, is a single power supply configuration and generates negative bias

through a Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply

and the bootstrap power supply can be used for the high side drive. This design requires the least cost and

design effort among the three solutions. However, this solution has limitations:

1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which

means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed

duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this

solution.

2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,

which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)

diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%

duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in

the other two example circuits.

Figure 9-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

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9.2.3 Application Curves

Figure 9-5shows a multiple pulses bench test circuit which uses L1 as the inductor load, and a group of control

pulses are generated to evaluate driver and SiC MOSFET switching transient under different load conditions.

The test conditions are: V_DC-Link= 600 V, VCC = 5 V, VDD = 15 V, VSS = –4 V, f_SW= 500 kHz, R_ON= 5.1 Ω,

R_OFF= 1.0 Ω. Figure 9-6 shows the turn on and turn off waveforms at around 20 A current

Channel 1 (Yellow): Gate-source voltage signal on the low side MOSFET.

Channel 2 (Blue): Gate-source voltage signal on the high side MOSFET.

Channel 3 (Pink): Drain-source voltage signal for the low side MOSFET.

Channel 4 (Green): Drain-source current signal for the low side MOSFET.

In Figure 9-6, the gate drive signals on the high and low power transistor have a 100-ns dead time, and both

signals are measured with >= 500 MHz bandwidth probes.

Figure 9-5. Bench Test Circuit with SiC MOSFET Switching

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Figure 9-6. SiC MOSFET Switching Waveforms

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Power Supply Recommendations

The recommended input supply voltage (VCCI) for UCC21530-Q1 is between 3 V and 18 V. The output bias

supply voltage (VDDA/VDDB) range depends on which version of UCC21530-Q1 one is using. The lower end

of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each

device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on

UVLO see Section 8.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of

the power device being driven by UCC21530-Q1. All versions of UCC21530-Q1 have a recommended maximum

VDDA/VDDB of 25 V.

A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned

as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further

suggested that one place two such capacitors: one with a value of between 220 nF and 10 µF for device biasing,

and an additional 100-nF capacitor in parallel for high frequency filtering.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of

current drawn by the logic circuitry within the input side of UCC21530-Q1, this bypass capacitor has a minimum

recommended value of 100 nF.

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9 Layout

9.1 Layout Guidelines

Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC21530-Q1.

9.1.1 Component Placement Considerations

•

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins

and between the VDD and VSS pins to support high peak currents when turning on the external power

transistor.

•

To avoid large negative transients on the switch node VSSA (HS) pin in bridge configurations, the parasitic

inductances between the source of the top transistor and the source of the bottom transistor must be

minimized.

•

To improve noise immunity when driving the EN pin from a distant micro-controller, TI recommends adding a

small bypass capacitor, ≥ 1 nF, between the EN pin and GND.

If the dead time feature is used, TI recommends placing the programming resistor R_DTand bypassing

capacitor close to the DT pin of the UCC21530-Q1 to prevent noise from unintentionally coupling to the

internal dead time circuit. The capacitor should be ≥ 2.2 nF.

9.1.2 Grounding Considerations

•

It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal

physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the

transistors. The gate driver must be placed as close as possible to the transistors.

•

Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-

referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor

is recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This

recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and

area on the circuit board is important for ensuring reliable operation.

9.1.3 High-Voltage Considerations

•

To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or

copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may

compromise the isolation performance.

•

For half-bridge or high-side/low-side configurations, maximize the clearance distance of the PCB layout

between the high and low-side PCB traces.

9.1.4 Thermal Considerations

•

A large amount of power may be dissipated by the UCC21530-Q1 if the driving voltage is high, the load is

heavy, or the switching frequency is high (refer to Section 9.2.2.4 for more details). Proper PCB layout can

help dissipate heat from the device to the PCB and minimize junction to board thermal impedance (θ_JB).

Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority

on maximizing the connection to VSSA and VSSB (see Figure 9-2 and Figure 9-3). However, high voltage

PCB considerations mentioned above must be maintained.

If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and

VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces

or copper from different high-voltage planes overlap.

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9.2 Layout Example

Figure 9-1shows a 2-layer PCB layout example with the signals and key components labeled.

Figure 9-1. Layout Example

Figure 9-2 and Figure 9-3 shows top and bottom layer traces and copper.

Note

There are no PCB traces or copper between the primary and secondary side, which ensures isolation

performance.

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the

creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node

VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

Figure 9-2. Top Layer Traces and Copper

Figure 9-3. Bottom Layer Traces and Copper

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Figure 9-4 and Figure 9-5 are 3D layout pictures with top view and bottom views.

Note

The location of the PCB cutout between the primary side and secondary sides, which ensures

isolation performance.

Figure 9-5. 3-D PCB Bottom View

Figure 9-4. 3-D PCB Top View

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

•

Isolation Glossary

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

10.3 Community Resources

10.4 Trademarks

All trademarks are the property of their respective owners.

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

DWK0014A

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SMALL OUTLINE INTEGRATED CIRCUIT

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

11X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

14X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4224374/A 06/2018

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DWK0014A

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

SYMM

14X (2)

1

14X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

14X (0.6)

SYMM

11X (1.27)

R0.05 TYP

9

8

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4224374/A 06/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DWK0014A

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

SYMM

14X (1.65)

14X (2)

1

16

14X (0.6)

SYMM

11X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4224374/A 06/2018

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

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型号：	UCC21530QDWKQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有用于 IGBT/SiC 的 EN 和 DT 引脚的汽车类 4A/6A、5.7kVRMS 隔离式双通道栅极驱动器 \| DWK \| 14 \| -40 to 125 栅极驱动双极性晶体管驱动器
文件：	总46页 (文件大小：2330K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21530QDWKQ1 [TI]

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