UCC21759QDWRQ1_技术文档

UCC21759-Q1

_{SLUSEB4A – AUGUST 2020 – REVISED}U_DC_ECC_E2_M1_B7_E5_R9₂-Q₀₂1₀

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

UCC21759-Q1 10-A Source/Sink Basic Isolated Single Channel Gate Driver

for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI

1 Features

3 Description

•

3-kV_RMSsingle channel isolated gate driver

AEC-Q100 qualified for automotive applications

Drives SiC MOSFETs and IGBTs up to 990V_pk

33-V maximum output drive voltage (VDD-VEE)

High peak drive current and high CMTI

±10-A drive strength and split output

150-V/ns minimum CMTI

200-ns response time fast DESAT protection

4-A internal active Miller clamp

400-mA soft turn-off under fault conditions

Isolated analog sensor with PWM output for

– Temperature sensing with NTC, PTC or thermal

diode

– High voltage DC-Link or phase voltage

Alarm FLT on over current and reset from RST/EN

Fast enable/disable response on RST/EN

Rejects <40-ns noise transients and pulses on

input pins

12-V VDD UVLO with power good on RDY

Inputs/outputs with over/under-shoot transient

voltage immunity up to 5 V

130-ns (maximum) propagation delay and 30-ns

(maximum) pulse/part skew

SOIC-16 DW package with creepage and

clearance distance > 8mm

The UCC21759-Q1 is a galvanic isolated single

channel gate driver designed for SiC MOSFETs and

IGBTs up to 990-V DC operating voltage with

advanced protection features, best-in-class dynamic

performance and robustness. UCC21759-Q1 has up

to ±10-A peak source and sink current.

The input side is isolated from the output side with

SiO₂capacitive isolation technology, supporting up to

700-V_RMSworking voltage with longer than 40 years

isolation barrier life, 6-kV_PKsurge immunity, as well as

providing low part-to-part skew, and >150-V/ns

common mode noise immunity (CMTI).

The UCC21759-Q1 includes the state-of-art protection

features, such as fast short circuit detection, fault

reporting, active Miller clamp, and input and output

side power supply UVLO optimized for SiC and IGBT

power transistors. The isolated analog to PWM sensor

can be utilized for easier temperature or voltage

sensing, further increasing the drivers' versatility and

simplifying the system design effort, size, and cost.

•

Device Information

PART

PACKAGE

BODY SIZE (NOM)

NUMBER⁽¹⁾

•

UCC21759-Q1

DW SOIC-16

10.3 mm × 7.5 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Operating junction temperature –40°C to +150°C

Safety-related certifications (Planned):

– 6000-V_PKbasic isolation per DIN V VDE

V0884-11: 2017-01

Device Pin Configuration

– 3-kV_RMSisolation for 1 minute per UL 1577

APWM

AIN

DESAT

COM

1

2

3

4

5

6

7

8

16

15

VCC

RST/EN

FLT

2 Applications

14

13

12

11

10

9

•

Traction inverter for EVs

On-board charger and charging pile

DC/DC converter for HEV/EVs

OUTH

VDD

RDY

INÅ

OUTL

CLMPI

VEE

IN+

GND

Not to scale

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Submit Document Feedback

1

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 4

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Power Ratings.............................................................6

6.6 Insulation Specifications............................................. 7

6.7 Safety-Related Certifications...................................... 8

6.8 Safety Limiting Values.................................................8

6.9 Electrical Characteristics.............................................9

6.10 Switching Characteristics........................................11

6.11 Insulation Characteristics Curves............................12

6.12 Typical Characteristics............................................13

7 Parameter Measurement Information..........................19

7.1 Propagation Delay.................................................... 19

7.2 Input Deglitch Filter...................................................20

7.3 Active Miller Clamp................................................... 21

7.4 Under Voltage Lockout (UVLO)................................ 22

7.5 Desaturation (DESAT) Protection............................. 24

8 Detailed Description......................................................26

8.1 Overview...................................................................26

8.2 Functional Block Diagram.........................................27

8.3 Feature Description...................................................27

8.4 Device Functional Modes..........................................34

9 Applications and Implementation................................35

9.1 Application Information............................................. 35

9.2 Typical Application.................................................... 35

10 Power Supply Recommendations..............................47

11 Layout...........................................................................48

11.1 Layout Guidelines................................................... 48

11.2 Layout Example...................................................... 49

12 Device and Documentation Support..........................50

12.1 Documentation Support.......................................... 50

12.2 Receiving Notification of Documentation Updates..50

12.3 Support Resources................................................. 50

12.4 Trademarks.............................................................50

12.5 Electrostatic Discharge Caution..............................50

12.6 Glossary..................................................................50

13 Mechanical, Packaging, and Orderable

Information.................................................................... 50

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (August 2020) to Revision A (December 2020)

Page

•

Corrected device pin configuration..................................................................................................................... 1

Specifications included for Isolated Temperature Sense and Monitor (AIN-APWM).......................................... 9

2

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

5 Pin Configuration and Functions

APWM

VCC

RST/EN

FLT

AIN

DESAT

COM

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OUTH

VDD

RDY

INÅ

OUTL

CLMPI

VEE

IN+

GND

Not to scale

UCC21759-Q1 DW SOIC (16) Top View

Submit Document Feedback

3

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. If not used, short

to COM

AIN

1

I

DESAT

COM

2

3

4

I

Desaturation current protection input. If not used, short to COM

Common ground reference, connecting to emitter pin for IGBT or source pin for SiC-MOSFET

Gate driver output pull up

P

O

OUTH

Positive supply rail for gate drive voltage, Bypassing a >220nF capacitor to COM to support specified gate

driver source peak current capability

VDD

5

6

7

P

O

OUTL

CLMPI

Gate driver output pull down

Internal active Miller clamp, connecting this pin directly to the gate of the power transistor. If not used, short

to VEE

Negative supply rail for gate drive voltage. Bypassing a >220nF capacitor to COM to support specified gate

driver sink peak current capability

VEE

8

P

GND

IN+

9

P

I

Input power supply and logic ground reference

Non-inverting gate driver control input

10

11

IN–

I

Inverting gate driver control input. If not used, short to GND

Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other

RDY signals

RDY

FLT

12

13

O

Active low fault alarm output upon over current or short circuit detection. FLT is in open drain configuration

and can be paralleled with other faults

The RST/EN serves two purposes:

1) Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to

low;

RST/EN

14

I

2) Resets the DESAT condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns.

A reset of signal FLT is asserted at the rising edge of terminal RST/EN.

For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The

FET is turned off by a general turn-off, if terminal EN is set to low.

VCC

15

16

P

Input power supply from 3V to 5.5V, bypassing a >100nF capacitor to GND

APWM

O

Isolated analog sensing PWM output. If not used, leave floating or tie a parallel capacitor to GND

(1) P = Power, G = Ground, I = Input, O = Output

4

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

MAX

6

UNIT

V

VCC

VDD

VEE

V_MAX

VCC – GND

VDD – COM

VEE – COM

VDD – VEE

–0.3

36

V

–17.5

0.3

V

–0.3

36

V

DC

GND–0.3

GND–5.0

COM–0.3

–0.3

VCC

VCC+5.0

VDD+0.3

5

V

IN+, IN–, RST/EN

Transient, less than 100 ns⁽²⁾

V

DESAT

AIN

Reference to COM

V

DC

VEE–0.3

VEE–5.0

GND–0.3

VDD

VDD+5.0

VCC

20

V

OUTH, OUTL , CLMPI

Transient, less than 100 ns⁽²⁾

V

RDY, FLT, APWM

V

I_FLT, I_RDY

I_APWM

T_J

FLT, and RDY pin input current

APWM pin output current

mA

°C

20

Junction temperature range

Storage temperature range

–40

–65

150

T_stg

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Values are verified by characterization on bench.

6.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

PARAMETER

VCC

MIN

MAX

5.5

UNIT

VCC–GND

VDD–COM

VDD–VEE

3.0

V

VDD

13

33

V_MAX

–

0.7×VCC

0

33

High level input voltage

Low level input voltage

VCC

0.3×VCC

4.5

IN+, IN–, RST/EN

Reference to GND

V

AIN

t_RST/EN

T_A

Reference to COM

0.6

V

Minimum pulse width that reset the fault

Ambient Temperature

800

ns

°C

–40

125

150

T_J

Junction temperature

–40

Submit Document Feedback

5

UCC21759-Q1

www.ti.com

UNIT

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

6.4 Thermal Information

DW (SOIC)

16

THERMAL METRIC⁽¹⁾

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

68.3

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

27.5

32.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

14.1

ψ_JB

32.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

Value

UNIT

P_D

Maximum power dissipation (both sides)

985

mW

Maximum power dissipation by

transmitter side

P_D1

VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/- = 5V, 150kHz,

50% Duty Cycle for 10nF load, T_a=25^oC

20

mW

Maximum power dissipation by receiver

side

P_D2

965

6

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

6.6 Insulation Specifications

PARAMETER

GENERAL

TEST CONDITIONS

VALUE

UNIT

CLR

CPG

External clearance⁽¹⁾

Shortest terminal-to-terminal distance through air

> 8

mm

Shortest terminal-to-terminal distance across the

package surface

External creepage⁽¹⁾

Minimum internal gap (Internal clearance) of the

double insulation (2 × 0.0085 mm)

DTI

CTI

Distance through the insulation

> 17

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664–1

> 600

I

Rated mains voltage ≤ 300 V_RMS

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage Category per IEC 60664–1

DIN V VDE V 0884-11 (VDE V 0884-11):2017-01⁽²⁾

V_IORMMaximum repetitive peak isolation voltage AC voltage (bipolar)

990

700

990

V_PK

V_RMS

V_DC

AC voltage (sine wave) Time dependent dielectric

breakdown (TDDB) test

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST=V_IOTM, t = 60 s (qualification test)

V_TEST=1.2 x V_IOTM, t = 1 s (100% production test)

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

4242

V_PK

Test method per IEC 62368-1, 1.2/50 µs waveform,

V_TEST= 1.6 × V_IOSM= 9600 V_PK(qualification)

V_IOSM

6000

≤ 5

Method a: After I/O safety test subgroup 2/3, V_ini

V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM, t_m= 10 s

=

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.6 × V_IORM, t_m

10 s

=

≤ 5

q_pd

Apparent charge⁽⁴⁾

pC

Method b1: At routine test (100% production) and

preconditioning (type test) V_ini= V_IOTM, t_ini= 1 s;

V_pd(m)= 1.875 × V_IORM= 3977 V_PK, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

V_IO= 0.5 sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

~ 1

≥ 10¹²

≥ 10¹¹

≥ 10⁹

pF

Ω

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 3000 V_RMS, t = 60 s (qualification);

V_TEST= 1.2 × V_ISO, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

3000

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the

printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques

such as inserting grooves and ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

Submit Document Feedback

7

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

6.7 Safety-Related Certifications

VDE

UL

Plan to certify according to DIN V VDE V 0884-11 (VDE V 0884-11):2017-01;

DIN EN 61010-1 (VDE 0411-1):2011-07

Plan to certify according to UL 1577 Component

Recognition Program

Maximum transient isolation voltage, 4242 V_PK

;

Maximum repetitive peak isolation voltage, 990 V_PK

Maximum surge isolation voltage, 6000 V_PK

;

Single protection, 3000 V_RMS

Certification Planned

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

R_θJA=68.3°C/W, V_DD= 15V, V_EE=-5V, T_J= 150°C, T_A=

25°C

61

Safety input, output, or supply

current

I_S

mA

49

R_θJA=68.3°C/W, V_DD= 20V, V_EE=-5V, T_J= 150°C, T_A=

25°C

R_θJA=68.3°C/W, V_DD= 20V, V_EE=-5V, T_J= 150°C, T_A=

25°C

P_S

T_S

Safety input, output, or total power

Safety temperature

1220

150

mW

°C

(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-

air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-

to-air thermal resistance in the Section 6.4 table is that of a device installed on a high-K test board for leaded surface-mount packages.

The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature

plus the power times the junction-to-air thermal resistance.

8

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

6.9 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD – COM = 20 V, 18 V or 15 V, COM – VEE = 0 V, 5 V, 8 V or 15

V, C_L= 100 pF, –40°C < T_J< 150°C (unless otherwise noted)^{(1) (2)}

.

PARAMETER

VCC UVLO THRESHOLD AND DELAY

V_{VCC_ON}

TEST CONDITIONS

MIN

TYP

MAX UNIT

2.55

2.35

2.7

2.5

0.2

10

2.85

V_{VCC_OFF}

V_{VCC_HYS}

t_VCCFIL

VCC–GND

2.65

V

VCC UVLO Deglitch time

VCC UVLO on delay to output

high

t_{VCC+ to OUT}

t_{VCC– to OUT}

t_{VCC+ to RDY}

t_{VCC– to RDY}

28

5

37.8

10

50

15

IN+ = VCC, IN– = GND

RST/EN = VCC

VCC UVLO off delay to output

low

µs

VCC UVLO on delay to RDY

high

30

5

37.8

10

50

15

VCC UVLO off delay to RDY low

VDD UVLO THRESHOLD AND DELAY

V_{VDD_ON}

10.5

9.9

12.0

10.7

0.8

5

12.8

11.8

V_{VDD_OFF}

V_{VDD_HYS}

t_VDDFIL

VDD–COM

V

VDD UVLO Deglitch time

VDD UVLO on delay to output

high

t_{VDD+ to OUT}

t_{VDD– to OUT}

t_{VDD+ to RDY}

t_{VDD– to RDY}

2

5

8

IN+ = VCC, IN– = GND

RST/EN = FLT=High

VDD UVLO off delay to output

low

10

µs

VDD UVLO on delay to RDY

high

10

15

VDD UVLO off delay to RDY low

VCC, VDD QUIESCENT CURRENT

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

2.5

1.45

3.6

3

2

4

2.75

5.9

I_VCCQ

VCC quiescent current

VDD quiescent current

mA

4

I_VDDQ

3.1

3.7

5.3

LOGIC INPUTS — IN+, IN– and RST/EN

V_INH

Input high threshold

Input low threshold

V_CC=3.3V

1.85

1.52

0.33

2.31

V

V_INL

0.99

V_INHYS

Input threshold hysteresis

Input high level input leakage

current

I_IH

V_IN= VCC

V_IN= GND

90

–90

55

µA

I_IL

Input low level input leakage

Input pins pull down resistance

see Section 8 for more

information

R_IND

kΩ

see Section 8 for more

information

R_INU

Input pins pull up resistance

55

IN+, IN– and RST/EN deglitch

(ON and OFF) filter time

T_INFIL

f_S= 50kHz

28

40

60

ns

T_RSTFIL

Deglitch filter time to reset /FLT

400

650

800

GATE DRIVER STAGE

I_OUT, I_OUTHPeak source current

I_OUT, I_OUTL

10

A

C_L=0.18µF, f_S=1kHz

Peak sink current

(3)

R_OUTH

Output pull-up resistance

Output pull-down resistance

High level output voltage

Low level output voltage

I_OUT= –0.1A

2.5

0.3

17.5

60

Ω

R_OUTL

V_OUTH

V_OUTL

I_OUT= 0.1A

Ω

I_OUT= –0.2A, V_DD=18V

I_OUT= 0.2A

V

mV

ACTIVE PULLDOWN

Submit Document Feedback

9

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD – COM = 20 V, 18 V or 15 V, COM – VEE = 0 V, 5 V, 8 V or 15

V, C_L= 100 pF, –40°C < T_J< 150°C (unless otherwise noted)^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output active pull down on OUT, I_OUTLor I_OUT= 0.1×I_OUT(L)(tpy)

,

V_OUTPD

1.5

2

2.5

V

OUTL

INTERNAL ACTIVE MILLER CLAMP

VDD=OPEN, VEE=COM

V_CLMPTH

V_CLMPI

I_CLMPI

Miller clamp threshold voltage

Output low clamp voltage

Output low clamp current

Reference to VEE

I_CLMPI= 1A

1.5

2.0

V

VEE + 0.5

V_CLMPI= 0V, VEE = –2.5V

4

0.6

15

A

R_CLMPI

t_DCLMPI

SHORT CIRCUIT CLAMPING

Miller clamp pull down resistance I_CLMPI= 0.2A

Ω

ns

Miller clamp ON delay time C_L= 1.8nF

50

OUT = Low, I_OUT(H)= 500mA,

t_CLP=10us

V_CLP-OUT(H)

V_CLP-OUT(L)

V_CLP-CLMPI

V_OUT–VDD, V_OUTH–VDD

0.9

1.8

1.0

0.99

1.98

V

OUT = High, I_OUT(L)= 500mA,

t_CLP=10us

V_OUT–VDD, V_OUTL–VDD

V_CLMPI–VDD

OUT = High, I_CLMPI= -20mA,

t_CLP=10us

DESAT PROTECTION

Blanking capacitor charge

current

I_CHG

V_DESAT= 2.0V

V_DESAT= 6.0V

450

500

15

570 µA

mA

Blanking capacitor discharge

current

I_DCHG

10

V_DESAT

Detection Threshold

Leading edge blank time

DESAT deglitch filter

8.5

9.15

200

140

9.8

V

t_DESATLEB

t_DESATFIL

ns

50

150

400

230

300

750

DESAT propagation delay to

OUT(L) 90%

t_DESATOFF

t_DESATFLT

200

580

ns

DESAT to FLT low delay

INTERNAL SOFT TURN-OFF

Soft turn-off current on fault

I_STO

250

400

570 mA

conditions

ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)

V_AIN

Analog sensing voltage range

Internal current source

0.5

196

380

4.5

V

I_AIN

V_AIN=2.5V, -40°C< T_J< 150°C

V_AIN=2.5V

203

400

10

209 µA

420 kHz

kHz

f_APWM

BW_AIN

APWM output frequency

AIN–APWM bandwidth

V_AIN= 0.6V

V_AIN= 2.5V

V_AIN= 4.5V

86.5

48.5

7.5

88

89.5

D_APWM

APWM Dutycycle

50

51.5

11.5

%

10

FLT AND RDY REPORTING

VDD UVLO RDY low minimum

holding time

t_RDYHLD

0.55

1

ms

t_FLTMUTE

R_ODON

V_ODL

Output mute time on fault

Reset fault through RST/EN

ms

Ω

Open drain output on resistance I_ODON= 5mA

Open drain low output voltage I_ODON= 5mA

30

0.3

V

COMMON MODE TRANSIENT IMMUNITY

Common-mode transient

immunity

CMTI

150

V/ns

(1) Current are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise notified.

(3) For internal PMOS only. Refer to Section 8.3.2 for effective pull-up resistance.

10

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

6.10 Switching Characteristics

VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, C_L=100pF, –

40°C<T_J<150°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

130

30

UNIT

ns

t_PDHL

t_PDLH

PWD

t_sk-pp

t_r

Propagation delay time – High to Low

Propagation delay time – Low to High

60

90

60

90

Pulse width distortion |t_PDHL– t_PDLH

Part to Part skew

|

Rising or Falling Propagation Delay

30

Driver output rise time

C_L=10nF

33

27

t_f

Driver output fall time

f_MAX

Maximum switching frequency

1

MHz

Submit Document Feedback

11

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

6.11 Insulation Characteristics Curves

80

1400

1200

1000

800

600

400

200

0

VDD=15V; VEE=-5V

VDD=20V; VEE=-5V

60

40

20

0

25

50

75

100

125

150

0

20

40

60

80

100

120

140

160

Ambient Temperature (^oC)

Safe

Figure 6-1. Thermal Derating Curve for Limiting

Current per VDE

Figure 6-2. Thermal Derating Curve for Limiting

Power per VDE

12

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

6.12 Typical Characteristics

22

20

18

16

14

12

10

8

22

20

18

16

14

12

10

8

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

6

4

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D016

D017

Figure 6-3. Output High Drive Current vs.

Temperature

Figure 6-4. Output Low Driver Current vs.

Temperature

6

4

VCC = 3.3V

VCC = 5V

VCC = 3.3V

VCC = 5V

5.5

3.5

5

4.5

4

3

2.5

2

3.5

3

1.5

1

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D015

D014

A.

IN+ = High

IN- = Low

IN+ = Low

IN- = Low

Figure 6-5. I_VCCQSupply Current vs. Temperature

Figure 6-6. I_VCCQSupply Current vs. Temperature

Submit Document Feedback

13

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

5

6

5.5

5

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

4.5

4

3.5

3

4.5

4

2.5

2

3.5

3

30

70

110

150 190

Frequency (kHz)

230

270

310

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D018

D012

A.

Figure 6-7. I_VCCQSupply Current vs. Input

Frequency

IN+ = High

IN- = Low

Figure 6-8. I_VDDQSupply Current vs. Temperature

6

10

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

9

8

7

6

5

4

3

2

5.5

5

4.5

4

3.5

3

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

30

70

110

150

190

Frequency (kHz)

230

270

310

D013

D019

A.

Figure 6-10. I_VDDQSupply Current vs. Input

Frequency

IN+ = Low

IN- = Low

Figure 6-9. I_VDDQSupply Current vs. Temperature

4

3.5

3

14

13.5

13

12.5

12

2.5

2

11.5

11

10.5

10

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D002

D001

Figure 6-12. VDD UVLO vs. Temperature

Figure 6-11. VCC UVLO vs. Temperature

14

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

100

90

80

70

60

50

90

80

70

60

50

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D022

D021

A.

V_CC= 3.3V

R_ON= 0Ω

V_DD=18V

C_L= 100pF

V_CC= 3.3V

R_ON= 0Ω

V_DD=18V

C_L= 100pF

R_OFF= 0Ω

Figure 6-14. Propagation Delay t_PDHLvs.

Temperature

Figure 6-13. Propagation Delay t_PDLHvs.

Temperature

60

50

40

30

20

10

50

40

30

20

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D023

D024

A.

V_CC= 3.3V

R_ON= 0Ω

V_DD=18V

C_L= 10nF

V_CC= 3.3V

R_ON= 0Ω

V_DD=18V

C_L= 10nF

R_OFF= 0Ω

Figure 6-15. t_rRise Time vs. Temperature

Figure 6-16. t_fFall Time vs. Temperature

Submit Document Feedback

15

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

2.5

2.25

2

3

2.75

2.5

1.75

1.5

1.25

1

2.25

2

1.75

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D025

Figure 6-18. V_CLP-OUT(H)Short Circuit Clamping

Voltage vs. Temperature

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D008

Figure 6-17. V_OUTPDOutput Active Pulldown

Voltage vs. Temperature

2

1.75

1.5

2.6

2.45

2.3

1.25

1

2.15

2

0.75

0.5

1.85

1.7

0.25

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

1.55

1.4

D026

Figure 6-19. V_CLP-OUT(L)Short Circuit Clamping

Voltage vs. Temperature

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D007

Figure 6-20. V_CLMPTHMiller Clamp Threshold

Voltage vs. Temperature

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

18

17

16

15

14

13

12

11

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D011

D010

Figure 6-21. I_CLMPIMiller Clamp Sink Current vs.

Temperature

Figure 6-22. t_DCLMPIMiller Clamp ON Delay Time

vs. Temperature

16

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

10

9.8

9.6

9.4

9.2

9

420

380

340

300

260

220

180

140

100

8.8

8.6

8.4

8.2

8

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D002

D001

Figure 6-24. t_DESATLEBDESAT Leading Edge

Blanking Time vs. Temperature

Figure 6-23. V_DESATDESAT Threshold Voltage vs.

Temperature

680

660

640

620

600

580

560

540

520

500

300

290

280

270

260

250

240

230

220

210

200

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D004

D003

Figure 6-26. t_DESATFLTDESAT Sense to /FLT Low

Delay Time vs. Temperature

Figure 6-25. t_DESATOFFDESAT Propagation Delay to

OUT(L) 90% vs. Temperature

320

310

300

290

280

270

260

250

240

230

220

560

550

540

530

520

510

500

490

480

470

460

450

440

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D005

D008

Figure 6-27. t_DESATFILDESAT Deglitch Filter vs.

Temperature

Figure 6-28. I_CHGDESAT Charging Current vs.

Temperature

Submit Document Feedback

17

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

20

19

18

17

16

15

14

13

12

11

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D009

Figure 6-29. I_DCHGDESAT Discharge Current vs. Temperature

18

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

7 Parameter Measurement Information

7.1 Propagation Delay

7.1.1 Non-Inverting and Inverting Propagation Delay

Figure 7-1 shows the propagation delay measurement for non-inverting configurations. Figure 7-2 shows the

propagation delay measurement with the inverting configurations.

50%

IN+

INÅ

t_PDLH

t_PDHL

90%

10%

OUT

Figure 7-1. Non-inverting Logic Propagation Delay Measurement

IN+

INÅ

50%

t_PDLH

t_PDHL

90%

OUT

10%

Figure 7-2. Inverting Logic Propagation Delay Measurement

Submit Document Feedback

19

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

7.2 Input Deglitch Filter

In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input

pins, i.e. IN+, IN–, RST/EN, a 40ns deglitch filter is designed to filter out the transients and make sure there is no

faulty output responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than the

input deglitch filter width, T_INFIL, there will be no responses on OUT drive signal. Figure 7-3 and Figure 7-4

shows the IN+ pin ON and OFF pulse deglitch filter effect. Figure 7-5 and Figure 7-6 shows the IN– pin ON and

OFF pulse deglitch filter effect.

IN+

t_PWM< T_INFIL

IN+

INÅ

OUT

Figure 7-3. IN+ ON Deglitch Filter

Figure 7-4. IN+ OFF Deglitch Filter

IN+

INÅ

t_PWM< T_INFIL

INÅ

OUT

Figure 7-5. IN– ON Deglitch Filter

Figure 7-6. IN– OFF Deglitch Filter

20

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

7.3 Active Miller Clamp

7.3.1 Internal On-chip Active Miller Clamp

For gate driver application with unipolar bias supply or bipolar supply with small negative turn-off voltage, active

Miller clamp can help add a additional low impedance path to bypass the Miller current and prevent the

unintentional turn-on through the Miller capacitance. Figure 7-7 shows the timing diagram for on-chip internal

Miller clamp function.

IN

(”IN+‘ Å ”INÅ‘)

t_DCLMPI

V_CLMPTH

OUT

HIGH

CLMPI

Ctrl.

LOW

Figure 7-7. Timing Diagram for Internal Active Miller Clamp Function

Submit Document Feedback

21

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

7.4 Under Voltage Lockout (UVLO)

UVLO is one of the key protection features designed to protect the system in case of bias supply failures on VCC

— primary side power supply, and VDD — secondary side power supply.

7.4.1 VCC UVLO

The VCC UVLO protection details are discussed in this section. Figure 7-8 shows the timing diagram illustrating

the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VCCFIL

t_{VCCÅ to OUT}

V_{VCC_ON}

VCC

V_{VCC_OFF}

VDD

COM

VEE

t_{VCC+ to OUT}

90%

V_CLMPTH

OUT

10%

t_{VCC+ to RDY}

t_RDYHLD

t_{VCCÅ to RDY}

Hi-Z

RDY

VCC

APWM

Figure 7-8. VCC UVLO Protection Timing Diagram

22

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

7.4.2 VDD UVLO

The VDD UVLO protection details are discussed in this section. Figure 7-9 shows the timing diagram illustrating

the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VDDFIL

VDD

t_{VDDÅ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

COM

VEE

VCC

t_{VDD+ to OUT}

V_CLMPTH

OUT

90%

t_RDYHLD

10%

t_{VDD+ to RDY}

t_{VDDÅ to RDY}

RDY

Hi-Z

VCC

APWM

Figure 7-9. VDD UVLO Protection Timing Diagram

Submit Document Feedback

23

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

7.5 Desaturation (DESAT) Protection

7.5.1 DESAT Protection with Soft Turn-OFF

DESAT function is used to detect V_DSfor SiC-MOSFETs or V_CEfor IGBTs under over current conditions. Figure

7-10 shows the timing diagram of DESAT operation with soft turn-off during the turning on transition.

IN

(”IN+‘ Å ”INÅ‘)

V_DESAT

t_DESATLEB

t_DESATFIL

DESAT

t_DESATOFF

90%

GATE

V_CLMPTH

t_DESATFLT

t_FLTMUTE

Hi-Z

FLT

t_RSTFIL

RST/EN

HIGH

Hi-Z

OUTH

OUTL

LOW

Hi-Z

LOW

Figure 7-10. DESAT Protection with Soft Turn-OFF During Turn-on Transition

24

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

Figure 7-11 shows the timing diagram of DESAT protection while the power device is already turned on.

IN

(”IN+‘ Å ”INÅ‘)

V_DESAT

t_DESATLEB

t_DESATFIL

DESAT

t_DESATOFF

90%

GATE

V_CLMPTH

t_DESATFLT

t_FLTMUTE

Hi-Z

FLT

t_RSTFIL

RST/EN

HIGH

Hi-Z

OUTH

OUTL

LOW

Hi-Z

LOW

Figure 7-11. DESAT Protection with Soft Turn-OFF While Power Device is ON

Submit Document Feedback

25

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

8 Detailed Description

8.1 Overview

The UCC21759-Q1 device is an advanced isolated gate driver with state-of-art protection and sensing features

for SiC MOSFETs and IGBTs. The device can support up to 990V DC operating voltage based on SiC MOSFETs

and IGBTs, and can be used to above 10kW applications such as HEV/EV traction inverter, motor drive, on-

board and off-board battery charger, solar inverter, etc. The galvanic isolation is implemented by the capacitive

isolation technology, which can realize a reliable basic isolation between the low voltage DSP/MCU and high

voltage side.

The ±10A peak sink and source current of UCC21759-Q1 can drive the SiC MOSFET modules and IGBT

modules directly without an extra buffer. The driver can also be used to drive higher power modules or parallel

modules with external buffer stage. The device can support up to 700-V_RMSworking voltage with longer than 40

years isolation barrier life, 6-kV_PKsurge immunity. The strong drive strength helps to switch the device fast and

reduce the switching loss, and the 150V/ns minimum CMTI guarantees the reliability of the system with fast

switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting, so the

conduction loss can be reduced.

The device includes extensive protection and monitor features to increase the reliability and robustness of the

SiC MOSFET and IGBT based systems. The 12V output side power supply UVLO is suitable for switches with

gate voltage ≥ 15V. The active Miller clamp feature prevents the false turn on causing by Miller capacitance

during fast switching. The device has the state-of-art DESAT detection time, and fault reporting function to the

low voltage side DSP/MCU. The soft turn off is triggered when the DESAT fault is detected, minimizing the short

circuit energy while reducing the overshoot voltage on the switches.

The isolated analog to PWM sensor can be used as switch temperature sensing, DC bus voltage sensing,

auxiliary power supply sensing, etc. The PWM signal can be fed directly to DSP/MCU or through a low-pass-filter

as an analog signal.

26

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

8.2 Functional Block Diagram

CLMPI

OUTH

7

4

6

10

11

15

9

IN+

INt

55kQ

PWM Inputs

MOD

DEMOD

Output Stage

t

ON/OFF Control

STO

VCC

OUTL

VDD

VCC

UVLO

VCC Supply

5

GND

RDY

UVLO

LDO[s for VEE,

COM and channel

3

8

COM

VEE

12

13

14

16

Fault Decode

FLT

DESAT Protection

Analog 2 PWM

2

DESAT

Fault Encode

RST/EN

50kQ

PWM Driver

AIN

1

APWM

DEMOD

MOD

8.3 Feature Description

8.3.1 Power Supply

The input side power supply VCC can support a wide voltage range from 3V to 5.5V. The device supports both

unipolar and bipolar power supply on the output side, with a wide range from 13V to 33V from VDD to VEE. The

negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the

other switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to

its fast switching speed.

8.3.2 Driver Stage

UCC21759-Q1 has ±10A peak drive strength and is suitable for high power applications. The high drive strength

can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage.

UCC21759-Q1 can also be used to drive higher power modules or parallel modules with extra buffer stage.

Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an

important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW

Submit Document Feedback

27

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

state. The split output of the driver stage is depicted in Figure 8-1. The driver has rail-to-rail output by

implementing a hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and

an N-Channel MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on

resistance R_NMOSis the same as R_OL. The hybrid pull-up structure delivers the highest peak-source current

when it is most needed, during the Miller plateau region of the power semiconductor turn-on transient. The R_OH

in represents the on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is

much smaller than R_OH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the P-

Channel MOSFET, the pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on

OUTH pin is about 3V below VDD voltage. The effective resistance of the hybrid pull-up structure during this

period is about 2 x R_OL. Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up

impedance results in strong drive strength during the turn-on transient, which shortens the charging time of the

input capacitance of the power semiconductor and reduces the turn on switching loss.

The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. This

MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pull-down impedance not only

results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering

the Miller effect.

VDD

R_OH

R_NMOS

OUTH

Input

Signal

Anti Shoot-

through

Circuitry

OUTL

R_OL

Figure 8-1. Gate Driver Output Stage

8.3.3 VCC and VDD Undervoltage Lockout (UVLO)

UCC21759-Q1 implements the internal UVLO protection feature for both input and output power supplies VCC

and VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The

output only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not

only reduces the power consumption of the driver itself during low power supply voltage condition, but also

increases the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the

gate-source voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD

value, the conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the

power stage. UCC21759-Q1 implements 12V threshold voltage of VDD UVLO, with 800mV hysteresis. This

threshold voltage is suitable for both SiC MOSFET and IGBT.

The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity

of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak

transient current from the power supply, which can result in sudden voltage drop of the power supply. With

28

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal

switching transients.

The timing diagrams of the UVLO feature of VCC and VDD are shown in Figure 7-8, and Figure 7-9. The RDY

pin on the input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO

condition, the RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to

VCC to indicate the power good. The AIN-APWM function stops working during the UVLO status. The APWM

pin on the input side will be held LOW.

8.3.4 Active Pulldown

UCC21759-Q1 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the

VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature

can prevent the output be false turned on before the device is back to control.

VDD

OUTL

R_a

Control

Circuit

VEE

COM

Figure 8-2. Active Pulldown

8.3.5 Short Circuit Clamping

During short circuit condition, the Miller capacitance can cause a current sinking to the OUTH/OUTL/CLMPI pin

due to the high dV/dt and boost the OUTH/OUTL/CLMPI voltage. The short circuit clamping feature of

UCC21759-Q1 can clamp the OUTH/OUTL/CLMPI pin voltage to be slightly higher than VDD, which can protect

the power semiconductors from a gate-source and gate-emitter overvoltage breakdown. This feature is realized

by an internal diode from the OUTH/OUTL/CLMPI to VDD.

Submit Document Feedback

29

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

VDD

D₁D₂D₃

OUTH

Control

Circuitry

OUTL

CLMPI

Figure 8-3. Short Circuit Clamping

8.3.6 Internal Active Miller Clamp

Active Miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In

applications which the device can be in synchronous rectifier mode, the body diode conducts the current during

the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same

and the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-

down impedance of UCC21759-Q1 can provide a strong pulldown to hold the OUTL to VEE. However, external

gate resistance is usually adopted to limit the dV/dt. The Miller effect during the turn on transient of the other

power semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source or

gate-emitter voltage. If the voltage on V_GSor V_GEis higher than the threshold voltage of the power

semiconductor, a shoot through can happen and cause catastrophic damage. The active Miller clamp feature of

UCC21759-Q1 drives an internal MOSFET, which connects to the device gate. The MOSFET is triggered when

the gate voltage is lower than V_CLMPTH, which is 2V above VEE, and creates a low impedance path to avoid the

false turn on issue.

V_CLMPTH

VCC

OUTH

+

3V to 5.5V

IN+

œ

CLMPI

OUTL

Control

Circuitry

µC

MOD

DEMOD

IN-

VEE

COM

VCC

Figure 8-4. Active Miller Clamp

30

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

8.3.7 Desaturation (DESAT) Protection

The UCC21759-Q1 implements a fast overcurrent and short circuit protection feature to protect the IGBT module

from catastrophic breakdown during fault. The DESAT pin of the device has a typical 9V threshold with respect

to COM, source or emitter of the power semiconductor. When the input is in floating condition, or the output is

held in low state, the DESAT pin is pulled down by an internal MOSFET and held in LOW state, which prevents

the overcurrent and short circuit fault from false triggering. The internal current source of the DESAT pin is

activated only during the driver ON state, which means the overcurrent and short circuit protection feature only

works when the power semiconductor is in on state. The internal pulldown MOSFET helps to discharge the

voltage of DESAT pin when the power semiconductor is turned off. UCC21759-Q1 features a 200ns internal

leading edge blanking time after the OUTH switches to high state. The internal current source is activated to

charge the external blanking capacitor after the internal leading edge blanking time. The typical value of the

internal current source is 500µA.

VDD

DESAT

D_HV

R

+

DESAT Fault

C_BLK

+

V_DESAT

œ

Control

Logic

COM

Figure 8-5. DESAT Protection

8.3.8 Soft Turn-off

UCC21759-Q1 initiates a soft turn-off when the overcurrent and short circuit protection is triggered. When the

overcurrent and short circuit fault happens, the IGBT transits from the active region to the desaturation region

very fast. The channel current is controlled by the gate voltage and decreasing in a soft manner, thus the

overshoot of the IGBT is limited and prevents the overvoltage breakdown. There is a tradeoff between the

overshoot voltage and short circuit energy. The turn off speed needs to be slow to limit the overshoot voltage,

but the shutdown time should not be too long that the large energy dissipation can breakdown the device. The

400mA soft turn off current of UCC21759-Q1 makes sure the power switches is safely turned off during short

circuit events. The timing diagram of soft turn-off shows in Figure 7-10.

Submit Document Feedback

31

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

VDD

DESAT

R

D_HV

+

C_BLK

+

V_DESAT

œ

Control

Logic

COM

OUTL

Soft Turn-off

VEE

Figure 8-6. Soft Turn-off

8.3.9 Fault ( FLT, Reset and Enable ( RST/EN)

The FLT pin of UCC21759-Q1 is open drain and can report a fault signal to the DSP/MCU when the fault is

detected through the DESAT pin. The FLT pin will be pulled down to GND after the fault is detected, and is held

low until a reset signal is received from RST/EN. The device has a fault mute time t_FLTMUTE, within which the

device ignores any reset signal.

The RST/EN is pulled down internally by a 50kΩ resistor, and is thus disabled by default when this pin is floating.

It must be pulled up externally to enable the driver. The pin has two purposes:

•

To reset the FLT pin. To reset, then RST/EN pin is pulled low; if the pin is set and held in low state for more

than t_RSTFILafter the mute time t_FLTMUTE, then the fault signal is reset and FLT is reset back to the high

impedance status at the rising edge of the input signal at RST/EN pin.

•

Enable and shutdown the device. If the RST/EN pin is pulled low for longer than t_RSTFIL, the driver will be

disabled and OUTL will be activated to pull down the gate of the IGBT or SiC MOSFET. The pin must be

pulled up externally to enable the part, otherwise the device is disabled by default.

8.3.10 Isolated Analog to PWM Signal Function

The UCC21759-Q1 features an isolated analog to PWM signal function from AIN to APWM pin, which allows the

isolated temperature sensing, high voltage dc bus voltage sensing, etc. An internal current source I_AINin AIN pin

is implemented in the device to bias an external thermal diode or temperature sensing resistor. The UCC21759-

Q1 encodes the voltage signal V_AINto a PWM signal, passing through the basic isolation barrier, and output to

APWM pin on the input side. The PWM signal can either be transferred directly to DSP/MCU to calculate the

duty cycle, or filtered by a simple RC filter as an analog signal. The AIN voltage input range is from 0.6V to 4.5V,

and the corresponding duty cycle of the APWM output ranges from 88% to 10%. The duty cycle increases

linearly from 10% to 88% while the AIN voltage decreases from 4.5V to 0.6V. This corresponds to the

temperature coefficient of the negative temperature coefficient (NTC) resistor and thermal diode. When AIN is

32

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

floating, the AIN voltage is 5V and the APWM operates at 400kHz with approximately 10% duty cycle. The duty

cycle absolute error is ±1.5% at 0.6V and 2.5V, and is +1.5% / -2.5% at 4.5V across process and temperature.

The in-system accuracy can be improved using calibration. The accuracy of the internal current source I_AINis

±3% across temperature.

The isolated analog to PWM signal feature can also support other analog signal sensing, such as the high

voltage dc bus voltage, etc. The internal current source I_AINshould be taken into account when designing the

potential divider if sensing a high voltage.

UCC217xx

In Module or

Discrete

VCC

VDD

13V to

33V

+

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

Figure 8-7. Isolated Analog to PWM Signal

Submit Document Feedback

33

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

8.4 Device Functional Modes

Table 8-1 lists the device function.

Table 8-1. Function Table

Input

Output

OUTH/

OUTL

VCC

VDD

VEE

IN+

IN-

RST/EN

AIN

RDY

FLT

CLMPI

APWM

PU

PD

PU

PD

PU

X

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

P^*

PU

X

Low

X

Open

PU

X

Open

PU

X

Low

PU

Low

X

High

PU

High

P^*

PU

High

P^*

PU: Power Up (VCC ≥ 2.85V, VDD ≥ 13.1V, VEE ≤ 0V); PD: Power Down (VCC ≤ 2.35V, VDD ≤ 9.9V); X:

Irrelevant; P^*: PWM Pulse; HiZ: High Impedance

34

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

9 Applications and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The UCC21759-Q1 device is very versatile because of the strong drive strength, wide range of output power

supply, high isolation ratings, high CMTI, and superior protection and sensing features. The 700-VRMS working

voltage and 6-kV_PKsurge immunity can support up both SiC MOSFET and IGBT modules with DC bus voltage

up to 990V. The device can be used in both low power and high power applications such as the traction inverter

in HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies and etc.

The device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device directly

without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows

the driver to have more control to the power semiconductor and saves the cost and space of the board design.

UCC21759-Q1 can also be used to drive very high power modules or paralleled modules with external buffer

stage. The input side can support power supply and microcontroller signal from 3.3V to 5V, and the device level

shifts the signal to output side through basic isolation barrier. The device has wide output power supply range

from 13V to 33V and support wide range of negative power supply. This allows the driver to be used in SiC

MOSFET applications, IGBT application and many others. The 12V UVLO benefits the power semiconductor

with lower conduction loss and improves the system efficiency. As a basic isolated single channel driver, the

device can be used to drive either a low-side or high-side driver.

UCC21759-Q1 device features extensive protection and monitoring features, which can monitor, report and

protect the system from various fault conditions.

•

Fast detection and protection for the overcurrent and short circuit fault. The semiconductor is shutdown when

the fault is detected and FLT pin is pulled down to indicate the fault detection. The device is latched unless

reset signal is received from the RST/EN pin.

Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and

short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is

limited.

UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to

be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is

back to normal operation mode once the power supply is out of the UVLO status. The power good status can

be monitored from the RDY pin.

•

Analog signal seensing with isolated analog to PWM signal feature. This feature allows the device to sense

the temperature of the semiconductor from the thermal diode or temperature sensing resistor, or dc bus

voltage with resistor divider. A PWM signal is generated on the low voltage side with basic isolated from the

high voltage side. The signal can be fed back to the microcontroller for the temperature monitoring, voltage

monitoring and etc.

•

The active Miller clamp feature protects the power semiconductor from false turn on.

Enable and disable function through the RST/EN pin.

Short circuit clamping.

Active pulldown.

9.2 Typical Application

Figure 9-1 shows the typical application of a half bridge using two UCC21759-Q1 isolated gate drivers. The half

bridge is a basic element in various power electronics applications such as traction inverter in HEV/EV to convert

the DC current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion

system. The topology can also be used in motor drive applications to control the operating speed and torque of

the AC motors.

Submit Document Feedback

35

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

Figure 9-1. Typical Application Schematic

9.2.1 Design Requirements

The design of the power system for end equipment should consider some design requirements to ensure the

reliable operation of UCC21759-Q1 through the load range. The design considerations include the peak source

and sink current, power dissipation, overcurrent and short circuit protection, AIN-APWM function for analog

signal sensing and etc.

A design example for a half bridge based on IGBT is given in this subsection. The design parameters are show

in Table 9-1.

Table 9-1. Design Parameters

Parameter

Input Supply Voltage

IN-OUT Configuration

Positive Output Voltage VDD

Negative Output Voltage VEE

DC Bus Voltage

Value

5V

Non-inverting

15V

-5V

800V

Peak Drain Current

Switching Frequency

Switch Type

300A

50kHz

IGBT Module

9.2.2 Detailed Design Procedure

9.2.2.1 Input filters for IN+, IN- and RST/EN

In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With

the strong drive strength of UCC21759-Q1, the dV/dt can be high, especially for SiC MOSFET. Noise can not

36

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

only be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal

PCB layout and coupled capacitance.

UCC21759-Q1 features a 40ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40ns can

be filtered out from the input pins. For noisy systems, external low pass filter can be added externally to the input

pins. Adding low pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and

increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should be

tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low pass filter is

to filter out the high frequency noise generated by the layout parasitics. While choosing the low pass filter

resistors and capacitors, both the noise immunity effect and delay time should be considered according to the

system requirements.

9.2.2.2 PWM Interlock of IN+ and IN-

UCC21759-Q1 features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg

shoot through issue. As shown in Table 8-1, the output is logic low while both IN+ and IN- are logic high. When

only IN+ is used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other

switch in the phase leg can be sent to the IN- pin. As shown in Figure 9-2, the PWM_T is the PWM signal to top

side switch, the PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal

is given to the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the

PWM_B signal is given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and

PWM_B signals are high, the outputs of both gate drivers are logic low to prevent the shoot through condition.

IN+

IN-

R_ON

OUTH

OUTL

R_OFF

PWM_T

PWM_B

R_ON

IN+

IN-

OUTH

OUTL

R_OFF

Figure 9-2. PWM Interlock for a Half Bridge

9.2.2.3 FLT, RDY and RST/EN Pin Circuitry

Both FLT and RDY pin are open-drain output. The RST/EN pin has 50kΩ internal pulldown resistor, so the driver

is in OFF status if the RST/EN pin is not pulled up externally. A 5kΩ resistor can be used as pullup resistor for

the FLT, RDY and RST/EN pins.

To improve the noise immunity due to the parasitic coupling and common mode noise, low pass filters can be

added between the FLT, RDY and RST/EN pins and the microcontroller. A filter capacitor between 100pF to

300pF can be added.

Submit Document Feedback

37

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

3.3V to 5V

VCC

15

9

1µF

0.1µF

GND

IN+

10

INt

11

5kQ

5kQ 5kQ

FLT

12

13

100pF

RDY

100pF

RST/EN

14

16

100pF

APWM

Figure 9-3. FLT, RDY and RST/EN Pins Circuitry

9.2.2.4 RST/EN Pin Control

RST/EN pin has two functions. It is used to enable or shutdown the outputs of the driver and to reset the fault

signaled on the FLT pin after DESAT is detected. RST/EN pin needs to be pulled up to enable the device; when

the pin is pulled down, the device is in disabled status. By default the driver is disabled with the internal 50kΩ

pulldown resistor at this pin.

When the driver is latched after DESAT is detected, the FLT pin and output are latched low and need to be reset

by the RST/EN pin. The microcontroller must send a signal to RST/EN pin after the fault to reset the driver. The

driver will not respond until after the mute time t_FLTMUTE. The reset signal must be held low for at least t_RSTFIL

after the mute time.

This pin can also be used to automatically reset the driver. The continuous input signal IN+ or IN- can be applied

to RST/EN pin. There is no separate reset signal from the microcontroller when configuring the driver this way. If

the PWM is applied to the non-inverting input IN+, then IN+ can also be tied to RST/EN pin. If the PWM is

applied to the inverting input IN-, then a NOT logic is needed between the PWM signal from the microcontroller

and the RST/EN pin. Using either configuration results in the driver being reset in every switching cycle without

an extra control signal from microcontroller tied to RST/EN pin. One must ensure the PWM off-time is greater

than t_RSTFILin order to reset the driver in cause of a DESAT fault.

38

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

3.3V to 5V

0.1µF

3.3V to 5V

VCC

15

1µF

0.1µF

GND

IN+

GND

IN+

9

10

INt

5kQ

11

5kQ

11

5kQ

FLT

12

13

12

13

100pF

RDY

RST/EN

APWM

RST/EN

APWM

14

16

14

16

Figure 9-4. Automatic Reset Control

9.2.2.5 Turn on and turn off gate resistors

UCC21759-Q1 features split outputs OUTH and OUTL, which enables the independent control of the turn on

and turn off switching speed. The turn on and turn off resistance determine the peak source and sink current,

which controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be

considered to ensure the device is in the thermal limit. At first, the peak source and sink current are calculated

as:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

)

VDD - VEE

R_OL+R_OFF+R_{G _Int}

I_{sink _ pk}= min(10A,

)

(1)

Where

•

R_{OH_EFF}is the effective internal pull up resistance of the hybrid pull-up structure, shown in Figure 8-1, which

is approximately 2 x R_OL, about 0.7 Ω. This is the dominant resistance during the switching transient of the

pull up structure.

•

R_OLis the internal pulldown resistance, about 0.3 Ω

R_ONis the external turn on gate resistance

R_OFFis the external turn off gate resistance

R_{G_Int}is the internal resistance of the SiC MOSFET or IGBT module

Submit Document Feedback

39

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

VDD

C_ies=C_gc+C_ge

+

C_gc

VDD

R_{OH_EFF}

OUTH

t

R_ON

R_{G_Int}

OUTL

R_OFF

C_ge

+

VEE

R_OL

t

VEE

COM

Figure 9-5. Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:

•

Q_g= 3300 nC

R_{G_Int}= 1.7 Ω

R_ON=R_OFF= 1 Ω

The peak source and sink current in this case are:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

) ö 5.9A

VDD - VEE

R_OL+R_OFF+R_{G _Int}

I_{sink _ pk}= min(10A,

) ö 6.7A

(2)

Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The

collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the Miller

plateau voltage. The hybrid pullup structure ensures the peak source current at the Miller plateau voltage, unless

the turn on gate resistor is too high. The faster the collector-to-emitter, V_ce, voltage rises to V_DC, the smaller the

turn on switching loss is. The dV/dt can be estimated as Q_gc/I_{source_pk}. For the turn off switching transient, the

drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After V_ce

reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled

by V_ge. The peak sink current determines the dI/dt, which dominates the V_cevoltage overshoot accordingly. If

using relatively large turn off gate resistance, the V_ceovershoot can be limited. The overshoot can be estimated

by:

DV = L_stray∂I_load/ ((R_OFF+R_OL+R_{G_Int})∂C_ies∂ln(V_plat/ V ))

ce

th

(3)

Where

•

L_strayis the stray inductance in power switching loop, as shown in Figure 9-6

I_loadis the load current, which is the turn off current of the power semiconductor

C_iesis the input capacitance of the power semiconductor

V_platis the plateau voltage of the power semiconductor

V_this the threshold voltage of the power semiconductor

40

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

L_DC

L_c1

L_stray=L_DC+L_e1+L_c1+L_e1+L_c1

R_G

L_load

t

+

L_e1

+

VDC

t

L_c2

VDD

C_gc

C_ies=C_gc+C_ge

R_G

OUTH

OUTL

COM

C_ge

L_e2

Figure 9-6. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The

power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

P

= P_Q+P

DR

SW

(4)

P_Qis the quiescent power loss for the driver, which is I_qx (VDD-VEE) = 5mA x 20V = 0.100W. The quiescent

power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic

circuits, protection circuits when the driver is swithing when the driver is biased with VDD and VEE, and also the

charging and discharing current of the internal circuit when the driver is switching. The power dissipation when

the driver is switching can be calculated as:

R_{OH_EFF}

2 R_{OH_EFF}+R_ON+R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g

SW

(5)

Where

•

Q_gis the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD

f_swis the switching frequency

In this example, the P_SWcan be calculated as:

Submit Document Feedback

41

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

R_{OH_EFF}

2 R_{OH_EFF}+ R_ON+ R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g= 0.505W

SW

(6)

Thus, the total power loss is:

P =P +P = 0.10W +0.505W = 0.605W

DR

Q

SW

(7)

When the board temperature is 125°C, the junction temperature can be estimated as:

T_j= T + y_jb∂P ö 150^oC

b

DR

(8)

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency

is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing

external gate resistance, the gate driver can be operated at a higher switching frequency.

9.2.2.6 Desaturation (DESAT) Protection

A standard desaturation circuit can be applied to the DESAT pin. If the voltage of the DESAT pin is higher than

the threshold V_DESAT, the soft turn-off is initiated. A fault will be reported to the input side to DSP/MCU. The

output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin. The state-of-art

overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC MOSFET and IGBT.

If DESAT pin is not in use, it must be tied to COM to avoid overcurrent fault false triggering.

•

Fast reverse recovery high voltage diode is recommended in the desaturation circuit. A resistor is

recommended in series with the high voltage diode to limit the inrush current. Multiple high voltage diodes

can be placed in series to reduce the DESAT detection voltage as seen by the IGBT or SiC MOSFET based

on the forward voltage drop.

•

A Schottky diode is recommended from COM to DESAT to prevent driver damage caused by negative

voltage.

A Zener diode is recommended from COM to DESAT to prevent driver damage caused by positive voltage.

9.2.2.7 Isolated Analog Signal Sensing

The isolated analog signal sensing feature provides a simple isolated channel for the isolated temperature

detection, voltage sensing and etc. One typical application of this function is the temperature monitor of the

power semiconductor. Thermal diodes or temperature sensing resistors are integrated in the SiC MOSFET or

IGBT module close to the dies to monitor the junction temperature. UCC21759-Q1 has an internal 200uA current

source with ±3% accuracy across temperature, which can forward bias the thermal diodes or create a voltage

drop on the temperature sensing resistors. The sensed voltage from the AIN pin is passed through the isolation

barrier to the input side and transformed to a PWM signal. The duty cycle of the PWM changes linearly from

10% to 88% when the AIN voltage changes from 4.5V to 0.6V and can be represented using Equation 9.

D_APWM(%) = -20 * V_AIN+100

(9)

9.2.2.7.1 Isolated Temperature Sensing

A typical application circuit is shown in Figure 9-7. To sense temperature, the AIN pin is connected to the thermal

diode or thermistor which can be discrete or integrated within the power module. A low pass filter is

recommended for the AIN input. Since the temperature signal does not have a high bandwidth, the low pass

filter is mainly used for filtering the noise introduced by the switching of the power device, which does not require

stringent control for propagation delay. The filter capacitance for C_filtcan be chosen between 1nF to 100nF and

the filter resistance R_filtbetween 1Ω to 10Ω according to the noise level.

The output of APWM is directly connected to the microcontroller to measure the duty cycle dependent on the

voltage input at AIN, using Equation 9.

42

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

UCC217xx

In Module or

Discrete

VCC

VDD

13V to

33V

+

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

Figure 9-7. Thermal Diode or Thermistor Temperature Sensing Configuration

When a high-precision voltage supply for VCC is used on the primary side of UCC21759-Q1 the duty cycle

output of APWM may also be filtered and the voltage measured using the microcontroller's ADC input pin, as

shown in Figure 9-8. The frequency of APWM is 400kHz, so the value for R_{filt_2}and C_{filt_2}should be such that

the cutoff frequency is below 400kHz. Temperature does not change rapidly, thus the rise time due to the RC

constant of the filter is not under a strict requirement.

UCC217xx

VDD

In Module or

Discrete

VCC

13V to

33V

+

œ

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_{filt_1}

R_{filt_2}

C_{filt_2}

GND

OSC

C_{filt_1}

COM

Thermal

Diode

NTC or

PTC

Figure 9-8. APWM Channel with Filtered Output

The example below shows the results using a 4.7kΩ NTC, NTCS0805E3472FMT, in series with a 3kΩ resistor

and also the thermal diode using four diode-connected MMBT3904 NPN transistors. The sensed voltage of the 4

MMBT3904 thermal diodes connected in series ranges from about 2.5V to 1.6V from 25°C to 135°C,

corresponding to 50% to 68% duty cycle. The sensed voltage of the NTC thermistor connected in series with the

3kΩ resistor ranges from about 1.5V to 0.6V from 25°C to 135°C, corresponding to 70% to 88% duty cycle. The

voltage at VAIN of both sensors and the corresponding measured duty cycle at APWM is shown in Figure 9-9.

Submit Document Feedback

43

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

90

84

78

72

66

60

54

Thermal Diode V_AIN

NTC V_AIN

Thermal Diode APWM

NTC APWM

48

20

40

60

80

Temperature (èC)

100

120

140

VAIN

Figure 9-9. Thermal diode and NTC V_AINand Corresponding Duty Cycle at APWM

The duty cycle output has 3% variation throughout temperature without any calibration from 0.6V to 2.5V at

VAIN, as shown in Figure 9-10 but with single-point calibration at 25°C, the duty accuracy can be improved to

1%, as shown in Figure 9-11.

1.5

Thermal Diode APWM Duty Error

NTC APWM Duty Error

1.25

1

0.75

0.5

0.25

0

-0.25

20

40

60

80

Temperature (èC)

100

120

140

APWM

Figure 9-10. APWM Duty Error Without Calibration

44

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

0.8

Thermal Diode APWM Duty Error

NTC APWM Duty Error

0.6

0.4

0.2

0

-0.2

20

40

60

80

Temperature (èC)

100

120

140

APWM

Figure 9-11. APWM Duty Error with Single-Point Calibration

9.2.2.7.2 Isolated DC Bus Voltage Sensing

The AIN to APWM channel may be used for other applications such as the DC-link voltage sensing, as shown in

Figure 9-12. The same filtering requirements as given above may be used in this case, as well. The number of

attenuation resistors, R_{atten_1}through R_{atten_n}, is dependent on the voltage level and power rating of the resistor.

The voltage is finally measured across R_{LV_DC}to monitor the stepped-down voltage of the HV DC-link which

must fall within the voltage range of AIN from 0.6V to 4.5V. The driver should be referenced to the same point as

the measurement reference, thus in the case shown below the UCC21759-Q1 is driving the lower IGBT in the

half-bridge and the DC-link voltage measurement is referenced to COM. The internal current source I_AINshould

be taken into account when designing the resistor divider. The AIN pin voltage is:

R_{LV _DC}

n

V_AIN

=

∂ V_DC+R_{LV _DC}∂I_AIN

R_{LV _DC}

+

R

atten _ i

ƒ

i=1

(10)

R_{atten_1}

R_{atten_2}

UCC217xx

VDD

VCC

R_{atten_n}

13V to

33V

+

3V to 5.5V

APWM

œ

C_DC

+

AIN

DEMOD

MOD

µC

R_filt

C_filt

R_{filt_2}

C_{filt_2}

GND

R_{LV_DC}

OSC

COM

Figure 9-12. DC-link Voltage Sensing Configuration

Submit Document Feedback

45

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

9.2.2.8 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the NPN/PNP buffer shown in

Figure 9-13) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and

must be avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/

D45VH10 pair is up to 20 A peak.

In the case of a over-current detection, the soft turn off (STO) is activated. External components must be added

to implement STO instead of normal turn off speed when an external buffer is used. C_STOsets the timing for soft

turn off and R_STOlimits the inrush current to below the current rating of the internal FET (10A). R_STOshould be at

least (VDD-VEE)/10. The soft turn off timing is determined by the internal current source of 400mA and the

capacitor C_STO. C_STOis calculated using Equation 11.

I_STO∂ t_STO

VDD

-

VEE

C_STO

=

(11)

•

I_STOis the the internal STO current source, 400mA

t_STOis the desired STO timing

VDD

UCC217xx

R_OH

C_ies=C_gc+C_ge

OUTH

OUTL

R_NMOS

C_gc

R_{G_2}

R_{G_1}

R_{G_Int}

C_ge

R_OL

C_STO

COM

VEE

R_STO

Figure 9-13. Current Buffer for Increased Drive Strength

46

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

9.2.3 Application Curves

Figure 9-14. PWM input (yellow) and driver output (blue)

Step Input (0.6 V to 4.5 V)

APWM Output

Figure 9-15. AIN step input (green) and APWM output (pink)

10 Power Supply Recommendations

During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and

VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a

voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of

decoupling capacitors are recommended at the power supplies. Considering UCC21759-Q1 has ±10A peak

drive strength and can generate high dV/dt, a 10µF bypass cap is recommended between VDD and COM, VEE

and COM. A 1µF bypass cap is recommended between VCC and GND due to less current comparing with

output side power supplies. A 0.1µF decoupling cap is also recommended for each power supply to filter out

high frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and

should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system

parasitics of PCB layout.

Submit Document Feedback

47

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

11 Layout

11.1 Layout Guidelines

Due to the strong drive strength of UCC21759-Q1, careful considerations must be taken in PCB design. Below

are some key points:

•

The driver should be placed as close as possible to the power semiconductor to reduce the parasitic

inductance of the gate loop on the PCB traces

•

The decoupling capacitors of the input and output power supplies should be placed as close as possible to

the power supply pins. The peak current generated at each switching transient can cause high dI/dt and

voltage spike on the parasitic inductance of PCB traces

•

The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If

the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close

as possible to the source or emitter terminal of the power device package to separate the gate loop from the

high power switching loop

•

Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the

high frequency noise generated by the output side switching transients. The ground plane provides a low-

inductance filter for the return current flow

If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the

ground plane on the output side to shield the output signals from the noise generated by the switch node; if

the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground

plane is not recommended

•

If ground plane is not used on the output side, separate the return path of the DESAT and AIN ground loop

from the gate loop ground which has large peak source and sink current

No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise

coupling between the input and output side which can contaminate the isolation barrier

48

Submit Document Feedback

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

11.2 Layout Example

Figure 11-1. Layout Example

Submit Document Feedback

49

UCC21759-Q1

SLUSEB4A – AUGUST 2020 – REVISED DECEMBER 2020

www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Isolation Glossary

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

50

Submit Document Feedback

GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

www.ti.com

EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC21759QDWRQ1
厂家：	TEXAS INSTRUMENTS
描述：	适用于 IGBT/SiC MOSFET 且具有 DESAT 和内部钳位的汽车类 3.0kVrms、±10A 单通道隔离式栅极驱动器 \| DW \| 16 \| -40 to 150 栅极驱动双极性晶体管驱动器
文件：	总57页 (文件大小：2481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21759QDWRQ1 [TI]

相关型号：

UCC2305

UCC2305-Q1

UCC2305DW

UCC2305DWG4

UCC2305N

UCC2305NG4

UCC2305TDWRQ1

UCC2305_14

UCC23313

UCC23313-Q1