UCC23514SDWV [TI]

具有钳位和分离输出选项的 5kVrms 4A/5A 单通道光兼容隔离式栅极驱动器 | DWV | 8 | -40 to 125;


型号：	UCC23514SDWV
厂家：	TEXAS INSTRUMENTS
描述：	具有钳位和分离输出选项的 5kVrms 4A/5A 单通道光兼容隔离式栅极驱动器 \| DWV \| 8 \| -40 to 125 栅极驱动驱动器
文件：	总40页 (文件大小：1935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC23514

ZHCSMC4A –JUNE 2020 –REVISED OCTOBER 2020

UCC23514 4A 拉电流、5A 灌电流、5.0kV_RMS光兼容

单通道隔离式栅极驱动器

高可靠性，非常适合所有类型的电机驱动器、光伏逆变

器、工业电源和电器。更高的工作温度为传统光耦合器

原来无法支持的应用开辟了机会。

1 特性

• 具有光兼容输入的5.0kV_RMS单通道隔离式栅极驱

动器

• 适用于光隔离式栅极驱动器的引脚对引脚普适版升

级

• 可输出4.5A 峰值拉电流、5.3A 峰值灌电流

• 12V 至33V 输出驱动器电源电压

• 轨到轨输出

• 105ns（最大值）传播延迟

• 25ns（最大值）器件间延迟匹配

• 35ns（最大值）脉宽失真度

• 150kV/μs（最小值）共模瞬态抗扰度(CMTI)

• 隔离栅寿命大于50 年

UCC23514V 选项可在单个终端上提供栅极驱动输出。

对于需要分离栅极驱动输出的应用，UCC23514S 版本

提供两个单独的输出引脚 OUTH 和 OUTL。如果应用

需要的 UVLO 以单独 COM 引脚为基准，则适用于

UCC23514E 版本，它有助于实现双极栅极驱动电源应

用。UCC23514M 选项将晶体管的栅极连接到内部钳

位，以防止米勒电流造成假接通。

器件信息⁽¹⁾

器件型号

特性说明

UCC23514E

UCC23514M

UCC23514S

UCC23514V

以发射极为基准的UVLO

米勒钳位

• 输入级具有13V 反极性电压处理能力

• DWV 封装，爬电距离为8.5mm

• 运行结温T_J：–40°C 至+150°C

• 安全相关认证（计划）：

分离输出

单个V_OUT引脚

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 符合DIN V VDE V0884-11:2017-01 标准的

7000V_PK增强型隔离

– 符合UL 1577 标准且长达1 分钟的5.0kV_RMS

隔离

– 符合GB4943.1-2011 标准的CQC 认证

ANODE

V_CC

UVLO

2 应用

V_OUT

CLAMP

V_EE

• 工业电机控制驱动

• 工业用电源，UPS

• 光伏逆变器

CATHODE

• 感应加热

3 说明

UCC23514 是一款适用于 IGBT、MOSFET 和 SiC

MOSFET 的光兼容单通道隔离式栅极驱动器，具有

4.5A 峰值拉电流和 5.3A 峰值灌电流以及 5.0kV_RMS增

强型隔离额定值。33V 的高电源电压范围允许使用双

极电源来有效驱动 IGBT 和 SiC 功率 FET 。

UCC23514 可以驱动低侧和高侧电源 FET。与基于光

耦合器的标准栅极驱动器相比，此器件的主要特性可显

著提高性能和可靠性，同时在原理图和布局设计中保持

引脚对引脚兼容性。性能亮点包括高共模瞬态抗扰度

(CMTI)、低传播延迟和小脉宽失真。

UCC23514M 的功能方框图

V_CC

UVLO

ANODE

CATHODE

V_OUT

COM

V_EE

严格的过程控制可实现较小的器件间偏移。输入级是仿

真二极管，这意味着与传统的 LED 相比，具有长期可

靠性和出色的老化特性。它采用 8 引脚表面贴装

7.5mm x 5.85mm（典型值）SOIC 封装，爬电距离和

间隙 ≥ 8.5mm，来自材料组 I 的模压化合物的相对漏

电起痕指数 (CTI) > 600V。UCC23514 具有高性能和

UCC23514E 的功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDV0

UCC23514

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ZHCSMC4A –JUNE 2020 –REVISED OCTOBER 2020

V_CC

ANODE

CATHODE

V_CC

UVLO

ANODE

OUTH

OUTL

V_EE

CATHODE

V_OUT

V_EE

UCC23514S 的功能方框图

UCC23514V 的功能方框图

English Data Sheet: SLUSDV0

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Table of Contents

6.11 Insulation Characteristics .......................................12

6.12 Typical Characteristics............................................13

7 Parameter Measurement Information..........................16

7.1 Propagation Delay, rise time and fall time.................16

7.2 I_OHand I_OLtesting.....................................................16

7.3 CMTI Testing.............................................................16

8 Detailed Description......................................................17

8.1 Overview...................................................................17

8.2 Functional Block Diagram.........................................17

8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................24

9 Application and Implementation..................................25

9.1 Application Information............................................. 25

9.2 Typical Application.................................................... 26

10 Power Supply Recommendations..............................33

11 Layout...........................................................................34

11.1 Layout Guidelines................................................... 34

11.2 PCB Material...........................................................34

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 3

5 Pin Configuration and Function.....................................4

Pin Functions for UCC23514E..........................................4

Pin Functions for UCC23514M......................................... 4

Pin Functions for UCC23514S..........................................5

Pin Functions for UCC23514V..........................................5

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Power Ratings.............................................................7

6.6 Insulation Specifications............................................. 8

6.7 Safety-Related Certifications...................................... 9

6.8 Safety Limiting Values.................................................9

6.9 Electrical Characteristics...........................................10

6.10 Switching Characteristics........................................11

Information.................................................................... 34

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (June 2020) to Revision A (October 2020)

Page

• Changed marketing status from Advance Information to initial release......................................................... 0

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5 Pin Configuration and Function

VCC

VOUT

COM

VEE

ANODE

CATHODE

Not to scale

图5-1. UCC23514E DWV Package 8-pin SOIC-WB Top View

Pin Functions for UCC23514E

NO.

TYPE

DESCRIPTION

NAME

UCC23514E

No Connection

—

ANODE

CATHODE

Anode

Cathode

No Connection

—

V_EE

Negative output supply rail

IGBT Emitter connection

Gate Drive Output

Positive output supply rail

COM

V_OUT

V_CC

VCC

ANODE

VOUT

CLAMP

VEE

CATHODE

Not to scale

图5-2. UCC23514M DWV Package 8-pin SOIC-WB Top View

Pin Functions for UCC23514M

NO.

TYPE

DESCRIPTION

NAME

UCC23514M

ANODE

Anode

No Connection

—

CATHODE

Cathode

No Connection

—

V_EE

Negative output supply rail

Miller Clamp Output

Gate Drive Output

Positive output supply rail

CLAMP

V_OUT

V_CC

English Data Sheet: SLUSDV0

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VCC

ANODE

CATHODE

OUTH

OUTL

VEE

Not to scale

图5-3. UCC23514S DWV Package 8-pin SOIC-WB Top View

Pin Functions for UCC23514S

NO.

TYPE

DESCRIPTION

NAME

UCC23514S

No Connection

—

ANODE

CATHODE

Anode

Cathode

No Connection

—

V_EE

Negative output supply rail

Gate-drive Pull down

Gate Drive Pull up

Positive output supply rail

OUTL

OUTH

V_CC

VCC

ANODE

CATHODE

VOUT

VEE

Not to scale

图5-4. UCC23514V DWV Package 8-pin SOIC-WB Top View

Pin Functions for UCC23514V

NO.

TYPE

DESCRIPTION

NAME

UCC23514V

No Connection

Anode

—

ANODE

CATHODE

Cathode

No Connection

Negative output supply rail

Gate-drive output

No Connection

Positive output supply rail

—

V_EE

V_OUT

—

V_CC

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Average Input Current

Peak Transient Input Current

Reverse Input Voltage

Output supply voltage

Output signal voltage

Junction temperature

Storage temperature

I_F(AVG)

I_F(TRAN)<1us pulse, 300pps

V_R(MAX)

-0.3

V_CC–V_EE

0.3

_OUT–V_CC

-0.3

-40

-65

_OUT–V_EE

(2)

T_J

150

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) To maintain the recommended operating conditions for T_J, see the 节6.4.

6.2 ESD Ratings

VALUE

±4000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS–001¹

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC specification JESD22-C101²

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_CC

Output Supply Voltage(V_CC–V_EE

)

I_F(ON)

V_F(OFF)

T_J

Input Diode Forward Current (Diode "ON")

Anode voltage - Cathode voltage (Diode "OFF")

Junction temperature

-13

-40

0.9

150

125

°C

T_A

Ambient temperature

6.4 Thermal Information

UCC23514E, UCC23514M,

UCC23514S, UCC23514V

THERMAL METRIC⁽¹⁾

UNIT

DWV (SOIC)

8 PINS

108.5

52.0

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

58.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

32.7

56.6

ψ_JB

(1) For more information about traditional and new thermal metrics, see the http://www.ti.com/lit/SPRA953 application report.

English Data Sheet: SLUSDV0

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6.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Maximum power dissipation on input and

output⁽¹⁾

P_D

750

V_CC= 20 V, I_F= 10mA 10-kHz, 50% duty

cycle, square wave,180-nF load, T_A=25^oC

P_D1

P_D2

Maximum input power dissipation⁽²⁾

Maximum output power dissipation

740

(1) Derate at 6 mW/°C beyond 25°C ambient temperature

(2) Recommended maximum P_D1= 40mW. Absolute maximum P_D1= 55mW

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6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

> 8.5

UNIT

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance through air

Shortest pin-to-pin distance across the package surface

> 8.5

Distance through the

insulation

DTI

CTI

Minimum internal gap (internal clearance)

> 17

µm

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

> 600

I-IV

I-III

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage category per

IEC 60664-1

DIN V VDE V 0884-11:2017-01⁽²⁾

Maximum repetitive peak

V_IORM

AC voltage (bipolar)

2121

V_PK

isolation voltage

AC voltage (sine wave); time dependent dielectric breakdown

(TDDB) test;

1500

2121

7000

V_RMS

V_DC

V_PK

Maximum working isolation

voltage

V_IOWM

DC Voltage

Maximum transient isolation V_TEST= V_IOTM, t = 60 s (qualification);

V_IOTM

V_IOSM

voltage

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

Maximum surge isolation

voltage⁽³⁾

Test method per IEC 62368-1, 1.2/50 μs waveform,

V_TEST= 1.6 × V_IOSM(qualification)

8000

V_PK

Method a, After I/O safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s;

≤5

V_pd(m)= 1.2 × V_IORM, t_m= 10 s

Method a, After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.6 × V_IORM= 2400 V_PK, t_m= 10 s

≤5

q_pd

Apparent charge⁽⁴⁾

Method b1; At routine test (100% production) and

preconditioning (type test)

V_ini= 1.2 × V_IOTM; t_ini= 1 s;

≤5

V_pd(m)= 1.875 × V_IORM= 2813 V_PK, t_m= 1 s

Barrier capacitance, input to

output⁽⁵⁾

C_IO

R_IO

0.5

V_IO= 0.4 sin (2πft), f =1 MHz

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output⁽⁵⁾

V_IO= 500 V at 100°C ≤T_A≤125°C

V_IO= 500 V at T_S=150°C

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO= 5000 V_RMS, t = 60 s. (qualification),

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

5000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

English Data Sheet: SLUSDV0

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6.7 Safety-Related Certifications

VDE

CQC

Plan to certify according to DIN V VDE V

0884-11: 2017-01

Plan to certify according to UL 1577

Component Recognition Program

Plan to certify according to GB4943.1-2011

Reinforced insulation Maximum transient

isolation voltage, 7000 V_PK

Maximum repetitive peak isolation voltage,

2121 V_PK

;

Reinforced insulation, Altitude ≤5000 m,

Tropical Climate

Single protection, 5000 V_RMS

Certificate planned

Maximum surge isolation voltage, 8000 V_PK

Certificate planned

6.8 Safety Limiting Values

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_qJA= 126°C/W, V_I= 15 V, T_J= 150°C,

T_A= 25°C

I_S

Safety input, output, or supply current

R_qJA= 126°C/W, V_I= 30 V, T_J= 150°C,

T_A= 25°C

P_S

T_S

Safety input, output, or total power

Maximum safety temperature¹

R_qJA= 126°C/W, T_J= 150°C, T_A= 25°C

750

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A. The junction-to-air thermal resistance, R_qJA, in the Thermal Information

table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value

for each parameter: T_J= T_A+ R_qJA´ P, where P is the power dissipated in the device. T_J(max)= T_S= T_A+ R_qJA´ P_S, where T_J(max)is

the maximum allowed junction temperature. P_S= I_S´ V_I, where VI is the maximum supply voltage.

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6.9 Electrical Characteristics

Unless otherwise noted, all typical values are at T_A= 25°C, V_CC–V_EE= 15V, V_EE= GND. All min and max specifications are

at recommended operating conditions (T_J= -40C to 150°C, I_F(on)= 7 mA to 16 mA, V_EE= GND, V_CC= 15 V to 30 V, V_F(off)= –

5V to 0.8V)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

Input Forward Threshold Current

Low to High

I_FLH

V_OUT> 5 V, Cg = 1 nF

I_F=10 mA

1.5

2.8

2.1

V_F

Input Forward Voltage

1.8

0.9

2.4

V_{F_HL}

Threshold Input Voltage High to Low V < 5 V, Cg = 1 nF

Temp Coefficient of Input Forward

I_F=10 mA

Voltage

1.35

mV/°C

ΔV_F/ΔT

V_R

Input Reverse Breakdown Voltage

Input Capacitance

I_R= 10 uA

C_IN

F = 0.5 MHz

OUTPUT

I_F= 10 mA, V_CC=15V,

C_LOAD=0.18uF, C_VDD=10uF, pulse

width <10us

I_OH

High Level Peak Output Current

Low Level Peak Output Current

4.5

5.3

V_F= 0 V, V_CC=15V,

C_LOAD=0.18uF, C_VDD=10uF, pulse

width <10us

I_OL

3.5

I_F= 10 mA, I_O= -20mA (with

respect to VCC)

0.07

0.18

VCC

0.36

V_OH

High Level Output Voltage

I_F= 10 mA, I_O= 0 mA

V_F= 0 V, I_O= 20 mA

I_F= 10 mA, I_O= 0 mA

V_F= 0 V, I_O= 0 mA

V_OL

Low Level Output Voltage

2.2

I_{CC_H}

I_{CC_L}

Output Supply Current (Diode On)

Output Supply Current (Diode Off)

INTERNAL MILLER CLAMP

V_CLMPTHMiller Clamp Threshold Voltage

I_CLMPMiller Clamp current

UNDER VOLTAGE LOCKOUT

CLAMP-V_EE

2.1

1.6

2.3

CLAMP = 3.5V above VEE

UCC23514M, UCC23514S, and

UCC23514V: V_CCto V_EE, I_F=10

UVLO_R

UVLO_F

Under Voltage Lockout VCC, rising

12.5

13.5

12.5

UCC23514E: V_CCto COM, I_F=10

UCC23514M, UCC23514S, and

UCC23514V: V_CCto V_EE, I_F=10

Under Voltage Lockout VCC, falling

11.5

1.0

UCC23514E: V_CCto COM, I_F=10

UVLO_HYSUVLO Hysteresis

English Data Sheet: SLUSDV0

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6.10 Switching Characteristics

Unless otherwise noted, all typical values are at T_A= 25°C, V_CC-V_EE= 30 V, V_EE= GND. All min and max specifications are at

recommended operating conditions (T_J= -40 to 150°C, I_F(ON)= 7 mA to 16 mA, V_EE= GND, V_CC= 15 V to 30 V, V_F(OFF)= –5V

to 0.8V)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_r

Output-signal Rise Time

Output-signal Fall Time

Propagation Delay, Low to High

Propagation Delay, High to Low

t_f

Cg = 1nF

F_SW= 20 kHz, (50% Duty Cycle)

VCC=15V

t_PLH

t_PHL

105

Pulse Width Distortion |t_PHL

t_PLH

–

t_PWD

Cg = 1nF

F_SW= 20 kHz, (50% Duty Cycle)

VCC=15V, I_F=10mA

Part-to-Part Skew in Propagation

Delay Between any Two Parts⁽¹⁾

t_sk(pp)

t_{UVLO_rec}

CMTI_H

UVLO Recovery Delay

V_CCRising from 0V to 15V

µs

Common-mode Transient

Immunity (Output High)

I_F= 10 mA, V_CM= 1500 V, V_CC= 30 V,

T_A= 25°C

150

kV/µs

Common-mode Transient

Immunity (Output Low)

V_F= 0 V, V_CM= 1500 V, V_CC= 30 V, T_A=

25°C

CMTI_L

kV/µs

(1) t_sk(pp)is the magnitude of the difference in propagation delay times between the output of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization.

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6.11 Insulation Characteristics

1.E+12

1.E+11

1.E+10

54 Yrs

1.E+09

1.E+08

1.E+07

1.E+06

1.E+05

1.E+04

1.E+03

1.E+02

1.E+01

TDDB Line (< 1 ppm Fail Rate)

VDE Safety Margin Zone

1800V_RMS

2200

200

1200

3200

4200

5200

6200

Applied Voltage (V_RMS

)

图6-1. Reinforced Isolation Capacitor Life Time Projection

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6.12 Typical Characteristics

V_CC= 15 V, 1-µF capacitor from V_CCto V_EE, C_LOAD= 1 nF for timing tests and 180nF for I_OHand I_OLtests, T_J=

–40°C to +150°C, (unless otherwise noted)

1.5

1.45

1.4

6.6

6.3

ICC H

ICC L

IOH

IOL

1.35

1.3

5.7

5.4

5.1

4.8

4.5

4.2

3.9

3.6

3.3

1.25

1.2

1.15

1.1

1.05

0.95

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temp (èC)

D002

Temp (èC)

D001

图6-3. Supply currents versus Temperature

C_LOAD= 180-nF

图6-2. Output Drive currents versus Temperature

1.4

3.5

3.4

3.3

3.2

3.1

ICC H

ICC L

1.3

1.2

1.1

2.9

2.8

2.7

2.6

-40 -20

80 100 120 140 160

15.5

20.5

23 25.5

V_CC(V)

30.5

33 35

Temp (èC)

D004

D003

图6-5. Forward threshold current versus

图6-4. Supply current versus Supply Voltage

Temperature

t_PDLH

t_PDHL

t_PDLH

t_PDHL

-40 -20

80 100 120 140 160

I_F(mA)

Temp (èC)

D006

D005

C_LOAD= 1-nF

图6-7. Propagation delay versus Forward current

图6-6. Propagation delay versus Temperature

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0.9

0.85

0.8

300

280

260

240

220

200

180

160

140

120

0.75

0.7

0.65

0.6

0.55

0.5

0.45

-40 -20

80 100 120 140 160

-40 -20

80 100 120 140 160

Temp (èC)

D007

D008

I_OUT= 0mA

I_OUT= 20mA

(sourcing)

图6-8. V_OH(No Load) versus Temperature

图6-9. V_OH(20mA Load) versus Temperature

t_PLH

t_PHL

-40 -20

80 100 120 140 160

Temp (èC)

V_CC(V)

D009

D010

I_OUT= 20mA

(sinking)

图6-11. Propagation delay versus Supply voltage

图6-10. V_OLversus Temperature

2.8

2.6

2.4

2.2

2.1

1.9

1.8

1.7

1.6

1.8

1.6

1.4

1.2

10 12 14 16 18 20 22 24 25

I_F(mA)

80 100 120 140 160 180 200

Freq (KHz)

D012

D011

T_A= 25°C

图6-12. Supply current versus Frequency

图6-13. Forward current versus Forward voltage

drop

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2.3

2.28

2.26

2.24

2.22

2.2

2.18

2.16

2.14

2.12

2.1

2.08

-40 -20

80 100 120 140 160

Temp (èC)

D013

I_F= 10mA

图6-14. Forward voltage drop versus Temperature

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7 Parameter Measurement Information

7.1 Propagation Delay, rise time and fall time

图 7-1 shows the propagation delay from the input forward current I_F, to V_OUT. This figures also shows the circuit

used to measure the rise (t_r) and fall (t_f) times and the propagation delays t_PDLHand t_PDHL

ANODE

V_CC

270Q

I_F

V_OUT

t_{PD_LH}

t_{PD_HL}

15V

1nF

80%

50%

20%

V_EE

CATHODE

V_OUT

t_r

t_f

图7-1. I_Fto V_OUTPropagation Delay, Rise Time and Fall Time

7.2 I_OHand I_OLtesting

图 7-2 shows the circuit used to measure the output drive currents I_OHand I_OL. A load capacitance of 180nF is

used at the output. The peak dv/dt of the capacitor voltage is measured in order to determine the peak source

and sink currents of the gate driver.

ANODE

V_CC

270Q

I_F

V_OUT

I_OH

15V

I_OL

180nF

V_EE

CATHODE

图7-2. I_OHand I_OL

7.3 CMTI Testing

图 7-3 is the simplified diagram of the CMTI testing. Common mode voltage is set to 1500V. The test is

performed with I_F= 6mA (VOUT= High) and I_F= 0mA (V_OUT= LOW). The diagram also shows the fail criteria for

both cases. During the application on the CMTI pulse with I_F= 6mA, if V_OUTdrops from VCC to ½VCC it is

considered as a failure. With I_F= 0mA, if V_OUTrises above 1V, it is considered as a failure.

e-diode off

V_CM

e-diode on

V_CM

ANODE

V_CC

150Q

1500V

I_F

V_OUT

30V

V_OUT

1nF

30V

15V

V_EE

CATHODE

Fail Threshold

V_OUT

V_CM=1500V

图7-3. CMTI Test Circuit

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8 Detailed Description

8.1 Overview

UCC23514 is a single channel isolated gate driver, with an opto-compatible input stage, that can drive IGBTs,

MOSFETs and SiC FETs. It has 4A peak output current capability with max output driver supply voltage of 33V.

The inputs and the outputs are galvanically isolated. UCC23514 is offered in an industry standard 8 pin (SOIC)

package with >8.5mm creepage and clearance. It has a working voltage of 1500-V_RMS, reinforced isolation rating

of 5.0-kV_RMSfor 60s and a surge rating of 8-kV_PK. It is pin-to-pin compatible with standard opto isolated gate

drivers. While standard opto isolated gate drivers use an LED as the input stage, UCC23514 uses an emulated

diode (or "e-diode") as the input stage which does not use light emission to transmit signals across the isolation

barrier. The input stage is isolated from the driver stage by dual, series HV SiO₂capacitors in full differential

configuration that not only provides reinforced isolation but also offers best-in-class common mode transient

immunity of >150kV/us. The e-diode input stage along with capacitive isolation technology gives UCC23514

several performance advantages over standard opto isolated gate drivers. They are as follows:

1. Since the e-diode does not use light emission for its operation, the reliability and aging characteristics of

UCC23514 are naturally superior to those of standard opto isolated gate drivers.

2. Higher ambient operating temperature range of 125°C, compared to only 105°C for most opto isolated gate

drivers

3. The e-diode forward voltage drop has less part-to-part variation and smaller variation across temperature.

Hence, the operating point of the input stage is more stable and predictable across different parts and

operating temperature.

4. Higher common mode transient immunity than opto isolated gate drivers

5. Smaller propagation delay than opto isolated gate drivers

6. Due to superior process controls achievable in capacitive isolation compared to opto isolation, there is less

part-to-part skew in the prop delay, making the system design simpler and more robust

7. Smaller pulse width distortion than opto isolated gate drivers

The signal across the isolation has an on-off keying (OOK) modulation scheme to transmit the digital data across

a silicon dioxide based isolation barrier (see 图 8-4). The transmitter sends a high-frequency carrier across the

barrier to represent one digital state and sends no signal to represent the other digital state. The receiver

demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The

UCC23514 also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the

radiated emissions from the high frequency carrier and IO buffer switching. 图 8-5 shows conceptual detail of

how the OOK scheme works.

8.2 Functional Block Diagram

Receiver

Transmitter

V_CC

I_F

UVLO

Anode

V_BIAS

R_NMOS

R_OH

V_OUT

Level

Shift /

Pre

Amplifier

Demodulator

Oscillator

V_clamp

driver

COM

Cathode

R_OL

V_EE

图8-1. Functional Block Diagram for UCC23514E (COM pin connection to IGBT Emitter)

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Receiver

Transmitter

V_CC

I_F

UVLO

Anode

V_BIAS

R_NMOS

R_OH

V_EE

V_OUT

Level

Shift /

Pre

Amplifier

Oscillator

Demodulator

V_clamp

driver

CLAMP

Cathode

R_OL

R_CLMP

V_EE

图8-2. Functional Block Diagram for UCC23514M (Miller clamp)

Receiver

Transmitter

V_CC

I_F

UVLO

Anode

V_BIAS

R_NMOS

R_OH

V_EE

OUTH

OUTL

Level

Shift /

Pre

Amplifier

Demodulator

Oscillator

V_clamp

driver

Cathode

R_OL

V_EE

图8-3. Functional Block Diagram for UCC23514S (Split output)

Receiver

Transmitter

V_CC

I_F

UVLO

Anode

V_BIAS

R_NMOS

R_OH

V_EE

Level

Shift /

Pre

V_OUT

Amplifier

Oscillator

Demodulator

V_clamp

driver

R_OL

Cathode

V_EE

图8-4. Functional Block Diagram for UCC23514V (single output pin)

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I_FIN

Carrier signal

through isolation

barrier

RX OUT

图8-5. On-Off Keying (OOK) Based Modulation Scheme

8.3 Feature Description

8.3.1 Power Supply

Since the input stage is an emulated diode, no power supply is needed at the input.

The output supply, V_CC, supports a voltage range from 14V to 33V. For operation with bipolar supplies, the

power device is turned off with a negative voltage on the gate with respect to the emitter or source. This

configuration prevents the power device from unintentionally turning on because of current induced from the

Miller effect. The typical values of the V_CCand V_EEoutput supplies for bipolar operation are 15V and -8V with

respect to GND for IGBTs, and 20V and -5V for SiC MOSFETs.

For operation with unipolar supply, the V_CCsupply is connected to 15V with respect to GND for IGBTs, and 20V

for SiC MOSFETs. The V_EEsupply is connected to 0V.

8.3.2 Input Stage

The input stage of UCC23514 is simply the e-diode and therefore has an Anode (Pin 1) and a Cathode (Pin 3).

Pin 2 has no internal connection and can be left open or connected to ground. The input stage does not have a

power and ground pin. When the e-diode is forward biased by applying a positive voltage to the Anode with

respect to the Cathode, a forward current I_Fflows into the e-diode. The forward voltage drop across the e-diode

is 2.1V (typ). An external resistor should be used to limit the forward current. The recommended range for the

forward current is 7mA to 16mA. When I_Fexceeds the threshold current I_FLH(2.8mA typ.) a high frequency signal

is transmitted across the isolation barrier through the high voltage SiO₂capacitors. The HF signal is detected by

the receiver and V_OUTis driven high. See 节 9.2.2.1 for information on selecting the input resistor. The dynamic

impedance of the e-diode is very small(<1.0Ω) and the temperature coefficient of the e-diode forward voltage

drop is <1.35mV/°C. This leads to excellent stability of the forward current I_Facross all operating conditions. If

the Anode voltage drops below V_{F_HL}(0.9V), or reverse biased, the gate driver output is driven low. The reverse

breakdown voltage of the e-diode is >15V. So for normal operation, a reverse bias of up to 13V is allowed. The

large reverse breakdown voltage of the e-diode enables UCC23514 to be operated in interlock architecture (see

example in 图 8-6) where V_SUPcan be as high as 12V. The system designer has the flexibility to choose a 3.3V,

5.0V or up to 12V PWM signal source to drive the input stage of UCC23514 using an appropriate input resistor.

The example shows two gate drivers driving a set of IGBTs. The inputs of the gate drivers are connected as

shown and driven by two buffers that are controlled by the MCU. Interlock architecture prevents both the e-

diodes from being "ON" at the same time, preventing shoot through in the IGBTs. It also ensures that if both

PWM signals are erroneously stuck high (or low) simultaneously, both gate driver outputs will be driven low.

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V_SUP

ANODE

V_CC

HSON from MCU

GND

UVLO

To High Side

Gate

V_OUT

V_SUP

V_EE

CATHODE

LSON from MCU

GND

ANODE

V_CC

UVLO

To Low Side

Gate

V_OUT

CATHODE

V_EE

图8-6. Interlock

8.3.3 Output Stage

The output stages of the UCC23514 family feature a pullup structure that delivers the highest peak-source

current when it is most needed which is during the Miller plateau region of the power-switch turnon transition

(when the power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features

a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel

MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turnon. Fast turnon is

accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing

states from low to high. The on-resistance of this N-channel MOSFET (R_NMOS) is approximately 5.1 Ω when

activated.

表8-1. UCC23514 On-Resistance

R_NMOS

R_OH

R_OL

UNIT

5.1

9.5

0.40

The R_OHparameter is a DC measurement and is representative of the on-resistance of the P-channel device

only. This parameter is only for the P-channel device because the pullup N-channel device is held in the OFF

state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.

Therefore, the effective resistance of the UCC23514 pullup stage during this brief turnon phase is much lower

than what is represented by the R_OHparameter, yielding a faster turn on. The turnon-phase output resistance is

the parallel combination R_OH|| R_NMOS

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The pulldown structure in the UCC23514 is simply composed of an N-channel MOSFET. The output voltage

swing between V_CCand V_EEprovides rail-to-rail operation because of the MOS-out stage which delivers very low

dropout.

V_CC

UVLO

R_NMOS

R_OH

V_EE

Level

Shift /

Pre

V_OUT

Demodulator

driver

R_OL

V_EE

图8-7. Output Stage

8.3.4 Protection Features

8.3.4.1 Undervoltage Lockout (UVLO)

UVLO function is implemented for V_CCand V_EEpins to prevent an under-driven condition on IGBTs and

MOSFETs. When V_CCis lower than UVLO_Rat device start-up or lower than UVLO_Fafter start-up, the voltage-

supply UVLO feature holds the effected output low, regardless of the input forward current as shown in 表 8-2.

The V_CCUVLO protection has a hysteresis feature (UVLO_hys). This hysteresis prevents chatter when the power

supply produces ground noise which allows the device to permit small drops in bias voltage, which occurs when

the device starts switching and operating current consumption increases suddenly.

When V_CCdrops below UVLO_F, a delay, t_{UVLO_rec}occurs on the output when the supply voltage rises above

UVLO_Ragain.

UVLO is referenced to COM on the UCC23514E, and to V_EEin all other versions.

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10mA

I_F

V_CC

UVLO_R

UVLO_F

V_CC

t_{UVLO_rec}

V_OUT

图8-8. UVLO functionality

8.3.4.2 Active Pulldown

The active pull-down function is used to pull the IGBT or MOSFET gate to the low state when no power is

connected to the V_CCsupply. This feature prevents false IGBT and MOSFET turn-on by clamping V_OUTpin to

approximately 2V.

When the output stage of the driver is in an unbiased condition (V_CCfloating), the driver outputs (see 图 8-7) are

held low by an active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the upper

PMOS & NMOS are held off while the lower NMOS gate is tied to the driver output through an internal 500-kΩ

resistor. In this configuration, the lower NMOS device effectively clamps the output (V_OUT) to less than 2V.

8.3.4.3 Short-Circuit Clamping

The short-circuit clamping function is used to clamp voltages at the driver output and pull the output pin V_OUT

slightly higher than the V_CCvoltage during short-circuit conditions. The short-circuit clamping function helps

protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping

function is implemented by adding a diode connection between the dedicated pins and the V_CCpin inside the

driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of

20 mA. Use external Schottky diodes to improve current conduction capability as needed.

8.3.4.4 Active Miller Clamp (UCC23514M)

The active Miller-clamp function is used to prevent false turn on of the power switches caused by Miller current in

applications where a unipolar power supply is used. The active Miller-clamp function is implemented by adding a

low impedance path between the power-switch gate terminal and ground (V_EE) to sink the Miller current. The

Miller clamping function is implemented by adding a low impedance path between the gate of the power device

and the V_EEsupply. Miller current sinks through the clamp pin, which clamps the gate voltage to be lower than

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the gate turn-on threshold value for the power device. The clamp engages whenever the voltage at the CLAMP

pin goes below V_CLMPTH

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8.4 Device Functional Modes

表8-2 lists the functional modes for UCC23514

表8-2. Function Table for UCC23514 with VCC Rising

e-diode

VCC

V_OUT

Low

High

OFF (I_F< I_FLH

)

0V - 33V

ON (I_F> I_FLH

)

0V - UVLO_R

UVLO_R- 33V

ON ( (I_F> I_FLH

)

表8-3. Function Table for UCC23514 with VCC Falling

e-diode

VCC

V_OUT

Low

High

OFF (I_F< I_FLH

)

0V - 33V

ON (I_F> I_FLH

)

UVLO_F- 0V

33V - UVLO_F

ON ( (I_F> I_FLH

)

8.4.1 ESD Structure

图 8-9 shows the multiple diodes involved in the ESD protection components of the UCC23514 device . This

provides pictorial representation of the absolute maximum rating for the device.

V_CC

Anode

40V

20V

V_OUT

40V

2.5V

36V

Cathode

V_EE

图8-9. ESD Structure

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9 Application and Implementation

备注

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

UCC23514 is a single channel, isolated gate driver with opto-compatible input for power semiconductor devices,

such as MOSFETs, IGBTs, or SiC MOSFETs. It is intended for use in applications such as motor control,

industrial inverters, and switched-mode power supplies. It differs from standard opto isolated gate drivers as it

does not have an LED input stage. Instead of an LED, it has an emulated diode (e-diode). To turn the e-diode

"ON", a forward current in the range of 7mA to 16mA should be driven into the Anode. This will drive the gate

driver output High and turn on the power FET. Typically, MCU's are not capable of providing the required forward

current. Hence a buffer has to be used between the MCU and the input stage of UCC23514. Typical buffer

power supplies are either 5V or 3.3V. A resistor is needed between the buffer and the input stage of UCC23514

to limit the current. It is simple, but important to choose the right value of resistance. The resistor tolerance,

buffer supply voltage tolerance and output impedance of the buffer, have to be considered in the resistor

selection. This will ensure that the e-diode forward current stays within the recommended range of 7mA to

16mA. Detailed design recommendations are given in the 节 9.1. The current driven input stage offers excellent

noise immunity that is need in high power motor drive systems, especially in cases where the MCU cannot be

located close to the isolated gate driver. UCC23514 offers best in class CMTI performance of >150kV/us at

1500V common mode voltages.

The e-diode is capable of 25mA continuous in the forward direction. The forward voltage drop of the e-diode has

a very tight part to part variation (1.8V min to 2.4V max). The temperature coefficient of the forward drop is

<1.35mV/°C. The dynamic impedance of the e-diode in the forward biased region is ~1Ω. All of these factors

contribute in excellent stability of the e-diode forward current. To turn the e-diode "OFF", the Anode - Cathode

voltage should be <0.8V, or I_Fshould be <I_FLH. The e-diode can also be reverse biased up to 13V (14V abs max)

in order to turn it off and bring the gate driver output low. The large reverse breakdown voltage of the input stage

provides system designers the flexibility to drive the input stage with 12V PWM signals without the need for an

additional clamping circuit on the Anode and Cathode pin.

The output power supply for UCC23514 can be as high as 33V (35V abs max). The output power supply can be

configured externally as a single isolated supply up to 33V or isolated bipolar supply such that V_CC-V_EEdoes not

exceed 33V, or it can be bootstrapped (with external diode & capacitor) if the system uses a single power supply

with respect to the power ground. Typical quiescent power supply current from V_CCis 1.2mA (max 2.2mA).

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9.2 Typical Application

The circuit in 图9-2, shows a typical application for driving IGBTs.

V_SUP

V_CC

R_EXT/2

15V

R_GON

R_{G_int}

ANODE

V_OUT

COM

V_EE

V_F

I_F

R_GOFF

CATHODE

R_EXT/2

GND2

PWM

GND

图9-1. Typical Application Circuit for UCC23514E to Drive IGBT with Split Gate Drive Supply

V_SUP

R_EXT/2

ANODE

V_CC

I_F

15V

R_GON

R_{G_int}

V_OUT

CLAMP

V_EE

V_F

R_GOFF

CATHODE

R_EXT/2

PWM

GND2

GND

图9-2. Typical Application Circuit for UCC23514M to Drive IGBT

V_SUP

V_CC

R_EXT/2

15V

R_GON

R_{G_int}

ANODE

OUTH

OUTL

V_EE

V_F

I_F

R_GOFF

CATHODE

R_EXT/2

PWM

GND2

GND

图9-3. Typical Application Circuit for UCC23514S to Drive IGBT

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V_SUP

V_CC

R_EXT/2

ANODE

V_OUT

V_EE

15V

V_F

I_F

R_GON

R_{G_int}

CATHODE

R_EXT/2

R_GOFF

PWM

GND2

GND

图9-4. Typical Application Circuit for UCC23514V to Drive IGBT

9.2.1 Design Requirements

表9-1 lists the recommended conditions to observe the input and output of the UCC23514 gate driver.

表9-1. UCC23514 Design Requirements

PARAMETER

VALUE

UNIT

V_CC

I_F

kHz

Switching frequency

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9.2.2 Detailed Design Procedure

9.2.2.1 Selecting the Input Resistor

The input resistor limits the current that flows into the e-diode when it is forward biased. The threshold current

I_FLHis 2.8 mA typ. The recommended operating range for the forward current is 7 mA to 16 mA (e-diode ON). All

the electrical specifications are guaranteed in this range. The resistor should be selected such that for typical

operating conditions, I_Fis 10mA. Following are the list of factors that will affect the exact value of this current:

1. Supply Voltage V_SUPvariation

2. Manufacturer's tolerance for the resistor and variation due to temperature

3. e-diode forward voltage drop variation (at I_F=10mA, V_F= typ 2.1 V, min 1.8 V, max 2.4 V, with a temperature

coefficient <1.35 mV/°C and dynamic impedance <1Ω)

See 图 9-5 for the schematic using a single NMOS and split resistor combination to drive the input stage of

UCC23514. The input resistor can be selected using the equation shown.

V_SUP

R_EXT/2

ANODE

V_CC

I_F

V_OUT

V_F

V_EE

CATHODE

R_EXT/2

PWM

GND

V_SUPF V_F

R_EXT

F R_M1

I_F

图9-5. Configuration 1: Driving the input stage of UCC23514 with a single NMOS and split resistors

Driving the input stage of UCC23514 using a single buffer is shown in 图 9-6 and using 2 buffers is shown in 图

9-7

V_SUP

I_F

ANODE

V_CC

R_EXT/2

PWM (From MCU)

GND

V_OUT

V_F

V_EE

R_EXT/2

CATHODE

GND

V_SUPF V_F

R_EXT

F R_{OH_buf}

I_F

图9-6. Configuration 2: Driving the input stage of UCC23514 with one Buffer and split resistors

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V_SUP

I_F

ANODE

V_CC

R_EXT/2

PWM (From MCU)

GND

V_OUT

V_F

V_SUP

V_EE

R_EXT/2

CATHODE

PWM (From MCU)

V_SUPF V_F

R_EXT

F (R_{OH_buf}+ R_{OL_buf})

I_F

图9-7. Configuration 3: Driving the input stage of UCC23514 with 2 buffers and split resistors

表 9-2 shows the range of values for R_EXTfor the 3 different configurations shown in 图 9-5, 图 9-6 and 图

9-7.The assumptions used in deriving the range for R_EXTare as follows:

1. Target forward current I_Fis 7mA min, 10mA typ and 16mA max

2. e-diode forward voltage drop is 1.8V to 2.4V

3. V_SUP(Buffer supply voltage) is 5V with ±5% tolerance

4. Manufacturer's tolerance for R_EXTis 1%

5. NMOS resistance is 0.25Ωto 1.0Ω(for configuration 1)

6. R_OH(buffer output impedance in output "High" state) is 13Ωmin, 18Ωtyp and 22Ωmax

7. R_OL(buffer output impedance in "Low" state) is 10Ωmin, 14Ωtyp and 17Ωmax

表9-2. R_EXTValues to Drive The Input Stage

_EXTΩ

Configuration

Min

218

Typ

Max

331

Single NMOS and

R_EXT

290

Single Buffer and

R_EXT

204

194

272

259

311

294

Two Buffers and R_EXT

9.2.2.2 Gate-Driver Output Resistor

The external gate-driver resistors, R_G(ON)and R_G(OFF)are used to:

1. Limit ringing caused by parasitic inductances and capacitances

2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery

3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss

4. Reduce electromagnetic interference (EMI)

The output stage has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in

parallel. The combined peak source current is 4.5 A Use 方程式 1 to estimate the peak source current as an

example.

V_CCF V_GDF

I_OH= minH4.5A,

(R_NMOS||R_OH+ R_GON+ R_GFET

)

INT

(1)

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where

• R_GONis the external turnon resistance.

• R_{GFET_Int}is the power transistor internal gate resistance, found in the power transistor data sheet. We will

assume 0Ωfor our example

• I_OHis the peak source current which is the minimum value between 4.5A, the gate-driver peak source

current, and the calculated value based on the gate-drive loop resistance.

• V_GDFis the forward voltage drop for each of the diodes in series with R_GONand R_GOFF. The diode drop for

this example is 0.7 V.

In this example, the peak source current is approximately 1.7A as calculated in 方程式2.

15 F 0.7

I_OH= minH4.5A,

I = 1.72A

(5.sÀ||9.wÀ + wÀ + rÀ)

(2)

(3)

Similarly, use 方程式3 to calculate the peak sink current.

V_CCF V_GDF

I_OL= minH5.3A,

(R_OL+ R_GOFF+ R_GFET

)

INT

where

• R_GOFFis the external turnoff resistance.

• I_OLis the peak sink current which is the minimum value between 5.3A, the gate-driver peak sink current, and

the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum of 方程式4 and 5.3A.

15 F 0.7

I_OL= minH5.3A,

I = 1.38A

(0.vÀ + srÀ + rÀ)

(4)

The diodes shown in series with each, R_GONand R_GOFF, in 图 9-1, 图 9-2, and 图 9-4 ensure the gate drive

current flows through the intended path, respectively, during turn-on and turn-off. Note that the diode forward

drop will reduce the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a

resistor from the V_OUTpin to the power switch gate, with a resistance value approximately 20 times higher than

R_GONand R_GOFF. For the examples described in this section, a good choice is 100 Ωto 200 Ω.

The UCC23514S provides split output pins, OUTH and OUTL, which provide separate paths for turn-on and

turn-off current. The series diodes are not necessary when this device option is used, as shown in 图 9-3. For

this case, substitute V_GDF= 0 V in the equations above. The UCC23514S provides rail-to-rail gate voltage levels

without need for additional parallel resistors.

备注

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot

and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized.

Conversely, the peak source and sink current is dominated by loop parasitics when the load

capacitance (C_ISS) of the power transistor is very small (typically less than 1 nF) because the rising

and falling time is too small and close to the parasitic ringing period.

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9.2.2.3 Estimate Gate-Driver Power Loss

The total loss, P_G, in the gate-driver subsystem includes the power losses (P_GD) of the UCC23514 device and

the power losses in the peripheral circuitry, such as the external gate-drive resistor.

The P_GDvalue is the key power loss which determines the thermal safety-related limits of the UCC23514 device,

and it can be estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes power dissipated in the input stage (P_{GDQ_IN}

)

as well as the quiescent power dissipated in the output stage (P_{GDQ_OUT}) when operating with a certain

switching frequency under no load. P_{GDQ_IN}is determined by I_Fand V_Fand is given by 方程式 5. The P_{GDQ_OUT}

parameter is measured on the bench with no load connected to V_OUTpin at a given V_CC, switching frequency,

and ambient temperature. In this example, V_CCis 15 V. The current on the power supply, with PWM switching at

10 kHz, is measured to be I_CC= 1.33 mA . Therefore, use 方程式6 to calculate P_{GDQ_OUT}

P_{GDQ _IN}= Û V_F* I_F

(5)

(6)

P_{GDQ _OUT}= V_CC* I_CC

The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of 方

程式5 and 方程式6 as shown in 方程式7

P_GDQ= P_{GDQ _IN}+ P_{GDQ _OUT}= 10 mW + 20mW = 30mW

(7)

The second component is the switching operation loss, P_GDSW, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Use 方程式 8 to calculate the total dynamic loss

from load switching, P_GSW

P_GSW= V_CC2ìQ_Gì f_SW

(8)

where

• Q_Gis the gate charge of the power transistor at V_CC

So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated

in 方程式9.

P_GSW= 15 V ì120 nC ì10 kHz = 18 mW

(9)

Q_Grepresents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change

with different testing conditions. The UCC23514 gate-driver loss on the output stage, P_GDO, is part of P_GSW

P_GDOis equal to P_GSWif the external gate-driver resistance and power-transistor internal resistance are 0 Ω,

and all the gate driver-loss will be dissipated inside the UCC23514. If an external turn-on and turn-off resistance

exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and

power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if

the source/sink current is not saturated to 4.5A/5.3A, however, it will be non-linear if the source/sink current is

saturated. Therefore, P_GDOis different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

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R_OH||R_NMOS

R_OL

GSW

GDO

R_OH||R_NMOS+ R_GON+ R_{GFET_int}R_OL+ R_GOFF+ R_{GFET_int}

(10)

(11)

In this design example, all the predicted source and sink currents are less than 4.5 A and 5.3 A, therefore, use

方程式10 to estimate the UCC23514 gate-driver loss.

18 mW

9.5À||5.1À

0.4À

GDO

I = 3.9 mW

9.5À||5.1À + 5.1À + 0À 0.4À + 10À + 0À

Case 2 - Nonlinear Pull-Up/Down Resistor:

F_Sys

R_Sys

GDO

= f_swx f4.5A x

(V_CCF V_OUT(t))dt + 5.3A x

V_OUT(t) dtj

(12)

where

• V_OUT(t)is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is

saturated for some time, this value can be simplified as a constant-current source (4.5 A at turnon and 5.3 A

at turnoff) charging or discharging a load capacitor. Then, the V_OUT(t)waveform will be linear and the T_{R_Sys}

and T_{F_Sys}can be easily predicted.

For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the P_GDOis

a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown

based on this discussion.

Use 方程式13 to calculate the total gate-driver loss dissipated in the UCC23514 gate driver, P_GD

P_GD= P_GDQ+ P_GDO= 30mW + 3.9mW = 33.9mW

(13)

(14)

9.2.2.4 Estimating Junction Temperature

Use 方程式14 to estimate the junction temperature (T_J) of UCC23514.

T_J= T_C+ Y_JTìP_GD

where

• T_Cis the UCC23514 case-top temperature measured with a thermocouple or some other instrument.

• Ψ_JTis the junction-to-top characterization parameter from the 节6.4 table.

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_θJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

The R_θJCresistance can only be used effectively when most of the thermal energy is released through the case,

such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of R_θJCwill

inaccurately estimate the true junction temperature. The Ψ_JTparameter is experimentally derived by assuming

that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the

application environment. As long as the recommended layout guidelines are observed, junction temperature

estimations can be made accurately to within a few degrees Celsius.

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9.2.2.5 Selecting V_CCCapacitor

Bypass capacitors for V_CCis essential for achieving reliable performance. TI recommends choosing low-ESR

and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature

coefficients, and capacitance tolerances. A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the

C_VCCcapacitor. If the bias power supply output is located a relatively long distance from the V_CCpin, a tantalum

or electrolytic capacitor with a value greater than 10 μF should be used in parallel with C_VCC

备注

DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V, 1-μF X7R

capacitor is measured to be only 500 nF when a DC bias of 15-V_DCis applied.

10 Power Supply Recommendations

The recommended input supply voltage (V_CC) for the UCC23514 device is from 14V to 33V. The lower limit of

the range of output bias-supply voltage (V_CC) is determined by the internal UVLO protection feature of the

device. V_CCvoltage should not fall below the UVLO threshold for normal operation, or else the gate-driver

outputs can become clamped low for more than 20 μs by the UVLO protection feature. UVLO is referenced to

COM on the UCC23514E, and to V_EEin all other versions. The higher limit of the V_CCrange depends on the

maximum gate voltage of the power device that is driven by the UCC23514 device, and should not exceed the

recommended maximum V_CCof 33 V. A local 220-nF to 10-μF bypass capacitor should be placed between the

V_CCand COM pins for the UCC23514E, or between the V_CCand V_EEpins for all other versions. TI recommends

placing an additional 100-nF capacitor in parallel with the device biasing capacitor for high frequency filtering.

Both capacitors should be positioned as close to the device pins as possible. Low-ESR, ceramic surface-mount

capacitors are recommended.

If only a single, primary-side power supply is available in an application, isolated power can be generated for the

secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such

applications, detailed power supply design and transformer selection recommendations are available in SN6501

Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for

Isolated Power Supplies data sheet.

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11 Layout

11.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the UCC23514. Some

key guidelines are:

• Component placement:

– Low-ESR and low-ESL capacitors must be connected close to the device between the V_CCand V_EEpins

to bypass noise and to support high peak currents when turning on the external power transistor.

– To avoid large negative transients on the V_EEpins connected to the switch node, the parasitic inductances

between the source of the top transistor and the source of the bottom transistor must be minimized.

• Grounding considerations:

– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area

is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of

the transistors. The gate driver must be placed as close as possible to the transistors.

• High-voltage considerations:

– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces

or copper below the driver device. A PCB cutout or groove is recommended in order to prevent

contamination that may compromise the isolation performance.

• Thermal considerations:

– A large amount of power may be dissipated by the UCC23514 if the driving voltage is high, the load is

heavy, or the switching frequency is high. Proper PCB layout can help dissipate heat from the device to

the PCB and minimize junction-to-board thermal impedance (θ_JB).

– Increasing the PCB copper connecting to the V_CCand V_EEpins is recommended, with priority on

maximizing the connection to V_EE. However, the previously mentioned high-voltage PCB considerations

must be maintained.

– If the system has multiple layers, TI also recommends connecting the V_CCand V_EEpins to internal ground

or power planes through multiple vias of adequate size. These vias should be located close to the IC pins

to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high

voltage planes are overlapping.

11.2 PCB Material

Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of

lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-

extinguishing flammability-characteristics.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLUSDV0

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC23514EDWV

UCC23514EDWVR

UCC23514MDWV

UCC23514MDWVR

UCC23514SDWV

UCC23514SDWVR

UCC23514VDWV

UCC23514VDWVR

ACTIVE

SOIC

DWV

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

23514E

1000 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

NIPDAU

23514E

23514M

23514S

23514V

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Dec-2020

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

DWV0008A

SOIC - 2.8 mm max height

SOIC

SEATING PLANE

11.5 0.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

5.95

5.75

NOTE 3

3.81

0.51

0.31

7.6

7.4

0.25

C A

2.8 MAX

NOTE 4

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

1.0

0.5

DETAIL A

TYPICAL

(2)

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

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EXAMPLE BOARD LAYOUT

DWV0008A

SOIC - 2.8 mm max height

SOIC

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DWV0008A

SOIC - 2.8 mm max height

SOIC

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC23514SDWV [TI]

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