UCC24636DBVR [TI]
具有超低待机电流的同步整流器控制器 | DBV | 6 | -40 to 125;
| 型号： | UCC24636DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有超低待机电流的同步整流器控制器 | DBV | 6 | -40 to 125 控制器 开关 光电二极管 |
| 文件： | 总36页 (文件大小：2459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
UCC24636 具有超低待机电流
的同步整流器 (SR) 控制器
1 特性
3 说明
1
•
针对 5V 至 24V 输出断续/转换模式反激转换器而优
化的二次侧 SR 控制器
UCC24636 SR 是一款紧凑型 6 引脚二次侧同步整流
器 MOSFET 控制器和驱动器，适用于在断续 (DCM)
和转换模式 (TM) 下工作的高效率反激转换器。与测量
SR MOSFET 漏极电压的传统 SR 控制器不同的
是，UCC24636 采用伏秒平衡控制方案来确定 SR
MOSFET 的关闭转换；因此，SR 导通时间与
MOSFET RDSON、寄生电感或振铃无关，这在组件选
择和 PCB 布局布线方面给予了设计人员更大的灵活
性。该控制方法可为给定的 MOSFET 实现最长的 SR
导通时间和最高的整流器效率。
•
•
通过伏秒平衡控制实现最高整流器效率
兼容一次侧同步整流器 (PSR) 和二次侧同步整流器
(SSR) 反激控制器
•
•
110µA 超低待机电流消耗
通过自动检测待机模式禁用 SR 开关以降低无负载
时的功耗
•
•
•
•
•
SR 关断与 RDSON 和寄生电感无关
工作频率高达 130kHz
宽 VDD 范围：3.6V 至 28V
自适应栅极驱动钳位
该控制器内置智能特性，可在检测到转换器中无负载运
行时自动进入待机模式。在待机模式下，它会禁用 SR
MOSFET 并将其偏置电源电流降至 110uA，从而进一
步降低总体系统待机功耗。该控制器具有较宽的 VDD
工作电压范围，允许直接从控制器输出获取偏置电压以
实现输出电压固定或可变的设计。这消除了主变压器对
辅助绕组的需求，从而简化电路设计并降低成本。
开路和短路引脚故障保护
2 应用
•
•
•
•
智能手机和平板电脑的 AC/DC 适配器
带有 Type-C 连接器的 USB 充电器
笔记本电脑和超极本适配器
工业用开关模式电源 (SMPS) 中的高效率反激转换
器
器件信息(1)
器件型号
UCC24636
封装
SOT23 (6)
封装尺寸（标称值）
•
服务器和台式机中的高效率辅助电源 应用
2.92mm x 1.30mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
栅极驱动时序与 VDS 感测 SR 驱动器间的关系
VOUT
1-mΩ RDSON MOSFET Example
15 A
CB1
CB2
NP
NS
COUT
œ
RVSC1
VAC
6
RVPC1
VDD
RVPC2
VPC
VSC
1
4
2
3
UCC28740
5 A
RVSC2
UCC24636
DRV TBLK
VDD
HV
0.85 A
Secondary
GND
5
DRV
CS
VS
FB
Current
TL431
RTBLK
GND
Gate Drive
VDS Sensing
Driver
300 ns
Gate Drive
UCC24636
5 ms
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCG2
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
目录
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
9.3 Do's and Don'ts ...................................................... 27
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements ............................................... 6
7.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 30
12.1 器件支持 ............................................................... 30
12.2 文档支持................................................................ 30
12.3 商标....................................................................... 30
12.4 静电放电警告......................................................... 30
12.5 Glossary................................................................ 30
13 机械、封装和可订购信息....................................... 30
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (December 2015) to Revision A
Page
•
已将器件状态从“产品预览”更改为“量产数据”并已发布完整数据表。 ...................................................................................... 1
2
Copyright © 2016, Texas Instruments Incorporated
UCC24636
www.ti.com.cn
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
5 Device Comparison Table
PART NUMBER
UCC24636
CCM DEAD TIME CONTROL
tOFF (µs)
FSW(MAX) (kHz)
No
4.35
2.5
130
200
UCC24630
Yes
6 Pin Configuration and Functions
DBV Package
6-Pin SOT23
Top View
1
6
5
4
VPC
VSC
TBLK
VDD
2
3
GND
DRV
Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
The Voltage during Primary Conduction pin is connected to a resistor divider from the SR MOSFET
drain. This pin determines a sample of the primary-side MOSFET volt seconds during the primary on-
time. This voltage programs a voltage controlled current source for the internal VPC ramp charging
current.
1
VPC
I
I
The Voltage during Secondary Conduction pin is connected to a resistor divider from the power-supply
output. This pin determines a sample of the secondary-side output voltage used to determine SR
MOSFET conduction time. This voltage programs a voltage controlled current source for the internal VSC
ramp charging current.
2
VSC
TIME BLANK pin is used to select the blanking time of the VPC rising edge. A programmable range from
200 ns to 2 µs is available to prevent false detection of the primary on-time due to ringing during DCM
operation.
3
4
5
6
TBLK
DRV
GND
VDD
–
O
G
P
DRIVE is an output used to drive the gate of an external synchronous rectifier N-channel MOSFET
switching transistor, with source pin connected to GND.
The GROUND pin is both the reference pin for the controller and the low-side return for the drive output.
Special care should be taken to return all AC decoupling capacitors as close as possible to this pin and
avoid any common trace length with analog signal return paths.
VDD is the bias supply input pin to the controller. A carefully placed bypass capacitor to GND is required
on this pin.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
Copyright © 2016, Texas Instruments Incorporated
3
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
30
UNIT
V
VVDD
IDRV
Bias supply voltage, VDD
–0.3
Continuous gate current sink, DRV
Continuous gate current source, DRV
Peak VPC pin current
50
mA
mA
mA
IDRV
–50
–1.2
IVPC
VDRV
VVPC, VVSC
TJ
Gate drive voltage at DRV
–0.3
–0.3
–55
Self-limiting
4.5
V
Voltage range, VPC, VSC
V
Operating junction temperature range
Lead temperature 0.6 mm from case for 10 seconds
Storage temperature
150
°C
°C
°C
TL
260
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.75
0.22
-40
MAX
UNIT
V
VVDD
Bias supply operating voltage
VDD bypass capacitor
28
CVDD
µF
°C
V
TJ
Operating junction temperature
Operating range
125
2.2
VVPC, VVSC
–0.3
7.4 Thermal Information
UCC24636
THERMAL METRIC(1)
DBV (SOT23)
UNIT
6 PINS
180
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
71.2
44
Junction-to-top characterization parameter
Junction-to-board characterization parameter
5.1
ψJB
13.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
UCC24636
www.ti.com.cn
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
7.5 Electrical Characteristics
over operating free-air temperature, VDD = 12 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
SUPPLY INPUT
IRUN
Supply current, run
IDRV = 0, run state, FSW = 0 kHz
IDRV = 0, standby mode
0.9
1.2
mA
µA
ISTBY
Supply current, standby
110
160
UNDER-VOLTAGE LOCKOUT
VVDD(on)
VVDD(off)
DRV
VDD turn-on threshold
VVDD low to high
VVDD high to low
3.9
3.3
4
4.3
3.7
V
V
VDD turn-off threshold
3.6
RDRVLS
VDRVST
VDRCL
DRV low-side drive resistance
DRV pull down in start-up
DRV clamp voltage
IDRV = 100 mA
1
2
0.95
15
Ω
V
V
VDD= 0 to 2 V, IDRV= 10 µA
VVDD = 30 V
11
13
10
VDD voltage to disable rail-to-rail
drive, VDD rising
VPMOS
Disable PMOS high-side drive
9.3
10.5
V
VDD voltage hysteresis to enable rail
to rail drive, VDD falling
VPMOS-HYS
PMOS enable hysteresis
DRV pull-up high voltage
0.75
4.6
1
1.25
5
V
V
VDRHI
VVDD = 5 V, IDRV = 15 mA
4.75
VSC INPUT
VVSCEN
SR enable voltage
SR enable hysteresis
SR disable voltage
Input bias current
VVSC > VVSCEN, VVSC rising
VVSC falling
250
300
50
340
mV
mV
mV
µA
VVSC-HYS
VVSCDIS
IVSC
220
250
0
280
0.4
VVSC = 2 V
–0.25
VPC INPUT
VVPCEN
SR enable voltage
VVPCEN < VVPC
VVPC > VVPCDIS
345
2.6
400
450
3.1
mV
V
VVPCDIS
VPC threshold to disable SR
2.85
VVPC = 0.95 V, VVPC-TH = 0.85 x VVPC
previous cycle
VVPC-TH
Threshold of VVPC rising edge
0.76
0.808
0.86
V
VVPC-TH-CLP
IVPC
Clamp threshold of VVPC rising edge
Input bias current
VVPC = 2 V
VVPC = 2 V
0.9
1
0
1.1
0.4
V
–0.25
µA
CURRENT EMULATOR
VVPC = 1.25 V, tVPC = 1 µs,
VVSC = 1.25 V
3.97
3.95
3.85
3.85
4.17
4.17
4.09
4.07
4.35
4.37
4.26
4.28
VVPC = 1.25 V, tVPC = 5 µs,
VVSC = 1.25 V
RatioVPC_VSC
KVPC/KVSC
VVPC = 2 V, tVPC = 1 µs,
VVSC = 1.25 V
VVPC = 1.25 V, tVPC = 1 µs,
VVSC = 0.45 V
Copyright © 2016, Texas Instruments Incorporated
5
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
MAX UNIT
Electrical Characteristics (continued)
over operating free-air temperature, VDD = 12 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
STANDBY OPERATION
TEST CONDITION
MIN
TYP
Number of switching cycles to enter
standby operation during tENTO
nENTO
nEN
64
32
Number of switching cycles to exit
(1)
standby operation during tEN
OVER TEMPERATURE PROTECTION
T(STOP) Thermal shutdown temperature
Internal junction temperature
165
°C
(1) The device exits standby operation as soon as nEN occurs within tEN
.
7.6 Timing Requirements
over operating free-air temperature range, VDD = 12 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
DRV
VVDD = 12 V, CL = 3.3 nF, VDRV = 2 V to 8 V
VVDD = 5 V, CL = 3.3 nF, VDRV = 1 V to 4 V
VVDD = 12 V, CL = 3.3 nF, VDRV = 8 V to 2 V
VVDD = 5 V, CL = 3.3 nF, VDRV = 4 V to 1 V
27
50
20
15
54
ns
tR
DRV high-side rise time
DRV low-side fall time
100
54
ns
50
tF
VVPC = 1 V to –0.05 V falling to DRV high,
VVDD = 12 V, VDRV = 0 V to 2 V
tDRVON
Propagation delay to DRV High
Propagation delay to DRV Low
80
65
160
95
ns
ns
tDRVOFF
Test mode
VPC INPUT
tVPC-SPL
VPC sampling time window
81
169
100
203
125
239
ns
ns
µs
RTBLK = 5 kΩ
RTBLK = 50 kΩ
Minimum VPC pulse for SR DRV
operation
tVPC-BLK
0.85
1.01
1.18
SR ON CONTROL
tSRONMIN SR minimum on time after VPC falling.
tOFF SR off blanking time from DRV falling.
STANDBY OPERATION
Time to disable SR operation, enter
300
350
425
ns
us
3.96
4.35
4.75
tENTO
Time to disable DRV
Time to enable DRV(1)
11.5
2.3
12.8
2.56
14.1
2.82
ms
ms
standby
Time to enable SR operation, exit
standby operation
tEN
(1) The device exits standby operation as soon as nEN occurs within tEN
.
6
Copyright © 2016, Texas Instruments Incorporated
UCC24636
www.ti.com.cn
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
7.7 Typical Characteristics
VVDD = 12 V, TJ = 25°C, unless otherwise noted.
4.75
4.63
4.50
4.38
4.25
4.13
4.00
3.88
3.75
3.63
3.50
3.38
3.25
150
140
130
120
110
100
90
VVDD(On)
VVDD(Off)
80
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
Temperature (oC)
Temperature (oC)
C001
C002
Figure 1. VDD Turn-On and Turn-Off Threshold vs
Temperature
Figure 2. Standby Current vs Temperature
500
475
450
425
400
375
350
325
300
400
375
350
325
300
275
250
225
200
0
25
50
75
100
125
150
œ50
œ25
-50
-25
0
25
50
75
100
125
150
Temperature (oC)
C004
Temperature (C°)
Figure 4. VSC Enable Threshold vs Temperature
Figure 3. VPC Enable Threshold vs Temperature
4.60
4.50
4.40
4.30
4.20
4.10
4.00
3.90
3.80
3.70
4.80
4.60
4.40
4.20
4.00
3.80
3.60
3.40
0
25
50
75
100
125
150
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
œ50
œ25
Temperature (oC)
VVPC (V)
C005
C006
VVPC = 1.25 V
tVPC = 1 µs
VVSC = 1.25 V
VVSC = 1.25 V
tVPC × VVPC = 3 V-µs
Figure 5. VPC-to-VSC Ramp Gain Ratio vs Temperature
Figure 6. VPC-to-VSC Ramp-Gain Ratio vs VPC Voltage
Copyright © 2016, Texas Instruments Incorporated
7
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Typical Characteristics (continued)
VVDD = 12 V, TJ = 25°C, unless otherwise noted.
4.8
300
280
260
240
220
200
180
160
140
120
100
4.6
4.4
4.2
4.0
3.8
3.6
3.4
0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7
0
25
50
75
100
125
150
œ50
œ25
Temperature (oC)
VVSC (V)
C007
C009
VVPC = 1.25 V
tVPC = 2 µs
RTBLK = 5 kΩ
Figure 7. VPC-to-VSC Ramp-Gain Ratio vs VSC Voltage
Figure 8. VPC Blanking Time vs Temperature (Minimum
Setting)
400
390
380
370
360
350
340
330
320
310
300
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
Temperature (oC)
Temperature (oC)
C014
C010
RTBLK = 50 kΩ
Figure 10. DRV Minimum On Time vs Temperature
Figure 9. VPC Blanking Time vs Temperature (Maximum
Setting)
5.5
5.25
5
4.75
4.5
4.25
4
3.75
3.5
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
D013
Figure 11. DRV Minimum Off Time vs Temperature
8
Copyright © 2016, Texas Instruments Incorporated
UCC24636
www.ti.com.cn
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
8 Detailed Description
8.1 Overview
The UCC24636 SR controller is targeted for flyback converters operating in DCM and TM modes of operation.
The control method to determine SR on time is based on the volt-second balance principle of primary and
secondary conduction volt-second product. In converters operating in DCM and TM, the secondary current
always returns to zero in each cycle. The inductor charge voltage and time product is equal to the discharge
voltage and time product. The device uses internal current ramp emulators to predict the proper SR on time
based on voltage and time information on the VPC and VSC pins.
To achieve very low standby power in the converter, the UCC24636 has a standby mode of operation that
disables the SR MOSFET drive and reduces the device bias current to ISTBY. The device monitors the average
switching frequency of the converter to enter and exit the standby mode of operation, and is compatible with
converters operating in burst mode or constant frequency in light-load mode.
8.2 Functional Block Diagram
Thermal
SD
VPC
Thresh
S&H
VPC
UVLO
4.0/3.6 V
VDD
+
SR Control Bias
+
Bias
VVPCEN
Fsw Detect
Stand By
Stand By
tVPC-BLK
VPC
Blanking
Timer
VPC
Min tOFF
TBLK
DRV
GND
S
Q
Q
SRon
Min tON
R
SR_On
Detect
+
DRV
Enable
+
Ramp
Enable
VVSCEN
VPC Ramp
VSC Ramp
VSC
One
Shot
+
+
Copyright © 2016, Texas Instruments Incorporated
9
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
8.3 Feature Description
8.3.1 Start Up and UVLO
The UCC24636 features a wide operating VDD range and low UVLO thresholds. The start up of the device is
dependent on voltage levels on three pins: VDD, VPC and VSC. The VDD pin can be directly connected to the
power supply output on converters from 5-V to 24-V nominal outputs. The start UVLO threshold is VVDD(on), 4.0 V
typical, and stop threshold is VVDD(off), 3.6 V typical. The DRV output is not enabled unless the voltage on the
VPC pin is greater than VVPCEN for a time longer than tVPC-BLK and the voltage on the VSC pin is greater than
VVSCEN. Once the VDD, VSC and VPC voltage and time thresholds are met, there is an internal initialization time
before the DRV output is enabled.
Refer to Figure 12 for a startup sequence that illustrates the timing sequence and configurable DRV output
based on VDD level. In most converter designs, the conditions for the VPC and VSC voltage to enable the
device are met before the VDD start-voltage threshold, this is reflected in the timing diagram. When VDD
exceeds VVDD(on) UVLO threshold the device starts the initialization sequence of 150 µs to 250 µs illustrated as
tINITIALIZE. After the device initialization, there is a logic initialization of 20 µs at which time VTBLK is enabled (high).
At VDD < VPMOS the driver high-side PMOS device is enabled and the DRV peak will be close to VDD. When
VDD exceeds VPMOS the PMOS device is disabled and the driver is operating as a high-side NMOS only and
DRV is approximately 1.2 V to 1.5 V lower than VDD. As VDD continues to increase, the DRV output is limited to
VDRCL regardless of VDD up to the recommended maximum rating.
VPMOS
VVDD
VVDD(on)
tINITIALIZE
20 µs
VTBLK
VVPC
VDRCL
VDRV
t
Figure 12. Start-Up Operation
10
Copyright © 2016, Texas Instruments Incorporated
UCC24636
www.ti.com.cn
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
Feature Description (continued)
8.3.2 Volt-Sec SR Driver On-Time Control
Refer to the timing diagrams in Figure 13 for functional details of the UCC24636 volt-sec on-time control.
VIN/NPS
Pri Volt-Sec
VOUT
SR VDS
Sec Volt-
Sec
VVPC Pk
VVPC-TH (0.85 VVPC Pk)
VVPC
VVPCEN
DRV
ramp EN
Enable
Primary
MOSFET
Primary
MOSFET
Primary Drive
and VDRV
DRV
DRV
tVPC-BLK
VPC Blanking Time
VPC Sample Time
tVPC-SPL
tOFF
DRV Inhibit
tOFF
tOFF
VPC Ramp
VPC Ramp
V/s Control
Ramps
VSC Ramp
VSC Ramp
Normalized Pri
and Sec Current
IPRI
ISEC/NPS
tVSC TH
IPRI
ISEC/NPS
tPRI
tSEC DIS
Figure 13. Operation in DCM
Copyright © 2016, Texas Instruments Incorporated
11
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Feature Description (continued)
The UCC24636 uses the VPC and VSC pins to sense the SR MOSFET VDS voltage and converter VOUT voltage
through resistor dividers. The information of VIN/NPS, tPRI, and VOUT can be obtained from the information on VPC
and VSC pins. The SR MOSFET turn on is determined when the SR MOSFET body diode starts conducting and
the VPC pin voltage falls to near zero; the SR MOSFET turn off is determined by the current emulator control
ramps.
The UCC24636 volt-sec control generates the internal VPC ramp and VSC ramp to emulate the transformer Volt-
Sec balancing as shown in Figure 13.
The secondary current discharge time, tSEC-DIS can be determined indirectly. The primary volt-sec ramp and
secondary volt-sec ramp both start when VPC rises above VVPC-EN and VVPC-TH. The charge currents for the VPC
and VSC ramps are determined by the voltage on the VPC and VSC pins respectively.
When VPC is higher than VVPC-EN and VVPC-TH for t > tVPC-BLK, the VPC pulse is qualified as a primary conduction
pulse and the SR can be enabled on the VPC falling edge. The VPC ramp continues to rise until the VPC falling
edge based on the real time voltage on the VPC pin and holds the peak for the cycle. The DRV output is turned
on during the VPC falling edge near zero volts, and DRV is turned off when the VSC rising ramp crosses the
VPC ramp held level.
Both VPC and VSC ramps are reset to zero on each VPC rising edge above the VVPC-EN and VVPC-TH thresholds.
To discriminate primary on-time pulses from DCM ringing, there are voltage and time criteria that must be
satisfied on the VPC pin to enable the DRV output. tVPC-BLK can be adjusted through the resistor on TBLK pin.
At the rising edge of VPC when the voltage exceeds VVPC-EN and VVPC-TH the blanking time tVPC-BLK is initiated. At
the end of tVPC-BLK, the VPC voltage is sampled during tVPC-SPL window, which is 100 ns nominal. Also at the end
of tVPC-BLK, the DRV output can be enabled.
The VPC voltage sampled during tVPC-SPL determines the VPC dynamic threshold VVPC-TH which is normally 85%
of the sampled VPC voltage. The dynamic threshold provides the ability to reject the DCM ringing and detect the
primary on-time. Noise immunity during the turn-on event of DRV at the falling edge of the VPC pin is enhanced
by a minimum DRV on time of tSRONMIN, which is 350 ns nominal.
During the falling edge of DRV, the tOFF timer is initiated which inhibits turn on of the SR until tOFF expires. This
eliminates false turn on of DRV if the DCM ringing is close to ground.
12
Copyright © 2016, Texas Instruments Incorporated
UCC24636
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ZHCSES5A –MARCH 2016–REVISED MARCH 2016
Feature Description (continued)
The UCC24636 is designed to operate in a variety of flyback converter applications over a wide operating range.
The internal volt-sec control ramps do have a dynamic range limit based on volt-sec on the VPC pin. As shown
in Figure 14, a Volt-sec product exceeding 7 V-µs on the VPC pin will result in saturation of the VPC volt-sec
control ramp. Operation beyond this point results in a DRV on-time less than expected. For example, if VVPC
=
0.5 V, tVPC should be < 14 µs, or if VVPC = 2.0 V, tVPC should be < 3.5 µs, to operate within the dynamic range of
the device. Assuming a converter operating in transition mode at low line and full load with a 50% duty cycle, the
operating period is 28 µs which results in a frequency that is under 40 kHz. The UCC24636 low-frequency
operating range extends to the standby mode threshold of 5 kHz; but each switching cycle VVPC Volt-sec product
should be less than 7 V-µs.
The device can support switching frequencies exceeding 130 kHz but the following timing limits need to be
confirmed to be compatible with the power train. The minimum primary on time when the device is expected to
be active needs to be compatible with the minimum VPC blanking time (tVPC-BLK) setting of 203 ns plus the
sampling window (tVPC-SPL) of 100 ns. The minimum secondary current conduction time should be greater than
the minimum SR on time (tSRONMIN) of 350 ns. The minimum time from the SR drive turn off until the next SR
drive turn on should be greater than the SR minimum off time (tOFF) of 4.35 µs.
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
VPC V-us (uWb)
C008
Figure 14. RatioVPC_VSC vs VPC V-µs
IOUT
VOUT
bs
VSEC
RVSC1
ë55
RVPC1
RVPC2
ë{/
ët/
5wë
COUT
RPL
UCC24636
RVSC2
Ç.[Y
Db5
RTBLK
GND
Figure 15. SR Controller Components
Copyright © 2016, Texas Instruments Incorporated
13
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Feature Description (continued)
Determining the VPC and VSC divider resistors is based on the operating voltage ranges of the converter and
RatioVPC-VSC gain ratio. Referring to Figure 15, the following equation determines the VPC divider values.
For RVPC2, a value of 10 kΩ is recommended for minimal impact on time delay, and low-resistor dissipation. A
higher RVPC2 value reduces resistor divider dissipation but may increase the DRV turn-on delay due to the time
constant of ~2 pF pin capacitance and divider resistance. A lower RVPC2 value can be used with the tradeoff of
higher dissipation in the resistor divider. A factor of 10% over the VPC threshold, VVPCEN, is shown in Equation 1
for design margin.
é
ê
ë
ù
V
æ
ö
÷
ø
IN(min)
+ VOUT(min) - V
´1.1 ´R
ú
ç
÷
VPCEN
VPC2
ç
NPS
ê
ú
û
è
RVPC1
=
VVPCEN ´1.1
where
•
•
•
•
VIN(min) is the converter minimum primary bulk capacitor voltage.
VOUT(min) is the minimum converter output voltage in normal operation.
VVPCEN is the VPC enable threshold, use the specified maximum value.
NPS is the transformer primary to secondary turns ratio.
(1)
The operating voltage range on the VPC pin should be within the range of 0.45 V < VVPC < 2.2 V. Referring to
Figure 6, if VVPC is greater than 2.3 V the linear dynamic range is exceeded and RatioVPC_VSC is reduced; in this
condition the DRV on time is less than expected. If VVPC is greater than 2.6 V for 500 ns, a fault is generated and
DRV is disabled for the cycle, refer to Pin Fault Protection. To ensure the maximum voltage is within range
confirm with Equation 2.
V
æ
ç
è
ö
IN(max)
+ VOUT(max) ´R
÷
VPC2
NPS
ø
VVPC(max)
=
RVPC1 + RVPC2
where
•
•
•
VIN(max) is the converter maximum primary bulk capacitor voltage.
VOUT(max) is the maximum converter output voltage at OVP.
NPS is the transformer primary-to-secondary turns ratio.
(2)
The program voltage on the VSC pin is determined by the VPC divider ratio and the device's parameter
RatioVPC_VSC. The current emulator ramp gain is higher on the VPC pin by the multiple RatioVPC_VSC, so the VSC
resistor divider ratio is reduced by the same RatioVPC_VSC accordingly. Determine the VSC divider resistors using
Equation 3 below. To minimize resistor divider dissipation, a recommended range for RVSC2 is 25 kΩ to 50 kΩ.
Higher RVSC2 values results in increasing offset due to VSC input current, IVSC. Lower RVSC2 values increases the
resistor divider dissipation. To ensure DRV turn off slightly before the secondary current reaches zero, 10%
margin is shown for initial values. Use a nominal value of 4.15 for RatioVPC_VSC
.
é
ê
ê
ê
ê
ë
ù
ú
RVPC1 + RVPC2
RVPC2
æ
ç
ç
ç
ö
÷
÷
÷
ú
RVSC1
=
-1 ´RVSC2
ú
ú
û
RatioVPC _ VSC ´1.1
ç
÷
è
ø
where
•
RatioVPC_VSC is the device parameter VPC and VSC gain ratio, use a value of 4.15.
(3)
14
Copyright © 2016, Texas Instruments Incorporated
UCC24636
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ZHCSES5A –MARCH 2016–REVISED MARCH 2016
Feature Description (continued)
The operating voltage on the VSC pin should be within the range of 0.3 V < VVSC < 2.2 V. Referring to Figure 7, if
VVSC is greater than 2.3 V, the linear dynamic range is exceeded and RatioVPC_VSC is increased; in this condition
the DRV on time is more than expected, resulting in possible negative current conduction. To ensure the VSC
voltage is within range, confirm with Equation 4 and Equation 5.
RVSC2
´ VOUT(min) ³ 0.3V
R
VSC1 + RVSC2
(4)
RVSC2
´ VOUT(max) £ 2.2V
R
VSC1 + RVSC2
where
•
•
VOUT(min) is the minimum converter output operating voltage of the SR controller.
VOUT(max) is the maximum converter output operating voltage of the voltage at OVP.
(5)
Discrimination of ringing during DCM operation from valid primary on-time is achieved by a dynamic VPC rising
threshold and programmable blanking time. The dynamic threshold VVPC-TH is 85% typical ratio of the previous
VPC pin peak voltage. Referring to Figure 13, the VPC pin voltage is sampled after the VPC voltage is greater
than VVPCEN and VVPC-TH for t > tVPC-BLK. The function of the dynamic threshold VVPC-TH is to reject the ringing in
DCM operation from the primary conduction pulses. The dynamic threshold has an active range from the
minimum VVPCEN voltage to a maximum of 1-V clamp. The blanking time is programmable from 200 ns to 2 µs in
order to accommodate a variety of converter designs.
Refer to Figure 16 for guidance on selecting the blanking time. The blanking time should be selected as long as
reasonable and still accommodate the minimum primary on-time at light-load condition and high-line voltage. In
the high-line minimum load condition, select a blanking time that meets the following criteria (Equation 6) to
accommodate tolerance of the blanking time and the tVPC-SPL sampling time window.
tVPC-BLK = (tPRI x 0.85) – 120 ns
(6)
For rejection of DCM ringing, the blanking time should be longer than the time that the ring is above the VVPC-TH
dynamic threshold, which is 85% of the minimum SR VDS peak voltage. Determine these criteria at low line and
maximum load condition. It is recommended that the transformer turns ratio be selected such that the secondary
reflected voltage is < 85% of VIN(min) bulk capacitor voltage at the highest load when DCM operation occurs at the
low line input condition.
To determine the resistor value for tVPC-BLK use Equation 7 to select from a range of 200 ns to 2 µs.
tVPC-BLK -100 ns
=
RTBLK
18 pF
where
•
tVPC-BLK is the target blanking time.
(7)
Additional discrimination for proper SR timing control is provided by the tOFF function. Refer to Figure 13 for the
timing details. After the DRV turn off, the DRV is inhibited from turning on again until the tOFF timer expires. This
protects against SR false turn on from SR VDS DCM ringing below ground.
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Feature Description (continued)
High Line Minimum Load
Low Line Maximum Load
Vout
SR VDS
VVPC-TH (1V)
VPC Pk
VVPC-TH (0.85 X VPC Pk)
VVPC
tVPC-BLK
tVPC-BLK
tVPC-BLK
tVPC-SPL
tVPC-SPL
t
tVPC-BLK
tPRI
Figure 16. VPC Blanking Time Criteria
16
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UCC24636
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ZHCSES5A –MARCH 2016–REVISED MARCH 2016
Feature Description (continued)
8.3.3 Standby Operation
To minimize power consumption at very light load and standby conditions, the UCC24636 disables the SR DRV
output and enters a low current operating state. The criteria for operating in standby mode or normal operation
are determined by the average frequency detected on the VPC pin. The frequency detection is compatible with
burst mode operation or continuous low frequency FM operation. At start up the device is in normal operation to
enable DRV to the SR MOSFET. If < 64 cycles occur in tENTO,12.8 ms typical, the device disables the DRV
output and enters low-current operating mode with bias current of ISTBY. In standby mode the criteria to enter
normal operating mode is when > 32 cycles occur within tEN, 2.56 ms typical. The device enters normal operation
as soon as the 32 cycles occur to reduce the response time exiting standby operation. The average frequency of
entering standby mode is 5 kHz typical, and the average frequency of exiting standby mode is 12.5 kHz typical.
Refer to Figure 17 for an illustration of standby mode timing.
Fsw Averaging
tEN
tEN
tENTO
tENTO
Window
> 32 cycles
<64 cycles during tENTO
VPC Cycle Detect
Constant Fsw
Burst example
VPC Cycle Detect
Burst Mode
SB Mode Enable
SR Driver Disabled
SR Driver Enabled
Figure 17. Standby Mode Operation
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Feature Description (continued)
8.3.4 Pin Fault Protection
The UCC24636 controller includes fault protection in the event of open pin, shorted pin to ground and abnormal
out of range operation.
8.3.4.1 VPC Pin Overvoltage
In the event that there is an abnormal high level on the VPC pin for a period beyond expected transformer
leakage spike duration, the DRV output is disabled on a cycle-to-cycle basis. If the voltage on the VPC pin
exceeds VVPCDIS, 2.6 V minimum, for 500 ns the SR is not enabled until the next valid cycle.
8.3.4.2 VPC Pin Open
In the event of an open circuit VPC pin, the device defaults to a zero VPC input signal condition which results in
disabling DRV operation.
8.3.4.3 VSC Pin Open
In the event of an open circuit VSC pin, the device defaults to a zero VSC input signal condition which results in
disabling DRV operation.
8.3.4.4 TBLK Pin Open
In the event of an open circuit TBLK pin, the device disables DRV operation.
8.3.4.5 VPC and VSC Short to Ground
Since the VPC and VSC enable thresholds must be satisfied for DRV operation, DRV is inherently disabled.
8.3.4.6 TBLK Pin Short to Ground
A shorted TBLK pin results in a minimum setting for tVPC-BLK blanking time.
18
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UCC24636
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ZHCSES5A –MARCH 2016–REVISED MARCH 2016
8.4 Device Functional Modes
According to VDD voltage, VSC voltage, and VPC voltage and frequency, the device can operate in different
modes.
8.4.1 Start-Up
During start-up when VDD is less than VVDD(on) the device is disabled. When VDD exceeds the VVDD(on) UVLO
threshold the IDD goes to IRUN and the device begins the start sequence detailed in Start Up and UVLO.
8.4.2 Normal Operation
When VDD exceeds VVDD(on), the VPC voltage exceeds VVPC-EN and VVPC-TH, and the VSC voltage exceeds
VVSCEN the DRV output is active. If the switching frequency is above the standby criteria of > 5 kHz the device is
in normal operation determining the DRV time based on volt-sec control. IDD will be IRUN
.
1. The device operates in volt-sec control based on the VPC and VSC volt-sec control ramps.
8.4.3 Standby Operation
If the number of VPC pulses is less than nENTO, 64, during tENTO the device enters standby mode. DRV operation
stops and most device functions are shut down. IDD is ISTBY during standby operation. To exit standby mode the
number of VPC pulses must exceed nEN, 32, during tEN. IDD returns to IRUN and the DRV output starts after the
initialization time as outlined in Figure 12.
8.4.4 Conditions to Stop Operation
The following conditions can disable DRV operation; IDD is IRUN during these conditions.
1. VPC overvoltage: When VVPC > VVPCDIS for >500 ns the DRV output is disabled for the cycle.
2. VSC undervoltage: When VVSC < VVSCEN, the DRV output is disabled.
3. VPC undervoltage: When VVPC< VVPCEN, the DRV output is disabled.
Copyright © 2016, Texas Instruments Incorporated
19
UCC24636
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC24636 is a high performance controller driver for N-channel MOSFET power devices used for
secondary-side synchronous rectification. The UCC24636 is designed to operate as a companion device to a
primary-side controller to help achieve efficient synchronous rectification in switching power supplies. The
controller features a high-speed driver and provides appropriately timed logic circuitry that seamlessly generates
an efficient synchronous rectification system. With its current emulator architecture, the UCC24636 has enough
versatility to be applied in DCM and TM operation. The UCC24636 SR on-time adjustability allows optimizing for
PSR and SSR applications. Additional features such as pin fault protection, dynamic VPC threshold sensing, and
voltage sense blanking time and make the UCC24636 a robust synchronous controller.
9.2 Typical Application
9.2.1 AC-to-DC Adapter, 5 V, 15 W
This design example describes the design of a 15-W off-line flyback converter providing 5 V at 3-A maximum
load and operating from a universal AC input. The design uses the UCC28740 AC-to-DC valley-switching
primary-side controller in a DCM type flyback converter and achieves over 86% full-load efficiency with the use of
the secondary side UCC24636 synchronous rectifier controller.
•
•
The design requirements are detailed in Design Requirements
The design procedure for selecting the component circuitry for use with the UCC24636 is detailed in
Calculation of Component Values.
•
Test results shown in Application Waveforms And Curves highlight the unique advantages of using the
UCC24636.
20
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UCC24636
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ZHCSES5A –MARCH 2016–REVISED MARCH 2016
L1
F1
7447462471
L2
VOUT
39213150000
D1
MDB6S
T1
1
L3
RLTI-1081
806µH
2
1
-
+
R1
100k
C1
330pF
R2
330k
10
9
2
5
C6
0.1µF
R4
100k
C2
12µF/400V
C3
12µF/400V
C4
680µF
C5
680µF
7
8
C7
R5
20
N1
R6
150
1000pF
4
750342752
L4
950 ohm
R7
150
GND
1,2,3
7,8
5,6,
GND
Q1
CSD18503
D5
BAS20HT1
GND
GND
D3
D4
DFLR1600-7
R9
147k
R31
130
VAUX
R8
2.0
BAS20HT1
R10
0
R12
68k
R13
10
R11
115k
U3
VPC
1
6
4
VDD
DRV
R14
Q2
AOD7N65
U4
VDD
1
1
2
3
4
8
0
HV
VS
FB
R15
1.5k
6
5
2
5
DRV
CS
VSC
GND
D6
DFLZ27-7
27V
3
GND
TBLK
UCC28740DR
UCC24636
R17
39k
C8
10µF
R18
20.0k
R19
1.0
R20
2.0
R21
10k
C9
NP
R22
20k
C10
1µF
C11 R23
220pF 47k
C12
100pF
GND
GND
R24
1.00k
R27
10.0k
GND
U5
GND
C13
R25
22k
C14
NA
NA
4
3
1
2
R26
2.00k
C15
R28
100k
0.022µF
TCMT1107
U6
TL431AIDBZR
R29
10.0k
C16
1µF
GND
Figure 18. AC-to-DC Charger: 5 V, 15 W
Copyright © 2016, Texas Instruments Incorporated
21
UCC24636
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www.ti.com.cn
9.2.2 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Performance Specifications AC-to-DC Charger 5 V, 15 W
PARAMETER
INPUT CHARACTERISTICS
VACIN Input voltage
fLINE
TEST CONDITIONS
MIN
NOM
MAX
UNIT
90
47
115/230
50/60
72
265
64
VRMS
Hz
Frequency
VAC(uvlo)
VAC(run)
IIN
Brownout voltage
Brownout recovery voltage
Input current
IOUT = IOUT(nom)
VRMS
VRMS
mA
85
VACIN = VACIN(min), IOUT = IOUT(nom)
335
OUTPUT CHARACTERISTICS
VACIN = VACIN(min) to VACIN(max)
IOUT = 0 to IOUT(nom)
,
VOUT
Output voltage
4.9
5.0
5.1
V
IOUT(nom)
IOUT(min)
Nominal output current
Minimum output current
VACIN = VACIN(min) to VACIN(max)
VACIN = VACIN(min) to VACIN(max)
3.0
0
A
A
VACIN = VACIN(min) to VACIN(max)
IOUT = 0 to IOUT(nom)
,
ΔVOUT
Output voltage ripple
80
15
mV
W
POUT
Output power
VACIN = VACIN(min), IOUT = IOUT(nom)
SYSTEM CHARACTERISTICS
ηavg
ƞ10%
PNL
Average efficiency
10% Load efficiency
No load power
VACIN = VACIN(nom), IOUT = 25%, 50%, 75%, 100% of IOUT(nom)
VACIN = VACIN(nom), IOUT = 10% of IOUT(nom)
VACIN = VACIN(nom), IOUT = 0
85%
87%
82.5%
14
73.5%
22
mW
22
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UCC24636
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ZHCSES5A –MARCH 2016–REVISED MARCH 2016
9.2.3 Calculation of Component Values
IOUT
VOUT
bs
R11
VSEC
ë55
UCC24636
Db5
R9
R21
ë{/
ët/
5wë
COUT
RPL
R23
Ç.[Y
R22
GND
Figure 19. UCC24636 Circuit Design
For ease of understanding, Figure 19 is a modified version of Figure 15 where the component reference
designators are the same as the schematic drawing of Figure 18.
9.2.3.1 VPC Input
For designs operating in constant current (CC) with low VOUT, there are two cases to examine. At maximum
power, VIN(MIN) will be lower but VOUT is nominal. In constant current operation, VOUT is the minimum but VIN(MIN)
will be higher. Determine R9 for both conditions, and choose the lowest value.
For minimal power dissipation, select:
R21=10kꢀ
Nominal VOUT, maximum power, minimum V case
IN
»
…
…
ÿ
V
≈
’
IN(min) +VOUT -V
×1.1 ×R21
Ÿ
∆
∆
÷
VPC_EN
÷
NPS
Ÿ
⁄
«
◊
R9=
VVPC_EN×1.1
VOUT=5V
NPS=15
VIN(min)=65V
VVPC_EN=0.45V
R9 = 179 kꢀ
(8)
Copyright © 2016, Texas Instruments Incorporated
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UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Minimum VOUT, constant current operation case
»
…
…
ÿ
V
≈
’
IN(min)CC +VOUT(min) -V
×1.1 ×R21
Ÿ
∆
∆
÷
VPC_EN
÷
NPS
Ÿ
⁄
«
◊
R9=
VVPC_EN×1.1
VOUT(min)=1.8V
IN(min)CC=89V
R9 = 146 kꢀ
Select standard value based on 146 kꢀ result.
With R9 = 147 kΩ :
V
(9)
V
IN(max)
(
+ VOUT(max) )ìR21
R9 + R21
NPS
VVPC(max)
=
VVPC(max) = 1.95V
(10)
Therefore, VVPC is within the recommended range of 0.45 V to 2.2 V.
24
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UCC24636
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ZHCSES5A –MARCH 2016–REVISED MARCH 2016
9.2.3.2 VSC Input
The value of R23 is recommended to be with the range of 25 kΩ to 50 kΩ.
There is a 10% margin included for the initial value calculation of R11 to provide timing margin during initial
operation verification.
R23 = 47 kW
é
ê
ê
ê
ù
R9 + R21
æ
ç
ç
ö
÷
÷
ú
R9
R11=
-1 ´R23
ú
Ratio
´1.1
ú
ç
÷
VPC _ VSC
ç
÷
ê
ú
è
ø
ë
û
R11= 115 kW
(11)
With R11 = 115 kΩ, the operating range of the VSC pin is:
R23
»
ÿ
VVSC(min) = (
) ì VOUT(min)
…
Ÿ
R11+ R23
⁄
VVSC(min) = 0.52V
(12)
(13)
R23
R11+ R23
»
ÿ
VVSC(max) = (
) ì VOUT(max)
…
Ÿ
⁄
VVSC(max) = 1.74V
Therefore, VVSC is within the recommended range of 0.3 V to 2.2 V.
The UCC24636 SR timing can be optimized (SR on time increased) by increasing the R115 value after initial
operation confirmation. The RatioVPC_VSC parameter has a positive tolerance of 5.3%. Using 1% divider resistors
for VPC and VSC should allow reducing the 10% initial SR timing margin.
9.2.3.3 TBLK Input
The blanking time is set with resistor R22.
Select the blanking time to meet the following criteria based on 660-ns minimum primary on-time at high line.
tVPC-BLK = (tPRI × 0.85) – 120 ns
spacer
tVPC-BLK -100 ns
R22 =
18 pF
(14)
A value of R22 = 20 kΩ results in a blanking time of approximately 460 ns.
Copyright © 2016, Texas Instruments Incorporated
25
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
9.2.4 Application Waveforms And Curves
CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div
CH3 (Mag): VOUT, 2V/Div
CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div
CH3 (Mag): VOUT, 2V/Div
CH4 (Green): DRV signal to Q1, 10V/Div
CH4 (Green): DRV signal to Q1, 10V/Div
Figure 20. DRV Timing at 115 VAC, 5 V, 3 A
Figure 21. DRV Timing at 230 VAC, 5 V, 3 A
CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div
CH3 (Mag): VOUT, 2V/Div
CH2 (Blue): Drain of synchronous rectifier Q1, 10V/Div
CH3 (Mag): VOUT, 2V/Div
CH4 (Green): DRV signal to Q1, 10V/Div
CH4 (Green): DRV signal to Q1, 10V/Div
Figure 22. DRV Timing at 115 VAC, 5 V, 300 mA
Figure 23. DRV Timing at 115 VAC, 1.8 V, 3.3 A
90
88
86
84
82
80
78
76
74
5.5
5
4.5
4
3.5
3
2.5
2
1.5
90 VAC
1
0.5
0
115 VAC
230 VAC
264 VAC
115 VAC
230 VAC
72
70
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
3.3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Output Current (A)
3
3.3 3.6
Figure 24. Efficiency vs Output Current
Figure 25. Output Voltage vs Output Current
26
Copyright © 2016, Texas Instruments Incorporated
UCC24636
www.ti.com.cn
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
9.3 Do's and Don'ts
•
Do operate the device within the recommended operating maximum parameters. Consider output overvoltage
conditions when determining stress.
•
•
Do consider the guideline for setting the blanking time resistor value illustrated in Figure 16.
Do not use the UCC24636 in CCM flyback converter designs. For CCM designs, use the UCC24630 with the
CCM dead time control function.
•
•
•
Do not use the UCC24636 in LLC converters as they can operate in CCM.
Do not add capacitance to the TBLK pin.
Do not add significant external capacitance to the VPC pin as there will be increased delay of the signal. If
filtering is necessary a recommended maximum capacitance is 15 pF with a lower resistor divider network
value of 10 kΩ.
10 Power Supply Recommendations
The VDD operating range allows direct connection to converter outputs from 5 V to 24 V. Since the driver and
control share the same VDD and ground, it is recommended to place a good quality ceramic capacitor as close
as possible to VDD and GND pins. To reduce VDD noise and eliminate high-frequency ripple current injected
from the converter output, it is recommended to place a small resistance of 2.2 Ω to 10 Ω between the converter
output and VDD. The device can tolerate VDD rise times from 100 µs to very long rise times typical of constant
current chargers. The start-up sequence will always be as shown in Figure 12. VDD can be connected to an
external bias to extend the device's operating range to be compatible with converter output voltages below 3.5 V
or above 24 V.
Copyright © 2016, Texas Instruments Incorporated
27
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
In general, try to keep all high current loops as short as possible. Keep all high current/high frequency traces
away from other traces in the design. If necessary, high-frequency/high-current traces should be perpendicular to
signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce noise pick up.
Always consider appropriate clearances between the high-voltage connections and any low-voltage nets.
11.1.1 VDD Pin
The VDD pin must be decoupled to GND with good quality, low ESR, low ESL ceramic bypass capacitors with
short traces to the VDD and GND pins. To eliminate high-frequency ripple current in the SR control circuit, it is
recommended to place a small value resistance of 2.2 Ω to 10 Ω between VDD and the converter output voltage.
11.1.2 VPC Pin
The trace between the resistor divider and the VPC pin should be as short as possible to reduce/eliminate
possible noise coupling. The lower resistor of the resistor divider network connected to the VPC pin should be
returned to GND with short traces. Avoid adding any significant external capacitance to the VPC pin so that there
is no delay of signal. If filtering is necessary a recommended maximum capacitance is 15 pF with a lower resistor
divider network value of 10 kΩ. Avoid high dV/dt traces close to the VPC pin and connection trace such as the
SR MOSFET drain and DRV output.
11.1.3 VSC Pin
The trace between the resistor divider and the VSC pin should be as short as possible to reduce/eliminate
possible noise coupling. The lower resistor of the resistor divider network connected to the VSC pin should be
returned to GND with short traces. External capacitance can be added to the VSC pin for noise filtering. The
maximum capacitance consideration is a time constant of the capacitor and the resistor divider resistance that is
less than 1/4 the minimum rise time of the converter output during startup. Avoid high dV/dt traces close to the
VSC pin and connection trace such as the SR MOSFET drain and DRV output.
11.1.4 GND Pin
The GND pin is the power and signal ground connection for the controller. The effectiveness of the filter
capacitors on the signal pins depends upon the integrity of the ground return. Place all decoupling capacitors as
close as possible to the device pins with short traces. The device ground and power ground should meet at the
output bulk capacitor’s return. Try to ensure that high frequency/high current from the power stage does not go
through the signal ground.
11.1.5 TBLK Pin
The programming resistor is placed on TBLK to GND, with short traces. The value may have to be adjusted
based on the time delay required. Avoid high dV/dt traces close to the TBLK pin and connection trace such as
the SR MOSFET drain and DRV output.
11.1.6 DRV Pin
The track connected to DRV carries high dv/dt signals. Minimize noise pickup by routing the trace to this pin as
far away as possible from tracks connected to the device signal inputs, VPC, VSC, and TBLK.
28
Copyright © 2016, Texas Instruments Incorporated
UCC24636
www.ti.com.cn
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
11.2 Layout Example
版权 © 2016, Texas Instruments Incorporated
29
UCC24636
ZHCSES5A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 器件命名规则
12.1.1.1 术语定义（用于设计示例）
•
•
•
•
•
•
•
•
•
•
VIN(min) = 65V：最高功率时转换器一次侧大容量电容的最低电压
VIN(min)CC = 89V：CC 工作模式下 VOUT(min) 时转换器一次侧大容量电容的最低电压
VIN(max) = 370V：转换器一次侧大容量电容的最高电压
VOUT(min) = 1.8V：UCC24636 的最低转换器输出工作电压
VOUT(max) = 6V：UCC24636 的最高转换器输出工作电压
VVPC_EN = 0.45V：同步整流器使能电压
VVPC(max) = 2.2V：VPC 的最高线性工作电压
NPS = 15：变压器一次侧绕组与二次侧绕组匝数比
RatioVPC_VSC = 4.15：电流模拟器增益 KVPC/KVSC
tVPC_BLK：保证同步整流器正常工作的最少 VPC 脉冲
12.2 文档支持
12.2.1 相关文档ꢀ
相关文档请参见以下部分：
•
•
•
•
《使用 UCC24636EVM 二次侧同步整流器控制器二极管替代产品演示板》（文献编号：SLUUBE7）
《UCC24636 设计计算器》（文献编号：SLUC604）
《UCC24630 具有超低待机电流的同步整流控制器》（文献编号：SLUSC82）
《UCC28740 具有光电耦合器反馈的恒压、恒流反激控制器（文献编号：SLUSBF3）
12.3 商标
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC24636DBVR
UCC24636DBVT
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
U636
U636
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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