UCC256402ADDBR_技术文档

UCC256402, UCC256403, UCC256404

ZHCSJY8E –JUNE 2019 –REVISED FEBRUARY 2021

UCC25640x 具有超低可闻噪声和待机功耗的

LLC 谐振控制器

1 特性

3 说明

• 优化的低功耗模式和突发模式算法

– 具有软启动和软关断周期的突发模式

– 在空载和待机状态下最大程度降低可闻噪声

– 用于禁用突发模式的用户选项

– 光耦合器低功耗运行

UCC25640x 是一款具有集成高电压栅极驱动器的全功

能LLC 控制器。此器件设计用于与 PFC 控制器配对使

用，以使用最少的外部组件提供完整的电源系统。根据

设计，所产生的电源系统无需单独的待机功率转换器即

可满足最严格的待机功率要求。

– 效率性能超过DoE VI 级和EU CoC 2 级外部电

源标准

• 混合迟滞控制(HHC)

UCC25640x 可提供具有软启动和软关断周期的高效突

发模式，以最大限度降低待机运行时的可闻噪声。突发

功率电平和迟滞是可编程的，因此能够简化对效率和突

发模式运行的优化过程。也可通过引脚配置来禁用突发

模式。UCC25640x 使用混合迟滞控制来提供出色的线

路和负载瞬态响应特性。

– 出色的瞬态响应特性

– 从突发模式快速退出

• 强大的自适应死区时间控制

• 具有0.6A 拉电流和1.2A 灌电流能力的集成高电压

栅极驱动器

• 强大的电容区(ZCS) 规避方案

• 具有过热、输出过压、输入

欠压保护以及三级

过流保护

• 集成高电压启动功能

UCC25640x 具有一系列特性，可使 LLC 转换器的运

行得到良好控制和保护。该器件可与 UCC28056 或

UCC28064A PFC 控制器搭配使用，并结合

UCC24624 同步整流器控制器以提供完整的电源解决

方案。

器件信息

• X 电容器主动放电功能

封装尺寸（标称值）

器件型号

UCC256402

封装

2 应用

SOIC

9.9mm x 3.9mm

• 电视SMPS 电源

• 照明

UCC256403

UCC256404

• 交流/直流适配器

• 电动工具

• 医疗电源

Cr

Lr

Lm

HO

Vout

• 多功能打印机

• 企业和影院投影仪

• PC 电源

HS

VIn

BLK

VCC

BW

LO

• 游戏机电源

FB

AC Line

HV

16

HS

1

HS

HO

HB

AC Neutral

RHV

HO

15

14

CBOOT

VCC

3

4

5

6

7

8

VCC

UCC25640x

LLC

Controller

BLK

FB

BLK

FB

RVCC

GND

12

11

10

9

ISNS

VCR

BW

LO

LL/SS

BW

CSS

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSD90

UCC256402, UCC256403, UCC256404

ZHCSJY8E –JUNE 2019 –REVISED FEBRUARY 2021

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Table of Contents

7.2 Functional Block Diagram.........................................17

7.3 Feature Description...................................................18

7.4 Device Functional Modes..........................................32

8 Power Supply Recommendations................................68

8.1 VCC Pin Capacitor....................................................68

8.2 Boot Capacitor.......................................................... 68

8.3 RVCC Pin Capacitor................................................. 69

9 Layout.............................................................................70

9.1 Layout Guidelines..................................................... 70

9.2 Layout Example........................................................ 71

10 Device and Documentation Support..........................73

10.1 Documentation Support.......................................... 73

10.2 Related Links.......................................................... 73

10.3 Receiving Notification of Documentation Updates..73

10.4 Community Resources............................................73

10.5 Trademarks.............................................................73

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

Device Comparison Table..................................................3

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................6

6.4 Thermal Information ...................................................6

6.5 Electrical Characteristics ............................................6

6.6 Switching Characteristics .........................................10

6.7 Typical Characteristics.............................................. 11

7 Detailed Description......................................................15

7.1 Overview...................................................................15

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (September 2020) to Revision E (February 2021)

Page

• Updated Absolute Maximum Ratings HV, HB Input Voltage from 640 V to 700 V maximum............................. 5

Changes from Revision C (March 2020) to Revision D (September 2020)

Page

• Added update to Device Comparison Table ...................................................................................................... 3

Changes from Revision B (November 2019) to Revision C (March 2020)

Page

• 将封装说明从 SOIC (14) 更改为 SOIC...............................................................................................................1

• Changed name of Pin 2 from Missing to Removed............................................................................................ 3

• Changed name of Pin 13 from Missing to Removed ......................................................................................... 3

• Added description of BLK OVP thresholds ......................................................................................................24

• Added input over voltage protection description...............................................................................................30

• Changed R_FBto R_LL.........................................................................................................................................37

• Added update to Layout Example.....................................................................................................................71

Changes from Revision A (August 2019) to Revision B (November 2019)

Page

• 将销售状态从“预告信息”更改为“量产数据”。............................................................................................ 1

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Device Comparison Table

Device

Integrated High

Voltage Startup

Integrated X-

Capacitor

Discharge

Requires

External Bias

Supply

Burst Soft On

and Soft Off

BLK OVP

BW OVP Mode

UCC256402

UCC256402A

UCC256403

Yes

No

Yes

No

Yes

No

Restart

Latch

No

Yes

No

UCC256403A

UCC256404

No

Yes

No

Restart

Latch

UCC256404A

UCC256404B⁽¹⁾

Yes

Restart

(1) The X capacitor discharge feature of this device has not been tested by certification agency and was

qualified by similarity under the existing UCC25640x certification

5 Pin Configuration and Functions

1

HV

16

15

14

HS

HO

HB

3

4

5

6

7

8

VCC

UCC25640x

LLC

BLK

FB

Controller

RVCC

GND

12

11

10

9

ISNS

VCR

LO

LL/SS

BW

图5-1. DDB Package 16-Pin SOIC (Pins 2, 13 removed) Top View

Pin Functions

I/O

DESCRIPTION

NAME

NO.

This pin is used to sense the LLC stage input voltage level. A resistor divider should be used

to attenuate the signal before it is applied to this pin. The voltage level on this pin will

determine when the LLC converter starts/stops switching.

BLK

BW

4

I

This pin is used to sense the output voltage through the bias winding. The sensed voltage is

used for output over voltage protection. During startup, the pin is also used to program the

ratio between the two burst mode thresholds (BMT_Land BMT_H).

8

I

LLC stage control feedback input. The amount of current sourced from this pin will determine

the LLC input power level.

FB

5

I

GND

11

G

Ground reference for all signals.

High-side gate-drive floating supply voltage. The bootstrap capacitor is connected between

this pin and HS pin. A high voltage, high speed diode should be connected from RVCC to

this pin to supply power to the high-side gate-driver during the period when the low-side

MOSFET is conducting.

HB

14

I

HO

HS

15

16

O

I

High-side floating gate-drive output.

High-side gate-drive floating ground. Current return for the high-side gate-drive current.

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I/O

DESCRIPTION

NAME

NO.

HV

1

I

Connects to internal HV startup JFET. For UCC256402 and UCC256404, this pin provides

start up power for both PFC and LLC stage. This pin also monitors the AC line voltage for x-

capacitor discharge function. For UCC256403, this pin needs to be connected to ground.

Resonant current sense. The resonant capacitor voltage is differentiated with a first order

filter to measure the resonant current.

ISNS

6

9

I

The capacitance value connected from this pin to ground will impact the duration of the soft-

start period. The resistor divider connected to the pin will define the initial voltage applied on

the pin for startup. After system startup, this pin is used to program the burst mode

threshold.

LL/SS

LO

10

2

O

N/A

P

Low-side gate-drive output.

Removed

RVCC

VCC

Functional creepage and clearance

Regulated 13-V supply. This pin is used to supply the gate driver and PFC controller.

Supply input.

13

12

3

P

VCR

7

I

Resonant capacitor voltage sense.

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to GND, currents are

positive into and negative out of the specified terminal.⁽¹⁾

MIN

-0.3

MAX

700

7.2

UNIT

HV, HB

BLK, LL/SS

VCR

V

-0.55

-0.8 Internally Clamped

VCC

-0.55

-5

30

Input voltage

BW, ISNS

7.2

HB - HS (For UCC256402, UCC256402A,

UCC256403, UCC256403A, UCC256404,

UCC256404A)

-0.3

17

V

HB - HS (For UCC256404B)

DC

-0.3

25

17

V

RVCC output

voltage

DC

HB + 0.3

HS –0.3

HS –2

-0.3

HO output voltage

LO output voltage

V

Transient, less than 100 ns

DC

RVCC + 0.3

Transient, less than 100 ns

-2

Floating ground

slew rate

dV_HS/dt

I_{OUT_PULSED}

T_J

-50

-0.6

-40

50

1.2

V/ns

A

HO, LO pulsed

current

Junction

temperature range

150

Storage

temperature

range, T_stg

T_stg

-65

150

°C

Soldering, 10 second

Reflow

300

260

Lead temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, HV, HO, HS, HB

pins⁽¹⁾

±1000

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all other pins⁽¹⁾

V_(ESD)

Electrostatic discharge

±2000

±500

V

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

All voltages are with respect to GND, -40°C < T_J= T_A< 125°C, currents are positive into and negative out of the specified

terminal, unless otherwise noted.

MIN

NOM

MAX

600

26

UNIT

V

HV, HS

V_CC

Input voltage

Supply voltage

13

10

15

12

V

HB - HS

C_B

Driver bootstrap voltage

16

V

Ceramic bypass capacitor from HB to HS

Soft start pin capacitor

0.1

4.7

5

µF

nF

µF

mA

°C

C_ss

470

C_RVCC

I_RVCCMAX

T_A

RVCC pin decoupling capacitor

Maximum output current of RVCC ⁽¹⁾

Operating ambient temperature

100

125

-40

(1) Not tested in production. Ensured by characterization

6.4 Thermal Information

UCC25640x

THERMAL METRIC⁽¹⁾

D (SOIC)

14 PINS

74.7

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

30.7

31.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

4.4

31.4

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

All voltages are with respect to GND, -40°C < T_J= T_A< 125°C, VCC = 15 V, currents are positive into and negative out of the

specified terminal, unless otherwise noted.

PARAMETER

SUPPLY VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

For UCC256402, UCC256402A,

UCC256404, UCC256404A,

UCC256404B

Below this threshold, use reduced start

up current

VCC_Short

0.3

9.35

25

0.5

9.65

26

0.8

9.95

28

V

For UCC256402, UCC256402A,

VCC_ReStartJfetBelow this threshold, re-enable JFET. UCC256404, UCC256404A,

UCC256404B

For UCC256402, UCC256402A,

Startup when VCC is above this level UCC256404, UCC256404A,

UCC256404B

VCC_StartSelf

VCC_StartSwitchi

Startup when VCC is above this level For UCC256403, UCC256403A

10.9

8.25

0.25

V

ng

VCC under voltage lockout voltage

(rising)

VCC_UVLOrising

7.85

0.15

8.70

0.35

VCC under voltage lockout voltage

hysteresis

VCC_UVLOHYS

SUPPLY CURRENT

Current drawn from VCC rail during

burst off period

I_CCSleep

650

780

950

µA

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All voltages are with respect to GND, -40°C < T_J= T_A< 125°C, VCC = 15 V, currents are positive into and negative out of the

specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current drawn from VCC Pin while

gate is switching. Excluding Gate

Current

I_CCRun

Dead time = 1 µs maximum dead time

1.8

2.2

2.7

mA

REGULATED SUPPLY

Regulated supply voltage

VCC = 15 V, no load

12.7

12.4

12.7

12.4

6.5

13

13.45

V

Regulated supply voltage

VCC = 15 V, 100 mA load

VCC = 13 V, no load

V_RVCC

Regulated supply voltage

12.98

12.6

7

Regulated supply voltage

VCC = 13 V, 30 mA load

V_RVCCUVLO

RVCC under voltage lock out voltage

7.5

HIGH VOLTAGE STARTUP

I_HVLow

I_HVHigh

I_HVLeak

Reduced startup pin current

V_HV= 20 V, VCC = 0 V

V_HV= 20 V, VCC = 4 V

V_HV= 600 V

0.3

7.6

0.5

10.20

1

0.65

13.5

4

mA

µA

Full startup pin current

HV current source leakage current

For UCC256404B

1.0

1.4

1.3

1.6

2.1

mA

Highest AC zero crossing detection

test current

I_HVZCD

For UCC256404, UCC256404A

1.7

AC zero crossing detection test current

steps

I_HVZCDStep

0.38

11.5

9

mA

V

I_{XCAPDischarge}X-cap discharge current

HV pin voltage threshold that zero-

8.9

8

13.5

11

V_{zero-crossing}

crossing is detected

AC zero crossing detection window

t_XCAPZCD

length for first three test current stage

10

12

14

ms

(1)

AC zero crossing detection window

length for final test current stage ⁽¹⁾

t_XCAPZCDLast

t_XCAPIdle

t_{XCAPDischarge}

43

635

327

46

700

360

12

52

772

390

ms

AC zero crossing detection idle period

length ⁽¹⁾

Time for X-cap discharge current

active ⁽¹⁾

Time of first X-cap detection after

JFETON ⁽¹⁾

t_XCAPJFETON

BULK VOLTAGE SENSE

For UCC256402, UCC256402A,

UCC256403, UCC256403A

2.94

0.98

2.15

0.88

3.92

3.72

3

1

3.06

1.02

2.25

0.925

4.08

3.88

V

BLK voltage that allows LLC to start

switching

V_BLKStart

For UCC256404, UCC256404A,

UCC256404B

For UCC256402, UCC256402A,

UCC256403, UCC256403A

2.2

0.9

4.0

3.8

BLK voltage that forces LLC operation

to stop

V_BLKStop

For UCC256404, UCC256404A,

UCC256404B

BLK over voltage protection rising

threshold

V_BLKOVPRise

V_BLKOVPFall

For UCC256402A

BLK over voltage protection falling

threshold

FEEDBACK PIN

R_FBInternalInternal pull down resistor value

90

73

100

82

110

91

kΩ

µA

For UCC256402, UCC256402A,

UCC256404, UCC256404A,

UCC256404B

I_FB

FB internal current source

For UCC256403, UCC256403A

147

164

182

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All voltages are with respect to GND, -40°C < T_J= T_A< 125°C, VCC = 15 V, currents are positive into and negative out of the

specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FB pin voltage when FB pin sink

current is at (IFB - 50 µA)

V_FB

5.6

V

FB pin voltage variation when FB pin

sink current ranges from (IFB - 50 µA)

to (IFB - 5 µA)

0.28

V

ΔV_FB

FB pin voltage variation when FB pin

sink current ranges from (IFB - 5 µA)

to (IFB + 5 µA)

0.4

82

V

μA

V

ΔV_clamp

I_FBclamp

ΔV_FBclamp

f_-3dB

Maximum FB internal current source

when FB is clamped

FB pin voltage variation when FB pin

sink current ranges from (IFB + 5 µA)

to (IFB + IFBClamp - 5 µA)

0.25

Feedback chain -3dB cut off frequency

1

MHz

(2)

RESONANT CURRENT SENSE

V_{ISNS_OCP1}

OCP1 threshold

3.9

4

5

4.1

V

V_{ISNS_OCP1_S}

OCP1 threshold during soft start

4.85

5.15

S

V_{ISNS_OCP2}

V_{ISNS_OCP3}

OCP2 threshold

OCP3 threshold

0.57

0.40

0.6

0.63

0.46

V

0.43

The time the average input current

needs to stay above OCP2 threshold

before OCP2 is triggered ⁽¹⁾

t_{ISNS_OCP2}

2

ms

The time the average input current

needs to stay above OCP3 threshold

before OCP3 is triggered ⁽¹⁾

t_{ISNS_OCP3}

50

ms

Resonant current polarity detection

hysteresis

V_{IpolarityHyst}

n_OCP1

16

30

4

44

mV

Number of OCP1 cycles before OCP1

fault is tripped ⁽¹⁾

RESONANT CAPACITOR VOLTAGE SENSE

V_CM

Internal common mode voltage

2.90

1.84

3

2

3.14

2.16

V

Frequency compensation ramp current

source value

I_RAMP

mA

Pull up and pull down ramp current

source mismatch ⁽³⁾

I_Mismatch

-1.25

1.25

%

GATE DRIVER

V_LOL

LO output low voltage

I_sink= 20 mA

0.02

0.10

0.02

0.10

0.05

0.18

0.05

0.18

0.12

0.3

V

V_RVCC- V_LOHLO output high voltage

I_source= 20 mA

I_sink= 20 mA

V_HOL- V_HS

V_HB- V_HOH

HO output low voltage

HO output high voltage

0.12

0.3

I_source= 20 mA

V_HB-

High side gate driver UVLO falling

threshold

6.6

7.25

0.9

7.75

1.05

V

HSUVLOFall

V_HB-

High side gate driver UVLO threshold

hysteresis

0.78

HSUVLOHys

I_{source_pk_HO}HO peak source current ⁽²⁾

-0.6

1.2

A

I_{source_pk_LO}

I_{sink_pk_HO}

LO peak source current ⁽²⁾

HO peak sink current ⁽²⁾

LO peak sink current ⁽²⁾

I_{sink_pk_LO}

1.2

BOOTSTRAP

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All voltages are with respect to GND, -40°C < T_J= T_A< 125°C, VCC = 15 V, currents are positive into and negative out of the

specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{BOOT_QUIESC}

(HB - HS) quiescent current

HB - HS = 12 V

42

62

80

µA

ENT

I_{BOOT_LEAK}

t_ChargeBoot

HB to GND leakage current

Length of charge boot state

V_HB= 600 V

0.40

265

5.40

300

µA

µs

230

26

SOFT START AND BURST MODE

Current output from SS pin to charge

up the soft start capacitor

I_SSUp

36

45

µA

R_SSDown

t_{SSInitVolPrgm}

R_LL

SS pin pull down resistance

ZCS or OCP1

300

720

92

370

776

98

450

830

106

Ω

SS initial voltage programming time ⁽¹⁾

µs

LL/SS voltage scaling resistor value

kΩ

For UCC256402, UCC256402A,

UCC256403A, UCC256404A

16

40

Minimum number of pulses in each

burst packet (including burst soft on/off

pulses)

N_burst

For UCC256403, UCC256404,

UCC256404B

Maximum number of pulses for burst

soft on/off

Nsoftmax

Ksoft

7

Minimal ratio of Vcomp/VFBreplica

during burst soft on/off

0.33

3.5

LL pin voltage during the burst mode

exit threshold (BMT_H) programming

V_LLVolPrgm

V

BMT_Hmin

BMT_Lmin

Minimal burst mode exit threshold

Minimal burst mode entry threshold

0.2

V

BIAS WINDING

Output voltage OVP - Positive

Threshold

V_BWOVPos

V_BWOVNeg

n_BWOV

3.86

4

-4

5

4.12

V

Output voltage OVP - Negative

Threshold

-4.12

-3.86

Number of BW OVP cycles before BW

OVP fault is tripped ⁽¹⁾

BW pin sourcing current for

BMT_L/BMT_Hprogramming

I_BWPrgm

t_BWPrgm

51

54

57

µA

ms

BMT_L/BMT_Hprogramming time

2

0.95

1

K_BMTL/BMTH1Ratio of BMT_L/BMT_HOption 1

K_BMTL/BMTH2Ratio of BMT_L/BMT_HOption 2

K_BMTL/BMTH3Ratio of BMT_L/BMT_HOption 3

K_BMTL/BMTH4Ratio of BMT_L/BMT_HOption 4

K_BMTL/BMTH5Ratio of BMT_L/BMT_HOption 5

K_BMTL/BMTH6Ratio of BMT_L/BMT_HOption 6

0.9

0.8

0.6

Ratio of BMT_L/BMT_HOption 7 (Burst

mode disable)

K_BMTL/BMTH7

0.4

BW pin equivalent resistance to

R_BWPrgm1

24730

17125

12562

9018

Ω

choose BMT_L/BMT_Hratio option 1 ⁽²⁾

BW pin equivalent resistance to

R_BWPrgm2

19976

13624

9813

choose BMT_L/BMT_Hratio option 2 ⁽²⁾

BW pin equivalent resistance to

R_BWPrgm3

choose BMT_L/BMT_Hratio option 3 ⁽²⁾

BW pin equivalent resistance to

R_BWPrgm4

choose BMT_L/BMT_Hratio option 4 ⁽²⁾

BW pin equivalent resistance to

R_BWPrgm5

6478

6849

choose BMT_L/BMT_Hratio option 5 ⁽²⁾

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All voltages are with respect to GND, -40°C < T_J= T_A< 125°C, VCC = 15 V, currents are positive into and negative out of the

specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BW pin equivalent resistance to

R_BWPrgm6

4450

4732

Ω

choose BMT_L/BMT_Hratio option 6⁽²⁾

BW pin equivalent resistance to

choose BMT_L/BMT_Hratio option 7

(Burst mode disable) ⁽²⁾

R_BWPrgm7

2422

-0.1

3038

-50

Ω

ADAPTIVE DEADTIME

dV_HS/dt

Detectable slew rate ⁽¹⁾

V/ns

s

FAULT RECOVERY

t_PauseTimeOutPaused timer ⁽¹⁾

THERMAL SHUTDOWN

1

T_{J_r}

Thermal shutdown temperature ⁽¹⁾

Thermal shutdown hsyterisis ⁽¹⁾

Temperature rising

125

145

10

°C

T_{J_H}

(1) Not tested in production. Ensured by characterization

(2) Not tested in production. Ensured by design

(3) I_Mismatchcalculated as [I_PU-(I_PD+I_PU)/2]/[(I_PD+I_PU)/2]

6.6 Switching Characteristics

All voltages are with respect to GND, -40°C < T_J= T_A< 125°C, VCC = 15 V, currents are positive into and negative out of the

specified terminal, unless otherwise noted.

PARAMETER

Rise time

TEST CONDITIONS

10% to 90%, 1 nF load

MIN

TYP

30

MAX

50

UNIT

ns

t_r(LO)

t_f(LO)

Fall time

10% to 90%, 1 nF load

20

50

ns

t_r(HO)

t_f(HO)

t_DT(min)

Rise time

30

50

ns

Fall time

20

50

ns

Minimum dead time ⁽¹⁾

100

ns

Maximum dead time (dead time fault)

t_DT(max)

ZCS event is not detected

ZCS event is detected

1.1

µs

(1)

Maximum dead time (dead time fault)

t_{DT(max_ZCS)}

150

(1)

t_ON(min)

t_ON(max)

Minimum gate on time ⁽¹⁾

Maximum gate on time ⁽¹⁾

250

16

ns

µs

(1) Not tested in production. Ensured by design

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6.7 Typical Characteristics

图6-1. I_HVHighvs Temperature

图6-2. I_HVLowvs Temperature

图6-3. I_HVLeakvs Temperature

图6-4. I_{BOOT_QUIESCENT}vs Temperature

图6-6. I_RAMPvs Temperature

图6-5. I_{BOOT_LEAK}vs Temperature

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图6-8. R_LLvs Temperature

图6-7. I_MISMATCHvs Temperature

图6-9. V_RVCC(no load) vs Temperature

图6-10. V_RVCC(100mA load) vs Temperature

图6-12. I_CCRunvs Temperature

图6-11. i_CCSleepvs Temperature

图6-13. V_CMvs Temperature

图6-14. R_FBvs Temperature

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图6-16. I_{XCAPDischarge}vs Temperature

图6-15. I_SSUpvs Temperature

图6-17. I_HVZCDvs Temperature

图6-18. V_{HB-HSUVLOFall}vs Temperature

图6-20. V_LOLvs Temperature

图6-19. I_HB-HSUVLOHysvs Temperature

图6-22. V_HOL- V_HSvs Temperature

图6-21. V_RVCC-VLOHvs Temperature

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图6-24. V_CCStartselfvs Temperature

图6-23. V_HB- V_HOHvs Temperature

图6-25. V_{CCReStartJfet}vs Temperature

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7 Detailed Description

7.1 Overview

The UCC25640x is a fully featured LLC resonant controller for AC/DC power supplies. The high level of

integration of UCC25640x enables significant reduction of component count and solution size without

compromising functionality. UCC25640x achieves very low standby power and low audible noise standby

operation using an optimized burst mode. The device's novel control scheme offers excellent transient

performance.

Many consumer applications, including large screen televisions, AC-DC adapters, industrial power supplies, and

LED drivers, employ PFC + LLC power supplies because they offer improved efficiency and small size,

compared with a PFC + flyback topology. A disadvantage of the PFC + LLC power supply system is that it has

poor light load efficiency and high no-load power consumption because the LLC stage requires a minimum

amount of circulating current to maintain regulation. To meet light load efficiency and standby power

consumption requirements, traditionally an auxiliary flyback converter is used. The auxiliary flyback converter

runs continuously to allow the main PFC + LLC power system to be shut down when the system enters low

power or standby mode. UCC25640x contains a number of novel features that enable it to offer excellent light

load efficiency and low no-load power. This will allow power supply designers to create systems that meet the

stringent no-load power target without needing an auxiliary flyback converter.

UCC25640x uses a novel control algorithm, Hybrid Hysteretic Control (HHC), to achieve regulation. In this

control algorithm, the switching frequency is defined by the resonant capacitor voltage, which carries accurate

input current information. This allows the controller to monitor and correct the input current directly. Compared

with traditional Direct Frequency Control (DFC), HHC makes the system close to a first order system if the

frequency control portion is small. This enables excellent load and line transient response.

UCC25640x adopts an advanced burst mode to meet the stringent requirements on standby power consumption

and audible noise level. At low output power levels UCC25640x automatically transitions into light-load burst

mode. In burst mode, UCC25640x repetitively delivers a burst packet with a fixed number of switching pulses

and a shut-off period. The shut-off time period between burst packets is terminated by the secondary regulator

loop based on the FB pin current. The LLC equivalent load current level during the burst on period is a

programmable value. For each burst packet, the switching frequency slowly ramps down at the first few

switching periods and ramps up at the last few switching periods, to slowly ramp up and ramp down the resonant

current during burst operation. This burst soft-on and soft-off can effectively help to minimize the audible noise

during burst mode operation. In addition, UCC25640x operates in a low power mode during burst mode with a

very low quiescent current and biased optocoupler operation with low current.

UCC25640x monitors the half-bridge switch node to determine the required dead-time for the gate signals. In

this way the dead-time is automatically adjusted to provide optimum efficiency and robust operation. UCC25640x

includes a slew rate detector with improved sensitivity of the switch node voltage for adaptive dead-time that

makes its operation inherently robust compared with alternative parts.

UCC25640x includes high and low-side drivers that can directly drive N-channel MOSFETs in an LLC power

stage. This allows complete and fully featured power systems to be realized with minimum component count.

UCC256402 and UCC256404 includes a high-voltage startup JFET to initially charge the VCC capacitor to

provide the energy needed to start the PFC and LLC power system. Once running, power for the PFC and LLC

controllers is derived from a bias winding on the LLC transformer. UCC256404 also includes the active X-

capacitor discharge feature to discharge the remaining voltage on the X-capacitor of the EMC filters after

unplugging the AC input. UCC256403 does not include the high voltage startup and active X-capacitor discharge

features. It requires an auxiliary supply to power the VCC.

UCC25640x includes robust algorithms for avoiding the zero-current switching (ZCS) operation region. When

ZCS operation is detected, UCC25640x overrides the feedback signal and ramps up the switching frequency

until non-capacitive operation is restored, after which the switching frequency is ramped back down at a rate

determined by the soft-start capacitor until control has been handed back to the voltage control loop.

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Additional protection features of UCC25640x include three-level over current protection (OCP), output over

voltage protection (OVP), input voltage under-voltage protection (UVP), gate driver under-voltage lock-out

(UVLO) protection, and over temperature protection (OTP).

The key features of UCC25640x can be summarized as follows:

• Hybrid Hysteretic Control helps achieve best-in-class load and line transient response

• Optimized light load burst mode enables less than 150-mW standby power designs

• Burst soft-on and soft-off enables ultra-quiet standby operation

• Robust adaptive dead time control

• Integrated high-voltage gate driver

• Integrated high-voltage startup for UCC256402 and UCC256404

• Active X-capacitor discharge for UCC256404

• Improved capacitive region operation prevention scheme

• Comprehensive protection feature set

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7.2 Functional Block Diagram

BLK

BW

+

-

+

-

BLKStart

BLKStop

OVPTh+

OVPTh-

HV Start Up

FET

Line

BLKStartTh

BLKStopTh

R_HV

OVP

HV

+

-

+

-

Neutral

To RVCC

HVFetOnOff

XcapDischarge

ACZeroCrossing

BMT_L:BMT_H

HV Startup ctrl & AC

disconnect detect

Bias

winding

or

external

supply

Vbus

Active/Low

Power

Wake Up

Control

WaveGenEn

VCCShort

VCC

monitor

HB

HO

HS

VCC

VCCReStartJfet

VCCStartSwitching

Temperature

sensor

OTP

SlewDone_H2L

RVCCEn

Adaptive

Dead Time

LDO

RVCCUVLO

VCM

Level

Shift

+

-

RVCC

+

HSON

IPolarity

RVCC

VCM

-

High Voltage Isolation

OCP1

+

-

+

-

LSON

LO

OCP2

OCP1Th

OCP2Th

To resonant

capacitor

CISNS

RISNS

ISNS

VCC

Average

MUX

+

-

OCP3

IFB

AVDD

OCP3Th

HSON

FB

IPolarity

SlewDone_H2L

ZCS

ChargeSS

SSEnd

FBLessThanSS

FBLessThanBMT

HSON

LSON

SSEn

ZCS

SS Ctrl

Feedback

Opto-

coupler

FBReplica

Waveform generator

Pick

lower

value

+

HSRampOn

LSRampOn

Pick

higher

value

+

-

RFB

-

Vcm

+

-

MUX

85µA

max

+

SSEnd

VCR

+

MUX

SSEnd

WaveGenEn

-

VCM

AVDD

To RVCC

AVDD

OVP

OTP

RVCCEn

ChargeSS

HSRampOn

LSRampOn

OCP1

OCP2

VCCClampEn

SS

OCP3

BLKStart

LL/SS

SSEn

System states and

faults

Rdischarge

ZCS

BLKStop

RVCCUVLO

XcapDischarge

HVFetOn

VCCReStartJfet

VCCStartSwitching

ACZeroCrossing

FBLessThanBMT

V_SS_

INITIAL

Gen

VCR

GND

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7.3 Feature Description

7.3.1 Hybrid Hysteretic Control

UCC25640x uses a novel control scheme, Hybrid Hysteretic Control (HHC), to achieve best-in-class line and

load transient performance. The control method makes the compensator easier to design. The control method

also makes light load management easier and more efficient. Improved line transient enables lower bulk

capacitor and output capacitor values, reducing system cost.

HHC is a control method which combines traditional frequency control and charge control. It is a charge control

with an added frequency compensation ramp. Compared with traditional frequency control, it changes the power

stage transfer function from a second order system to a first order system, so that it makes the compensation

network design easier. The control effort is directly related to input current, so superior line and load transients

can be achieved. Compared with charge control, Hybrid Hysteretic Control avoids instability by adding in a

frequency compensation ramp. The frequency compensation ensures system stability, and makes the output

impedance lower as well. Lower output impedance makes the transient performance better than charge control.

The frequency compensation also makes the implementation of burst mode soft-on and soft-off much easier, as

changing the control effort can directly impact the switching frequency. For burst mode soft-on and soft-off, the

converter switching frequency self-adjusts to achieve a reduced resonant current.

In summary, HHC solves the following problems:

• Help LLC converters achieve superior load transient and line transient

• Changes the small-signal transfer function to a first order system to easily achieve very high bandwidth

• Inherently stable via frequency compensation

• Makes burst mode control easier to optimize light load efficiency

• Makes the implementation of burst mode soft-on and soft-off much easier, to achieve lower audible noise

图 7-1 shows the HHC implementation in UCC25640x: a capacitor divider (C1 and C2) and two well matched

controlled current sources. The resonant capacitor voltage is divided down by the capacitor divider formed by C1

and C2. The current sources are controlled by the gate drive signals. When the high-side switch is on, the upper

current source injects a constant current into the capacitor divider; when the low-side switch is on, the lower

current source pulls the same amount of constant current out of the capacitor divider. The two current sources

add a triangular compensation ramp to the VCR node. The current sources are supplied by a reference voltage

AVDD. AVDD needs to be equal to or larger than twice the common mode voltage V_CM. The divided resonant

capacitor voltage and the compensation ramp voltage are then added together to get the VCR node voltage. If

the frequency compensation ramp dominates, the VCR node voltage will look like a triangular waveform, and the

control will be similar to direct frequency control. If the resonant capacitor voltage dominates, the shape of the

VCR node voltage will look like the actual resonant capacitor voltage, and the control will be similar to charge

control. This is why the control method is called “hybrid” and the compensation ramp is called frequency

compensation.

This set up has an inherent negative feedback to keep the high-side and low-side on-time balanced, and also to

keep the common mode voltage at the VCR node at V_CM

.

There are two input signals needed for the new control scheme: VCR and V_COMP. VCR is the sum of the scaled

down version of the resonant capacitor voltage and the frequency compensation ramp. V_COMPis the voltage loop

compensator output. The waveform below shows how the high-side and low-side switches are controlled based

on VCR and V_COMP. The common mode voltage of VCR is V_CM

.

Based on V_COMPand V_CM(3 V), two thresholds: V_THand V_TLare created.

V_comp

V_TH= V_CM

+

2

(1)

(2)

V_comp

V_TL= V_CM

-

2

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The VCR voltage is compared with the two thresholds. When VCR > V_TH, the high-side switch is turned off;

when VCR < V_TL, low-side switch is turned off. HO and LO turn on edges are controlled by the adaptive dead

time circuit.

I_IN

+

Gate_H

Lr

V_OUT

V_IN

Gate_L

Cr

-

Dead

time

control

Compensator

AVDD

Gate_L

Gate_H

Q S

Icomp

+

-

Gate_H

Gate_L

V_TL

R

Q

V_COMP

C1

+

-

V_CM

Q S

+

VCR

C2

+

-

Icomp

R

Q

V_TH

VCR

V_COMP= V_TH- V_TL

Turn high side off when VCR > V_TH

;

Turn low side off when VCR < V_TL

;

(V_TH+ V_TL)/2 = V_CM

+

High side and low side are turned on

by dead time control circuits

VCR =

图7-1. UCC25640x HHC Implementation

High-Side Gate

Low-Side Gate

T/2

ûVCR‘

VTH

VTL

ûVCR

t₃

t₁

t₄

t₂

图7-2. HHC Gate On/Off Control Principle

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7.3.2 Regulated 13-V Supply

RVCC pin is the regulated 13-V supply. This regulated rail is used to supply the PFC and LLC as a bias. RVCC

has under voltage lock out (UVLO) function. During normal operation, if the RVCC voltage is less than

RVCC_UVLOthreshold, the system will enter FAULT state. Details about the FAULT handling will be discussed in

the 节7.3.9 section.

7.3.3 Feedback Chain

Control of the output voltage is provided by a voltage regulator circuit located on the secondary side of the

isolation barrier. The demand signal from the secondary regulator circuit is transferred across the isolation

barrier using an optocoupler and is fed into the FB pin on UCC25640x. This section discusses the whole

feedback chain. 图 7-3 shows the block diagram of the FB chain, and 图 7-4 shows the typical timing diagram

with a normal soft start followed by a ZCS event, and load step into burst mode, and then exiting burst mode.

The feedback chain has the following functions:

• Optocoupler feedback signal input and bias

• FB voltage clamp

• Soft start function selection by a "pick lower value" block

• Burst mode selection by a "pick higher value" block

• Convert single ended feedback demand into two thresholds V_THand V_TL; and VCR comparison with the

thresholds and the common mode voltage V_CM

VCC

IFB

AVDD

FB

ChargeSS

SSEnd

FBLessThanSS

FBLessThanBMT

SS

Ctrl

SSEn

ZCS

Feedback

Opto-

coupler

FBreplica

Pick

lower

value

+

Pick

higher

value

V_TL

VcrLowerThanVthl

+

-

RFB

-

V_CM

+

SSreplica

VcrHigherThanVthh

VcrHigherThanVcm

BMTreplica

V_TH

-

MUX

85µA

max

SSEnd

VCR

V_CM

+

-

+

AVDD

SS

BMT

图7-3. Feedback Chain Block Diagram

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FBreplica

SS

BMT

VTH

VCM

VTL

SSEn

ZCS

FBLessThanSS

SSEnd

ChargeSS

FBLessThanBMT

图7-4. Feedback Chain Timing Diagram

7.3.3.1 Optocoupler Feedback Signal Input and Bias

The secondary regulator circuit and optocoupler feedback circuit all add directly to the standby power consumed

by the system. To achieve very low standby power it is necessary to drive the optocoupler in a low current mode.

As shown in 图 7-3, a constant current source IFB is generated from VCC voltage and connected to FB pin. A

resistor RFB is also connected to this current source with a PMOS in series. During normal operation, the PMOS

is always on, so that the FB pin voltage will be equal to the zener diode reference voltage plus the voltage drop

on the PMOS source to gate.

I_FB= I_opto+I_RFB

(3)

From this equation, when I_optoincreases, I_RFBwill decrease, making FBreplica decrease. In this way, the control

effort is inverted. A conventional way to bias the optocoupler is using a pull up resistor on the collector of the

optocoupler output. To reduce the power consumption, the pull up resistor needs to be big, which will limit the

loop bandwidth. For the bias current method used in UCC25640x, the FB pin voltage is maintained constant so

that the parasitic capacitor of the optocoupler will not introduce an extra pole to the system, and subsequently

limit the loop bandwidth.

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7.3.3.2 FB Pin Voltage Clamp

As shown in the 节 7.3.3.1 section, the FBreplica decreases while I_optoincreases. When I_optoreaches the value

of I_FB, the FB pin voltage starts to drop because there is no current flow through the PMOS. FB pin pulled low

will impact the system transient response, due to the extra delay introduced by charging the parasitic capacitor

of the optocoupler to pull up the FB pin voltage. A FB pin voltage clamp circuit is used to prevent this scenario.

When FB pin voltage drops below the FB pin clamp voltage threshold, an extra current source is turned on to

clamp the FB voltage. The clamp strength is I_FBclamp. The FB pin clamp circuit improves the system transient

performance from light load to heavy load.

7.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer

This part of the circuit consists of 3 elements:

• A pick lower block

• A MUX which selects AVDD or SS signal as the second input to the pick lower block

• An SS control block which handles the charge and discharge of the SS capacitor in the case of a ZCS fault

The pick lower block has two inputs. The first input is FBreplica. The second input is selected between AVDD

and LL/SS pin voltage. The output of the block is the lower of the two inputs.

The MUX selects between SS and AVDD. The selection is based on SSEnd (soft start end) signal, which is an

output of the SS Ctrl block. SSEnd is high when SS is higher than FBreplica, and the soft start process has been

initiated by the state machine, and there is no ZCS condition. Switching to AVDD after soft start has ended helps

make sure that during non-soft start or non-ZCS fault condition, FBreplica signal is always sent through the pick

lower block. It also releases the LL/SS pin to perform the light load threshold programming.

The SS control block handles the charge and discharge of the SS capacitor in the case of a ZCS fault. It resets

the SSEnd signal when ZCS happens, so the effect of pulling down on LL/SS pin to increase the switching

frequency can pass through the pick lower block.

7.3.3.4 Pick Higher Block and Burst Mode Multiplexer

The output of the pick lower block goes into a pick higher block, which selects the higher of the pick lower block

output and the burst mode threshold setting.

The burst mode multiplexer selects between burst mode threshold (BMT) and ground. During soft start, the

multiplexer selects ground. The startup process is open loop and controlled by the soft start ramp. Burst mode is

not enabled during soft start phase.

After soft start, the higher of the two inputs are sent to the differential amplifier. The output of the block is

FBLessThanBMT. This output is sent to the waveform generator state machine to control burst mode and system

external shut down.

7.3.3.5 VCR Comparators

The output of the pick higher block is sent to a differential amplifier to convert the signal into two thresholds

symmetrical to V_CM. The difference between the two thresholds V_THand V_TLequals the input amplitude. The

VCR pin voltage is then compared with V_TH, V_TL, and V_CM. The results are sent to the waveform generator.

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7.3.4 Resonant Capacitor Voltage Sensing

The resonant capacitor voltage sense pin senses the resonant capacitor voltage through a capacitor divider.

Inside the device, two well matched, controlled current sources are connected to the VCR pin to generate the

frequency compensation ramp. The on/off control signals of the two current sources come from the waveform

generator block.

During waveform generator IDLE state or before startup, the VCR node is clamped to V_CM. This action will help

reduce the startup peak current, and help the VCR voltage to settle down quickly during burst mode.

AVDD

HSRampOn

VCR

7

VCR

LSRampOn

图7-5. VCR Block Diagram

The ramp current on/off sequence is shown in 图 7-6. The ramp current is on all the time. It changes direction at

the falling edge of the high-side on or low-side on signal.

HSON

LSON

2 mA

Compensation ramp

current

0

-2 mA

图7-6. VCR Compensation Ramp Current On/Off

On the VCR pin, a capacitor divider is used to combine the resonant capacitor waveform and the compensation

ramp waveform. Adjusting the size of the external capacitors can change the contribution of charge control and

direct frequency control. Assuming the divided down version of the resonant capacitor voltage by the capacitor

divider is V_div, the compensation ramp current resultant voltage on the VCR pin is V_ramp. If V_divis much larger

than V_ramp, the control method is similar to charge control, in which the control effort is proportional to the input

charge of one switching cycle. If V_rampis much larger than V_div, the control method is similar to direct frequency

control, in which the control effort is proportional to the switching frequency. The most optimal transient response

can be achieved by adjusting the ratio between V_divand V_ramp

.

7.3.5 Resonant Current Sensing

The ISNS pin is connected to the resonant capacitor using a high voltage capacitor. The capacitor CISNS and

the resistor RISNS form a differentiator. The resonant capacitor voltage is differentiated to get the resonant

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current. The differentiated signal is AC and goes both positive and negative. In order to sense the zero crossing,

the signal is level shifted using an op amp adder. The IPolarity comparator detects the direction of the resonant

current. IPolarity is checked at LSON and HSON falling edges for ZCS protection, with more details described in

节 7.3.9.1 section. The digital state machine implements a blanking time on IPolarity. The IPolarity edges during

the first 400 ns of dead time are ignored considering the noise on ISNS pin introduced by the switching node

transition.

OCP2 and OCP3 thresholds are based on average input current. To get the average input current, the

differentiator output is multiplexed with the high-side switch on signal HSON. When HSON is on, the MUX output

is the differentiator output; when HSON is off, the MUX output is 0. The MUX output is then averaged using a

low pass filter. The output of the filter is the sensed average input current. Note that the MUX needs to pass

through both positive and negative voltages. OCP2 and OCP3 faults have a 2 ms and 50 ms timer respectively.

Only when the OCP2/OCP3 comparators output high for continuous 2 ms or 50 ms, will the faults be activated.

OCP1 threshold is set on the peak resonant current. The voltage on the ISNS pin gets compared to OCP1

threshold OCP1Th directly. The peak resonant current is checked once per cycle on the positive half cycle.

OCP1 fault is only activated when there are 4 consecutive cycles of OCP1 event detected. During start up, the

OCP1 comparator output of the first 15 cycles are ignored.

VCM

+

-

IPolarity

VCM

-

OCP1

+

-

+

-

To

Resonant

Capacitor

OCP2

OCP1Th

OCP2Th

ISNS

CISNS

RISNS

6

Average

MUX

+

OCP3

-

OCP3Th

HSON

图7-7. ISNS Block Diagram

7.3.6 Bulk Voltage Sensing

The BLK pin is used to sense the LLC DC input voltage (bulk voltage) level. The comparators on BLK pin have

the following two thresholds:

• Bulk voltage level when LLC starts switching –V_BLKStart

• Bulk voltage level when LLC stops switching –V_BLKStop

A resistor divider is connected to the pin to achieve the desired system input range. A fault is triggered if BLK pin

voltage drops lower than V_BLKStopduring operation. The detailed action of Input Under Voltage Protection is

described in 节7.3.9.4 section.

图7-8 shows the block diagram of the BLK pin.

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BLK

4

+

-

BLKStart

BLKStop

V_BLKStart

+

-

V_BLKStop

图7-8. BLK Pin Block Diagram

BLK voltage is also used to monitor the input over voltage fault for some device versions as listed in 节 Device

Comparison Table. There are two thresholds:

• Bulk voltage level when BLK over voltage protection (OVP) rising threshold - V_BLKOVPRise

• Bulk voltage level when BLK over voltage protection (OVP) falling threshold - V_BLKOVPFall

When BLK voltage is higher than V_BLKOVPRise, OVP is triggered; OVP gets cleared when BLK voltage falls below

V_BLKOVPFall

.

7.3.7 Output Voltage Sensing

The output voltage is sensed through the bias winding (BW) voltage sense pin. With one terminal of the bias

winding connected to primary side ground, the bias winding voltage at the other terminal represents the output

voltage when the secondary side rectifier diode conducts. A resistor divider is typically used to connect from the

bias winding terminal to the BW pin. The BW voltage is compared with a positive and a negtive threshold to

generate an output OVP fault. During startup, BW pin is multiplexed for burst mode threshold programming. The

details are introduced in the 节 7.4.3.1 section. The block diagram of the bias winding voltage sense block is

shown below.

BW

8

+

OVPTh+

OVPTh-

-

OVP

+

-

BMT_L:BMT_H

图7-9. Bias Winding Sensing Block Diagram

If the OVP event is high for 5 consecutive switching cycles, the system will enter FAULT state. The actions

during an OVP fault are described in the 节7.3.9.3 section.

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7.3.8 High Voltage Gate Driver

LO is the low-side gate driver output. The gate driver is supplied by the 13-V RVCC rail.

The high-side driver module consists of three physical device pins. HB and HS form the positive and negative

bias rail, respectively, of the high-side driver, and HO connects to the gate of the upper half-bridge MOSFET.

During periods when the lower half-bridge MOSFET is conducting, HS is shorted to GND via the conducting

lower MOSFET. At this time power for the high-side driver is obtained from RVCC via the high voltage diode

DBOOT, and capacitor CBOOT is charged to RVCC minus the forward drop on the diode.

During periods when the upper half-bridge MOSFET is conducting, HS is connected to the LLC input voltage rail.

At this time the HV diode is reverse biased and the high-side driver is powered by the charge stored in CBOOT.

Both the high-side and low-side gate drivers have under voltage lock out (UVLO) protection. The low-side gate

driver UVLO is implemented on RVCC; the high-side gate driver UVLO is implemented on (HB - HS) voltage.

When operating at light load, UCC25640x enters burst mode. During the burst off period, the gate driver enters

low power mode to reduce power consumption.

The block diagram of the gate driver is shown in 图7-10.

To RVCC

Vbus

Active/Low

Power

WaveGenEn

Wake Up

Control

HB

HO

HS

14

15

16

SlewDone_H2L

Adaptive

Dead Time

Level

Shift

HSON

High Voltage Isolation

LO

LSON

10

图7-10. Gate Driver Block Diagram

7.3.8.1 Adaptive Dead Time Control

The Dead Time describes the time interval between an outgoing LLC MOSFET turning off and the incoming LLC

MOSFET turning on. Dead time control is critical for LLC operation. A certain amount of dead time is required to

prevent shoot through. During the dead time, the HS node slews from one input rail to the other due to the

inductive resonant current. In order to achieve zero voltage switching (ZVS) turn on, the dead time needs to be

long enough for the resonant current to fully charge or discharge the HS node. But after the body diode starts

conducting, the MOSFET should be turned on quickly. Too long of a turn on delay can result in reverse resonant

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current and lead to the loss of ZVS. Also, the voltage drop on the body diode is higher than that on the MOSFET

channel. Optimized dead time can help to minimize the power loss.

The resonant current flowing through the HS node during the dead time depends on the LLC resonant tank

design and varies by operating frequency and output/input voltage ratio. Therefore, the optimized dead time

varies widely with LLC operating conditions. UCC25640x includes an adaptive dead time control to automatically

find the optimized dead time across the entire operating range. It detects the change of slew rate of the HS node

voltage. During a switching transition, the slew rate rises up first and then drops back to zero. A slew rate

detector is used to detect the moment when the slew rate drops below a pre-defined threshold. A slew done

event is only detected when the slew rate during dead time crosses the threshold and then drops back below the

threshold. If the slew rate is lower than the threshold (i.e. minimal detectable slew rate) during the whole dead

time period, no slew done will be detected. This is to prevent the mis-detection due to noise on the HS node

voltage. If slew done is not detected, maximum dead time is used.

Because of the natural symmetric operation of LLC, only the dead time between high-side MOSFET turn off and

low-side MOSFET turn on is determined by the slew rate detector. This dead time is copied and then applied to

the dead time between low-side MOSFET turn off and high-side MOSFET turn on.

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7.3.9 Protections

7.3.9.1 ZCS Region Prevention

The capacitive region is an LLC operating region in which the voltage gain increases when the switching

frequency increases. It is also called the ZCS region. Capacitive mode operation should be avoided for two

reasons:

• The feedback loop becomes positive feedback in the capacitive region

• The MOSFET may be damaged because of body diode reverse recovery

The capacitive region detection is done by checking the resonant current polarity at HSON or LSON falling edge.

If the resonant current is positive at LSON falling edge, or negative at HSON falling edge, the ZCS signal in the

waveform generator is turned high. The ZCS signal stays high until ZCS is cleared at the next HSON or LSON

falling edge.

If ZCS is detected, the next gate will be turned on at the next IPolarity flip event when the resonant current

becomes inductive again. The IPolarity flip indicates that the capacitive operation cycle has already passed. The

resonant current reverses direction and begins to discharge the switch node. In this stage, the body diode is no

longer conducting and it is allowed to turn on the next gate. If there is a slew done event detected, it suggests

that the opposite body diode must not be conducting and the next gate will be turned on as well. If neither the

IPolarity flip event or slew done event is detected, the next gate will be turned on by the maximum dead time

timer expiration. During a ZCS event, the maximum dead time is changed to 150 µs.

ZCS typically happens when the LLC operates at heavy load condition and the switching frequency is too low.

Therefore, when ZCS is detected, the LL/SS pin is pulled low through a diode to ground and the system enters a

"ZCS soft start" process. The switching frequency is forced to ramp up in order for the system to recover from

ZCS. The details of the "ZCS soft start" are described in the 节 7.4.3.1 section. As the ZCS detection relies on

the resonant current polarity detection, if LLC operates at very light load condition, the magnitude of the resonant

current can be very small and there may be chances that the resonant current polarity detection can be distorted

by the switching noise. In order to prevent the nuisance ZCS detection at light load condition, ZCS is disabled at

light load condition by utilizing the burst mode control. The details are described in the 节7.4.3 section.

Below is the flow chart of the capacitive region prevention algorithm and the timing diagram of a ZCS event:

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Start

ZCS event detected at HSON or

LSON turn off edge?

Yes

No

ZCS = 1, Maximum

dead-time changed

to 150us

ZCS = 0

No

Pull done LLSS pin,

initiate ZCS soft

start process

System in Burst Mode?

Yes

Slew done detected or

Ipolarity flip detected after

Ipolarity blanking expires?

Yes

No

Yes

Turn on the next

gate

Maximum dead time expired?

图7-11. ZCS Prevention Algorithm Flow Chart

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Next Switch

Turn On is

Delayed

HS

LS

ZCS

Detected

Resonant

current

No Slope Until

Current

Becomes

Primary Side

Switch Node

Negative

t

V_COMPRamps Down

Until No ZCS

图7-12. Timing Diagram of a ZCS Event

7.3.9.2 Over Current Protection (OCP)

There are three levels of OCP:

1. OCP1: peak current protection (highest threshold)

a. Fault action: If ISNS is higher than OCP1 threshold for 4 consecutive switching cycles, the switching will

stop. The system enters FAULT state, and waits for 1 s and then re-enters the startup state.

2. OCP2: average input current protection (high threshold)

a. Fault action: If sensed ISNS average value is above the threshold for 2 ms, the switching will stop. The

system enters FAULT state, and waits for 1 s and then re-enters the startup state.

3. OCP3: average input current protection (low threshold)

a. Fault action: If sensed ISNS average value is above the threshold for 50 ms, the switching will stop. The

system enters FAULT state, and waits for 1 s and then re-enters the startup state.

The circuit block diagram has been discussed in the 节7.3.5 section.

7.3.9.3 Bias Winding Over Voltage Protection (BWOVP)

This is typically used for output over voltage protection when the transformer has a bias winding. The output over

voltage trip point can be set by configuring the voltage divider on the BW pin. When the BW OVP comparator is

high for 5 consecutive switching cycles, the switching will stop. The system enters fault state, and waits for 1 s

and then re-enters the startup state.

7.3.9.4 Input Under Voltage Protection (VINUVP)

This is the input under voltage protection. The trip point can be set by configuring the voltage divider on the BLK

pin. If the BLK voltage drops below BLKStop, switching will stop immediately. The system enters FAULT state,

and waits for 1 s and then re-enters the startup state.

7.3.9.5 Input Over Voltage Protection (VINOVP)

This is the input over voltage protection. This feature only exists in some device versions. If the BLK voltage

rises above V_BLKOVPRise, switching will stop immediately. The system enters FAULT state, and waits for 1s and

then re-enters the startup state if BLK voltage falls below V_BLKOVPRise

.

7.3.9.6 Boot UVLO

This is the high-side gate driver UVLO. When (HB – HS) voltage is less than the threshold, the high-side gate

output will be shut down. The system does not enter FAULT state.

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7.3.9.7 RVCC UVLO

This is the regulated 13-V UVLO. When RVCC voltage is less than the threshold, both the high-side gate output

and the low-side gate output will be turned off immediately. The system enters FAULT state, and waits for 1 s

and then re-enters the startup state.

7.3.9.8 Over Temperature Protection (OTP)

This is the device over temperature protection. When OTP threshold is exceeded, the switching will stop. The

system enters FAULT state, and waits for 1 s and then re-enters the startup state if the temperature is back

below the OTP threshold.

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7.4 Device Functional Modes

7.4.1 High Voltage Start-Up

UCC256402 and UCC256404 uses a self bias start up scheme, thus eliminating the need for a separate

auxiliary supply. When AC power is first plugged in, the PFC and LLC are both off. The internal JFET on the HV

pin will be enabled and will start to deliver current from a source connected from the HV pin to the VCC

capacitor. The charge current is small when VCC pin voltage is below V_CCShort, and then becomes larger when

VCC pin voltage is above V_CCShort.Once the VCC pin voltage exceeds its VCC_{StartSwitching}threshold, the current

source will be turned off and RVCC will be enabled to turn on the PFC. When the PFC output voltage reaches a

certain level, the LLC is turned on. When the LLC is operating and the output voltage is established, the bias

winding will supply current for both the PFC and the LLC controller devices.

UCC256403 does not include a high voltage start-up feature. It requires an external auxiliary supply to power on

the IC. The HV pin needs to be grounded when using the UCC256403.

7.4.2 X-Capacitor Discharge

X-capacitors used in EMC filters on the AC side of the diode bridge rectifier must have a method to allow them to

discharge down to a reasonable voltage within a specific amount of time. This is to ensure that voltage does not

remain present on the pins of the AC plug indefinitely after it is physically removed from the AC power.

Typically, discharge resistors are provided in parallel with the X-capacitors to provide this discharge path, but

these resistors then lead to fixed standing power loss as long as the power supply is connected to AC power,

and can be significant in the context of achieving very low standby power.

For every 100 nF of capacitance, a maximum bleed resistor of 10 MΩ must be added in parallel. For a typical

60-W to 100-W power supply with a typical capacitance of 330 nF, this requires 3 MΩ of discharge resistance.

At nominal high line 230 V, these resistors dissipate 17.63 mW of standing power loss. Thus it is necessary to

find alternative ways to discharge the X-capacitors using switched discharge paths in order to avoid the static

standing loss.

There are several standards for X-capacitor discharge. IEC60950 and IEC60065 requires that the discharge time

constant is less than 1s. IEC62368 requires that after 2 seconds of AC unplug, the remaining voltage on the x-

capacitor is less than 60 V (for 300 nF or more capacitance). UCC25640x uses an active discharge scheme to

support the fast discharge of up to 5-μF X-capacitance, for device variants that has X-capacitor discharge.

To meet the requirements of the standards, AC disconnect events must be detected. UCC25640x detects AC

disconnect by monitoring the AC zero crossings through the HV pin. When AC is present, there will be two AC

zero crossings in one line cycle. When AC is disconnected, there will be no zero crossings for an extended

period of time. 图 7-13 shows the rectified AC waveform. In the figure, the AC is disconnected at the peak of the

last half AC cycle. In reality, it can be disconnected anywhere within a switching cycle.

No zero crossings detected

Zero crossings detected every half switching cycle

图7-13. AC Disconnect Waveform

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To detect the zero crossings reliably as well as save power consumption, a staircase test current is generated

every 700 ms. When there are 4 zero crossings missing in a row at the highest test current setting, AC

disconnect is confirmed and the I_{XCapDischarge}current source is enabled. The waveform below shows the

staircase current waveform:

I4

I3

I2

I1

Staircase current

7 x 12 ms = 84 ms maximum

If AC is disconnected

12ms

700 ms

48 ms max if AC is

present

图7-14. Staircase Test Current for X-Capacitor Discharge

The test current is required for reliable AC zero crossing sensing. In short, this is because the leakage current in

the AC bridge rectifier diodes will affect the zero crossing detection at very light load. The added test current on

the HV pin will overcome the leakage current and make sure that AC zero crossing is detected on the HV pin. If

one zero crossing is detected during any test current stage, it means that AC is not disconnected. The test

current will shut off immediately and the system goes to the 700-ms no test current stage.

HV pin voltage

Zero crossing detection

threshold

AC zero crossing

detection active

I₄

I₃

I₂

I₁

Staircase test current

AC_zero_cross_detected

Zero cross detected with current I3

Close observation period

Zero cross detected with current I1

Close observation period

Zero cross detected

before highest test

current period expires

XCAP_discharge_active

No discharge

Discharge as 4 zero

crossings has missed

图7-15. Different Staircase Current Waveforms

图 7-15 shows different staircase current waveforms. The last waveform shows the AC disconnect is detected

and X-capacitor discharge current is enabled. The X-capacitor discharge current is enabled for 350 ms. AC zero

crossing function is available in all operation modes and available all the time. 图 7-16 shows the flow chart of

AC zero crossing detection and X-capacitor discharge. The zero crossing test starts 12 ms after HV startup is

completed. The discharge current I_{XCapDischarge}is created by turning on the JFET and enabling a current source

from JFET source to GND. During a fault restart process, HV startup is higher priority, so that the JFET is

connected to VCC. A zero crossing test current will be sent out 12 ms after HV startup is completed, regardless

of whether the detection idle timer has expired.

In some of the device variants, the X-capacitor discharge feature is disabled.

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Start

700 ms expired

Enable zero crossing

test current I1

Zero crossing

detected

No zero crossing

for 12 ms

No test current or

discharge current for

700 ms

Enable zero crossing

test current I2

Zero crossing detected

or 350 ms expired

No zero crossing

for 12 ms

Enable

IXCapDischarge

Enable zero crossing

test current I3

No zero crossing

for 12 ms

Enable zero crossing

test current I4

No zero crossing

for 48 ms

图7-16. AC ZCD and X-Capacitor Discharge Flow Chart

7.4.3 Burst Mode Control

The efficiency of an LLC converter power stage drops rapidly with falling output power. To maintain reasonable

light load efficiency it is necessary to operate the LLC converter in burst mode. In this mode the LLC converter

operates at relatively high power for a short burst period and then switching is stopped for a time period. During

the burst period excess charge is transferred to and stored in the output capacitor. During the burst off period

this stored charge is used to supply the load current. The burst mode operation is critical to meet strict standby

power consumption requirements. But a challenge with burst mode operation is the audible noise performance.

Due to the need to stop switching for certain time, there will be a pattern of switching pulses with frequencies

that fall within the audible frequency range from 20 Hz to 20 kHz. Some device variants of UCC25640x includes

a burst mode with soft on and soft off periods at the first few and last few switching pulses, minimizing the

audible noise during standby operation.

图 7-17 describes the timing diagram of the burst mode operation. Two burst mode thresholds are used (BMT_H

for burst mode exit and BMT_Lfor burst mode entry). The details of how to program these two thresholds are

described in 节 7.4.3.1 section. The FBreplica from the FB chain is compared with the two thresholds, and

determines the burst mode operation.

• At t₁, FBreplica is below BMT_L. The system enters burst mode and stops switching immediately. During the

burst off period, UCC25640x disables some internal blocks to save power consumption.

• At t₂, FBreplica is above BMT_H. The system starts to switch again, and this period is referred to as the burst

on period. During burst on period, the control effort V_compsent to the VCR comparator is the higher value of

FBreplica and BMT_L. For the first switching pattern after the system enters burst mode, there is no burst soft

on.

• At t₃, FBreplica falls below BMT_Lagain. Switching will not stop until it reaches the predefined number (N_burst

)

of a burst packet. The V_compstill selects the higher value of FBreplica and BMT_L. For the last 7 switching

cycles, soft off will be applied (only 3 soft on/off steps are shown in 图7-17 for conceptual introduction). The

V_compis a fraction of the higher value between FBreplica and BMT_L. The number of fractions for different

switching cycles are described in 表7-1. For burst soft off, it starts from step 7 and ramps down. After it

reaches step 1, soft off steps are completed and the system enters burst off period. This helps to achieve

slow ramping down of the LLC transformer current. For burst soft on, it reverses the direction by starting from

step 1 and ends at step 7. If FBreplica becomes greater than BMT_Lbefore the soft off steps are completed,

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the burst soft off will end immediately and the system transitions to burst soft on. In this condition, the soft on

step starts from the step where soft off ends at, to ensure a smooth transition between soft off and soft on.

• At t₄, FBreplica is greater than BMT_L. The system enters burst on period, and since this is not the first burst

on period, there is soft on period at the first 7 switching cycles. The fraction of Vcomp to the higher value of

FBreplica and BMT_Lis also described in 表7-1. After burst soft on steps are completed, Vcomp uses the

higher value of FBreplia and BMT_Luntil it reaches burst soft off periods.

• At t₅, FBreplica is greater than BMT_Lagain after another burst off period. This time the difference is that

FBreplica is greater than BMT_Hat t₆, when the burst soft on steps are not completed yet. The burst soft on

will get terminated immediately, so that V_compcan follow the FBreplica. This is to ensure a quick system

response during a load transient from burst mode operation to out-of-burst mode operation.

BMT_H

Vcomp

FBreplica

BMT_L

Switching

Pulses

LLC

Transformer

Current

t₁

t₂

t₃

t₅t₆

t₄

图7-17. Burst Mode Switching Pattern

表7-1. Burst Mode Soft On and Soft Off V_compControl

Burst Soft On and Soft Off Step

Fraction used for Reduced V_compDuring Soft On

1

2

3

4

5

6

7

1/3

9/21

11/21

13/21

15/21

17/21

19/21

The HHC control makes the implementation of the burst soft on and soft off very straight forward. Due to the

frequency control portion in HHC, changing the V_compcan directly impact the LLC switching frequency to control

the resonant current magnitude within switching cycles. Also the last pulse of each burst on period is turned off

when the VCR node voltage equals the common mode voltage VCM. In HHC control, this is approximately

equivalent to resonant capacitor voltage equal to V_IN/2. This operation keeps the resonant capacitor voltage to

approximate V_IN/2 for each burst off period, thus enabling the burst pattern to settle as soon as possible during

the burst on period.

As described in 节 7.3.9.1, in order to avoid nuisance ZCS detection at light load condition, ZCS is disabled at

light load condition. This is achieved by using the BMT_Hthreshold. When FBreplica is below BMT_H, indicating a

light load operating condition, ZCS detection is disabled. When FBreplica is above BMT_H, ZCS detection will

resume.

Some device variants disables the burst soft on and soft off feature, for applications that have less concern

about audible noise, but want smaller output ripple during burst mode. A smaller burst packet size is also used.

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The timing diagram of the burst mode operation for when burst soft on and soft off is disabled is described in 图

7-18.

• At t₁, FBreplica is below BMT_L. The system enters burst mode and stops switching immediately.

• At t₂, FBreplica is above BMT_H. The system starts to switch again, and enters burst on period. The control

effort V_compsent to the VCR comparator is the higher value of FBreplica and BMT_L.

• At t₃, FBreplica falls below BMT_Lagain. Switching will not stop until it reaches the predefined number (N_burst

of a burst packet. If switching reaches the N_burstbefore FBreplica falls below BMT_Lagain, system will

continue to deliver burst packet until FBreplica is below BMT_L.

)

• At t₄, FBreplica is greater than BMT_L. The system enters burst on period without soft on. So the control effort

V_compis the higher value of FBreplica and BMT_L.

• At t₅, FBreplica is greater than BMT_Lagain after another burst off period. The control effort V_compfollows

FBreplica. At t₆, FBreplica becomes above BMT_H, V_compstill follows FBreplica. If FBreplica remains above

BMT_Hmore than N_burstswitching cycles, system exits burst mode.

BMT_H

Vcomp

FBreplica

BMT_L

Switching

Pulses

LLC

Transformer

Current

t₁

t₂

t₃

t₅t₆

t₄

图7-18. Burst Mode Switching Pattern when Soft On and Soft Off is Disabled

UCC25640x can also disable the burst mode by changing the BW pin resistance, as described in 节 7.4.3.2.

When burst mode is disabled, the switching does not stop even when FBreplica becomes lower than BMT_L. The

pick higher block still works by picking the higher value of BMT_Land FBreplica for the control effort V_comp. In this

case, BMT_Lwill limit the maximum switching frequency of LLC.

When burst mode is disabled, FBreplica needs to be higher than BMT_Lat steady state. Otherwise, LLC output

voltage will lose regulation as it continues deliver more energy than what is demanded from the feedback. For a

transient period, it is ok for FBreplica to be lower than BMT_L.

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7.4.3.1 Soft-Start and Burst-Mode Threshold

The soft-start programming and burst mode threshold programming are multiplexed on the pin LL/SS. In

addition, when ZCS region operation happens, this pin is pulled down to ground through a diode to increase the

switching frequency. The pin block diagram is shown in 图7-19.

图7-20 shows the timing diagram of the LL/SS pin programming. It includes 5 phases:

• SS pull low phase - LL/SS pin is internally pulled low with a typical 1.2 kΩresistor to ground.

• SS initial voltage program phase - The internal pull low is released. As shown in 图7-19, LL/SS pin is

typically connected with a resistor divider from RVCC and a capacitor to ground. When the internal pull low

circuit is released, LL/SS pin voltage can be charged up depending on the external resistor and capacitor.

This phase ends when charge boot stage is completed and it has a fixed time of t_{SSInitVolPrgm}

.

• Soft start phase - An internal constant current source charges the soft start capacitor right after the charge

boot stage, and ends when FBreplica becomes lower than the LL/SS pin voltage. During this phase, LL/SS

pin voltage is used as the control effort V_comp. The slow ramp up of LL/SS pin helps the LLC operate at a

higher switching frequency when the output voltage is not established yet during startup. This can avoid the

large inrush current during startup.

• BMT_Lsettling phase - When soft start phase is completed, LL/SS pin is used for burst mode threshold

programming. As described in 节7.4.3, two burst mode thresholds are used. During this phase, BMT_His

fixed at either 0.6V (1.2 V if BW option 7 is selected). BMT_Lis also fixed which is determined by the

programmed ratio of BMT_L/BMT_H. The typical duration of this phase is 600 us.

• BMT_Land BMT_Hprogramming/setting phase - LL/SS pin is buffered at 3.5 V during this phase. Depending on

the resistors connected to the pin, LL/SS pin could either sink or source current. If LL/SS pin sinks current,

the current will be internally mirrored to flow through R_LL, and the voltage on R_FBis the programmed voltage

of BMT_H. If LL/SS pin sources current, the programmed voltage of BMT_His set to minimal. If the programmed

voltage of BMT_His different from the initial voltage, BMT_Hramps to the target value at a refresh frequency of

every 200 us. The slow refresh frequency makes sure that BMT_Hdoes not change due to the noise on LL/SS

pin. BMT_Lfollows the change of BMT_Hbased on the programmed ratio of BMT_L/BMT_H.

The programmability of the SS initial voltage provides a freedom to limit the maximum switching frequency

during startup. This helps to prevent hard switching due to excessively high switching frequency. For applications

that require very high switching frequency during startup, an option is also provided to disable the SS initial

voltage programming through BW pin, as described in 节 7.4.3.2. If this option is selected, LL/SS pin continues

pull low with the internal 1.2 kΩresistor during the SS initial voltage program phase.

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AVDD

To RVCC

ChargeSS

LL/SS

9

SS

Rdischarge

ZCS

Burst

Threshold

Gen

BMT_H

SS Pin

Initial Vol

Prog

V_SSinit

图7-19. LL/SS Block Diagram

FB_replica

Burst Mode Disabled

BMT_H

LL/SS pin

BMT_L

SS Initial Voltage

Program Phase

BMT_LProgram

Phase

BMT_Land BMT_HThreshold

Setting Phase

Soft Start Phase

图7-20. Timing Diagram of LL/SS Pin Programming

7.4.3.2 BMT_L/BMT_HRatio Programming

As described in 节 7.3.7, BW pin is multiplex for BMT_L/BMT_Hratio programming. The programming phase

happens only once before startup. After that, the BMT_L/BMT_Hratio is then fixed, until system restarts after a fault

or power recycle. The programming phase occurs right before soft start begins. It sources a constant current and

measures the voltage on the pin. Depending on the measured pin voltage, different ratio of BMT_L/BMT_His

selected as listed in 表7-2. The required BW equivalent resistance is listed in electrical characteristics section.

Other than selecting different BMT_L/BMT_Hratios, the option 5 also disables the LL/SS pin initial voltage program

phase during startup, and the option 7 disables the burst mode.

表7-2. BMT_L/BMT_HRatio Programming

Option

BMT_L/BMT_H

1

0.95

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表7-2. BMT_L/BMT_HRatio Programming (continued)

Option

BMT_L/BMT_H

2

3

4

5

6

7

1

0.9

0.8

0.6 (LL/SS pin initial voltage programming disabled)

0.6

0.4 (Burst Mode Disabled)

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7.4.4 System State Machine

Below is an overview of the system states sequence:

The state transition diagram starts from the un-powered condition of UCC25640x. For device variants that has

HV startup, as soon as the AC input is plugged in, the internal JFET of the HV pin will be enabled and will start to

deliver current from a source connected from the HV pin to the VCC capacitor. Once the VCC pin voltage

exceeds its VCC_{StartSwitching}threshold, the system state will change to JFETOFF. For device variants which does

not have HV startup feature, there is no JFETon state. Once VCC exceeds its VCC_{StartSwitching}threshold, the

system state will change to JFETOFF. When the PFC output voltage reaches a certain level, the LLC is turned

on. Before the LLC starts running, the LO pin is kept high to pull the HS node of the LLC bridge low, thus

allowing the capacitor between the HB and HS pins to be charged from VCC via the bootstrap diode.

UCC25640x will remain in the CHARGE_BOOT state for a certain time to ensure the boot capacitor is fully

charged. When the LLC output voltage reaches a certain level, both PFC and LLC controllers get power from the

LLC transformer bias winding. When the load drops below a certain level, the LLC operates in burst mode.

Fault conditions encountered by UCC25640x will cause normal operation to stop, or pause for a certain period of

time followed by an automatic re-start. This is to ensure that while a persistent fault condition is present, it is not

possible for the temperature of UCC25640x controller or the power converter to rise as a result of the repeated

re-start attempts.

BWOVP

OTP

OCP1

OCP2

WaveGenEn

RVCCEn

OCP3

BLKStart

System states

and faults

BLKStop

RVCCUVLO

SSEn

VCCReStartJfet

VCCStartSwitching

ACZeroCrossing

HVFetOn

FBLessThanBMT

图7-21. Block Diagram of System State Machine

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表7-3 summarizes the inputs and outputs of 图7-21.

表7-3. System State Machine Block Inputs and Outputs

SIGNAL NAME

BWOVP

I/O

DESCRIPTION

I

Output over voltage fault

Over temperature fault

Peak current fault

OTP

OCP1

I

OCP2

I

Average current fault with 2 ms timer

Average current fault with 50 ms timer

Bulk voltage is above start threshold

Bulk voltage is below stop threshold

RVCC UVLO fault

OCP3

I

BLKStart

I

BLKStop

I

RVCCUVLO

VCCReStartJfet

VCCStartSwitching

ACZeroCrossing

WaveGenEn

RVCCEn

I

VCC is below restart threshold

VCC is above start switching threshold

AC zero crossing is detected

Waveform generator enable

RVCC enable

I

O

SSEn

Soft start enable

HVFetOn

Turn on or off JFET

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The state machine is shown in 图 7-22 and the description of the states and state transition conditions are in the

tables below.

AC plug in

STARTUP

1

12

JFETON

2

13

7

JFETOFF

3

18

14

8

WAKEUP

4

FAULT

15

9

LLSS/BW Programming

5

10

16

17

CHARGE_BOOT

6

11

STEADY_STATE_RUN

图7-22. System State Machine Transition

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表7-4. States in System State Machine

STATE

OUTPUT STATUS

DESCRIPTION

WaveGenEn = 0

RVCCEn = 0

SSEn = 0

HVFetOn = 0

STARTUP

JFETON

This is the first state after AC input is plugged-in for the system to load trim.

WaveGenEn = 0

RVCCEn = 0

SSEn = 0

In this state, the JFET is on. VCC is charged with a current source connected from

HV pin. For device variants that does not have HV startup feature, this state does

not exist.

HVFetOn = 1

WaveGenEn = 0

RVCCEn = 1

SSEn = 0

When VCC is higher than VCCStartSwitching threshold, the JFET is turned off and

the system enters JFETOFF state. The regulated RVCC is turned on. If RVCC is

supplied to PFC voltage supply pin, PFC soft start begins.

JFETOFF

HVFetOn = 0

WaveGenEn = 0

RVCCEn = 1

SSEn = 0

When BLK voltage reaches BLKStart level, the system enters WAKEUP state and

stays in WAKEUP state for a short time for the analog circuits to wake up.

WAKEUP

HVFetOn = 0

WaveGenEn = 0

RVCCEn = 1

SSEn = 0

In this state, the system goes through the LL/SS pin and BW pin programming

phase.

LLSS/BW Programming

CHARGE_BOOT

STEADY_STATE_RUN

FAULT

HVFetOn = 0

WaveGenEn = 0

RVCCEn = 1

SSEn = 0

In this state, the BOOT capacitor is charged by turning on the low-side switch for a

certain period of time. The programmed initial voltage is buffered to LL/SS pin.

HVFetOn = 0

WaveGenEn = 1

RVCCEn = 1

SSEn = 1

In this state, the waveform generator is enabled. Soft start module is enabled. The

LLC starts to soft start. When soft start is done, the system enters normal

operation.

HVFetOn = 0

WaveGenEn = 0

RVCCEn = 0

SSEn = 0

In fault state, the waveform generator is disabled to stop switching. The system will

stay in FAULT state for 1 s before re-start. The 1 s timer allows the system to cool

down and prevents frequent repetitive start ups in case of a persistent fault.

HVFetOn = 0

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表7-5. System State Machine Transition Conditions

STATE TRANSITION

CONDITION

DESCRIPTION

1

2

System ready (trim load done)

VCCStartSwitching = 1

VCCReStartJfet = 0

BLKStart = 1

BLKStop = 0

RVCCUVLO = 0

3

4

BLKStart = 1

BLKStop = 0

RVCCUVLO = 0

FBLessThanBMT = 0

5

6

LLSS/BW programming done

Charge boot done

VCCReStartJfet = 1

OTP = 1

7

8

9

10

11

12

13

14

15

16

OTP = 1

OTP = 1 or BLKStop = 1 or BWOVP = 1 or

OCP1 = 1 or OCP 2 = 1 or OCP3 = 1 or

RVCCUVLO = 1

17

18

1 s pause time out

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图 7-23 and 图 7-24 show the most commonly used state transition (assuming no faults during start up states so

all the states are captured in the timing diagram). Many different ways of state transitions may happen according

to the state machine, but are not captured in this section.

In 图 7-24, a normal start up procedure is shown. The system enters normal operation and then a fault (OCP,

OVP, or OTP) happens.

AC plug in

VCC

VCCStartSwitching

PFC output voltage

RVCC

LLC output voltage

LLC gate drive

waveforms

STEADY_STATE_RUN

STARTUP

STEADY_STATE_RUN

FAULT

STARTUP

System state

WAKEUP

CHARGE_BOOT

WAKEUP

CHARGE_BOOT

图7-23. Timing Diagram of System State Machine for UCC256403

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AC plug in

VCCStartSwitching

VCC

VCCReStartJfet

VCCShort

PFC output voltage

RVCC

LLC output voltage

LLC gate drive

waveforms

STEADY_STATE_RUN

STARTUP

JFETON

JFETOFF

STEADY_STATE_RUN

FAULT JFETON JFETOFF

System state

WAKEUP CHARGE_BOOT

图7-24. Timing Diagram of System State Machine for UCC256402 and UCC256404

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Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

UCC25640x can be used in a wide range of applications in which LLC topology is implemented. In order to make

the part easier to use, TI has prepared a list of materials to demonstrate the features of the device:

• Full featured EVM hardware

• An excel design calculator

• Simulation models

• Application notes on Hybrid Hysteretic Control theory

In the following sections, a typical design example is presented.

8.2 Typical Application

Shown below is a typical half bridge LLC application using UCC25640x as the controller.

Cr

Lr

Lm

HO

Vout

HS

VIn

BLK

VCC

BW

LO

FB

AC Line

HS

HV

1

16

15

14

HS

HO

HB

AC Neutral

RHV

HO

CBOOT

VCC

3

4

5

6

7

8

VCC

UCC25640x

LLC

Controller

BLK

FB

BLK

FB

RVCC

GND

12

11

10

9

ISNS

VCR

BW

LO

LL/SS

BW

CSS

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8.2.1 Design Requirements

The design specifications are summarized in 表8-1 .

表8-1. System Design Specifications

PARAMETER

INPUT CHARACTERISTICS

DC Voltage range

TEST CONDITIONS

MIN

TYP

MAX

UNITS

365

85

390

410

264

VDC

VAC

Hz

AC Voltage range

AC Voltage frequency

Input DC UVLO On

47

63

365

315

VDC

Input DC UVLO Off

OUTPUT CHARACTERISTICS

Output voltage, VOUT

Output load current, IOUT

Output voltage ripple

No load to full load

12

VDC

A

360 VDC to 410 VDC

15

390 VDC and full load = 10 A

120

mVpp

SYSTEMS CHARACTERISTICS

Resonant Frequency

100

92

kHz

°C

Peak efficiency

390 VDC

Operating temperature

Natural convection

25

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8.2.2 Detailed Design Procedure

8.2.2.1 LLC Power Stage Requirements

Start the design by deciding the LLC power stage component values. The LLC power stage design procedure

outlined here follows the one given in the TI application note “Designing an LLC Resonant Half-Bridge Power

Converters”. The application note contains a full explanation of the origin of each of the equations used. The

equations given below are based on the First Harmonic Approximation (FHA) method commonly used to analyze

the LLC topology. This method gives a good starting point for any design, but a final design requires an iterative

approach combining the FHA results, circuit simulation, and hardware testing. An alternative design approach is

given in TI application note SLUA733, LLC Design for UCC29950.

8.2.2.2 LLC Gain Range

First, determine the transformer turns ratio by the nominal input and output voltages.

V

/ 2

IN nom

390 / 2

12

(

)

V_{OUT nom}

N_PS

=

= 16.25 Ω 16.5

(

)

(4)

Then determine the LLC gain range M_G(min)and M_G(max). Assume there is a 0.5-V drop in the rectifier diodes (V_f)

and an additional 0.5-V due to other losses (V_loss).

V_{OUT min}+V_f

12 + 0.5

410 / 2

(

)

M_{G min}= N_PS

= 16.5

= 1.006

(

)

V

/ 2

IN max

(

(5)

(6)

V_{OUT max}+V +V

f

loss

12 + 0.5 + 0.5

365 / 2

(

)

M_{G max}= N_PS

= 16.5

= 1.175

(

)

V

/ 2

IN min

(

)

8.2.2.3 Select L_nand Q_e

L_Nis the ratio between the magnetizing inductance and the resonant inductance.

L_M

L_N=

L_R

(7)

Q_Eis the quality factor of the resonant tank.

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L_R/ C_R

Q_E=

R_E

(8)

In this equation, R_Eis the equivalent load resistance.

Selecting L_Nand Q_Evalues should result in an LLC gain curve, that intersects with M_G(min)and M_G(max)traces.

The peak gain of the resulting curve should be larger than M_G(max). Details of how to select L_Nand Q_Eare not

discussed here. They are available in the UCC25640x Design Calculator.

In this case, the selected L_Nand Q_Evalues are:

L_N= 6

(9)

Q_E= 0.3

(10)

8.2.2.4 Determine Equivalent Load Resistance

Determine the equivalent load resistance by 方程式11.

2

8ì16.5²12

V_{OUT nom}

8ìN_PS

(

I_{OUT nom}

)

R_E=

ì

=

ì

= 176.5W

Œ²

15

(

)

(11)

8.2.2.5 Determine Component Parameters for LLC Resonant Circuit

Before determining the resonant tank component parameters, a nominal switching frequency (resonant

frequency) should be selected. In this design, 100 kHz is selected as the resonant frequency.

f₀= 100kHz

(12)

The resonant tank parameters can be calculated as the following:

1

C_R=

=

= 30.0nF

2Œ ìQ_Eìf₀ìR_E2Œ ì0.3ì100kHz ì176.5W

(13)

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1

L_R=

=

= 84.4mH

2Œ ìf ²C_R

2Œ ì100kHz ²ì30.0nF

(

)

(

)

0

(14)

(15)

L_M= L_NìL_R= 6ì84.4 mH = 506.4mH

After the preliminary parameters are selected, find the closest actual component value that is available, re-check

the gain curve with the selected parameters, and then run time domain simulation to verify the circuit operation.

The following resonant tank parameters are:

C_R= 30nF

(16)

L_R= 85 mH

(17)

L_M= 510 mH

(18)

Based on the final resonant tank parameters, the resonant frequency can be calculated:

1

f₀=

=

= 99.7kHz

2Œ L_RC_R2Œ 30nF ì85 mH

(19)

Based on the new LLC gain curve, the normalized switching frequency at maximum and minimum gain are given

by:

f_{N Mgmax}= 0.7

(

)

(20)

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f_{N Mgmin}= 1.0

(

)

(21)

The maximum and minimum switching frequencies are:

f_{SW Mgmax}= 69.8kHz

(

)

(22)

(23)

f_{SW Mgmin}= 99.7kHz

(

)

8.2.2.6 LLC Primary-Side Currents

The primary-side currents are calculated for component selection purposes. The currents are calculated based

on a 110% overload condition.

The primary side RMS load current is given by:

I_o

Œ

1.1ì15 A

16.5

I_OE

=

ì

=

ì

= 1.111A

n

2 2

(24)

The RMS magnetizing current at minimum switching frequency is given by:

N_PSV_OUT

2 2

16.5ì12

2Œ ì 64.8kHz ì510mH

I_M

=

ì

=

ì

= 0.797A

Œ

&L_M

Œ

(25)

The total current in resonant tank is given by:

2

I_R= I_M²+ I_OE

=

1.111A ²+ 0.797A = 1.367A

2

(

)

(

)

(26)

8.2.2.7 LLC Secondary-Side Currents

The total secondary side RMS load current is the current referred from the primary side current (I_OE) to the

secondary side.

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I_OES= N_PSìI_OE= 16.5ì1.111A = 18.327A

(27)

In this design, the transformer’s secondary side has a center-tapped configuration. The current of each

secondary transformer winding is calculated by:

2 ìI_OES

2 ì18.327 A

I_WS

=

= 12.959 A

2

(28)

The corresponding half-wave average current is:

2 ìI_OES

Œ

2 ì18.327 A

I_SAV

=

= 8.250 A

Œ

(29)

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8.2.2.8 LLC Transformer

A bias winding is needed in order to utilize the HV self start up function. It is recommended to design the bias

winding so that the VCC voltage is greater than 13 V.

The transformer can be built or purchased according to these specifications:

• Turns ratio: Primary : Secondary : Bias = 33 : 2 : 3

• Primary terminal voltage: 450 V_ac

• Primary magnetizing inductance: L_M= 510 µH

• Primary side winding rated current: I_R= 1.367 A

• Secondary terminal voltage: 36 V_ac

• Secondary winding rated current: I_WS= 12.959 A

• Minimum switching frequency: 69.8 kHz

• Maximum switching frequency: 99.7 kHz

• Insulation between primary and secondary sides: IEC60950 reinforced insulation

The minimum operating frequency during normal operation is calculated above. Please note that for some

applications that operate as a wide input LLC where the PFC may be shut off in standby mode, the operating

frequency may be much lower during heavy load shutdown and the LLC can operate at just above the ZCS

boundary which is a lower frequency. The magnetic components in the resonant circuit, the transformer and

resonant inductor, should be rated to operate at this lower frequency.

8.2.2.9 LLC Resonant Inductor

The AC voltage across the resonant inductor is given by its impedance multiplied by the current:

V_L= &L_RI_R= 2Œ ì 69.8kHzì85mHì1.367A = 50.946V

R

(30)

The inductor can be built or purchased according to the following specifications:

• Inductance: L_R= 85 µH

• Rated current: I_R= 1.367 A

• Terminal AC voltage: 50.946 V

• Frequency range: 69.8 kHz to 99.7 kHz

Please note some designs may utilize the leakage inductance of the transformer as the resonant inductance and

do not require an external resonant inductor.

8.2.2.10 LLC Resonant Capacitor

This capacitor carries the full-primary current at the switching frequency. A low dissipation factor capacitor is

needed to prevent overheating.

The AC voltage across the resonant capacitor is given by its impedance multiplied by the current.

I_R

1.367A

V_CR

=

= 104.0V

&C_R2Œ ì 69.8kHz ì30nF

(31)

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2

V

≈

∆

’

÷

IN max

(

2

)

410

2

≈

’

V_{CR rms}

=

+V_C²_R

=

+104.0²= 229.9V

∆

«

÷

◊

(

)

∆

«

÷

◊

(32)

Peak voltage:

V

IN max

(

2

410

2

)

V_{CR peak}

=

+ 2V_CR

=

+ 2 ì104.0 = 352.0V

(

)

(33)

Valley voltage:

V

IN max

(

2

410

2

)

V_{CR valley}

=

- 2V_CR

=

- 2 ì104.0 = 58.0V

(

)

(34)

(35)

Rated current:

I_R= 1.367 A

8.2.2.11 LLC Primary-Side MOSFETs

Each MOSFET sees the input voltage as its maximum applied voltage. Choose the MOSFET voltage rating to be

1.5 times of the maximum bulk voltage:

V_{QLLC peak}= 1.5 ìV

= 615V

IN max

(

)

(36)

(37)

Choose the MOSFET current rating to be 1.1 times of the maximum primary side RMS current:

I_QLLC= 1.1ìI_R= 1.504 A

8.2.2.12 LLC Rectifier Diodes

The voltage rating of the output diodes is given by:

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V

IN max

410

(

N_PS

)

V_DB= 1.2ì

= 1.2ì

= 29.82V

16.5

(38)

The current rating of the output diodes is given by:

2 ìI_OES

Œ

2 ì18.329

I_SAV

=

= 8.250 A

Œ

(39)

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8.2.2.13 LLC Output Capacitors

The LLC converter topology does not require an output filter although a small second stage filter inductor may be

useful in reducing peak-to-peak output noise. Assuming that the output capacitors carry the rectifier’s full wave

output current then the capacitor ripple current rating is:

Œ

I_RECT

=

I_OUT

=

ì15 = 16.66A

2 2

(40)

Use 20 V rating for 12-V output voltage:

V_LLCcap= 20V

(41)

The capacitor’s RMS current rating is:

2

≈

∆

«

’

≈

∆

«

’

Œ

I_{C out}

=

I_OUT- I_O²_UT

=

ì15 -15²= 7.251A

÷

(

)

2 2

◊

(42)

Solid Aluminum capacitors with conductive polymer technology have high ripple-current ratings and are a good

choice, especially if the design is required to operate at colder temperatures. The ripple-current rating for a

single capacitor may not be sufficient so multiple capacitors are often connected in parallel.

The ripple voltage at the output of the LLC stage is a function of the amount of AC current that flows in the

capacitors. To estimate this voltage, assume that all the current, including the DC current in the load, flows in the

filter capacitors.

V_{OUT pk-pk}

(

)

0.12V

ESR_max

=

= 5.1mW

Œ

I_{RECT pk}

(

)

2

ì15 A

4

(43)

The capacitor specifications are:

• Voltage Rating: 20 V

• Ripple Current Rating: 7.251 A

• ESR: < 5.1 mΩ

8.2.2.14 HV Pin Series Resistors

Multiple resistors are connected in series with HV pin to limit the power dissipation of the UCC25640x device.

The recommended series resistor with HV pin is 5 kΩ.

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8.2.2.15 BLK Pin Voltage Divider

BLK pin senses the LLC input voltage and determines when to turn on and off the LLC converter. Different

versions of UCC25640x have different BLK thresholds.

Choose bulk startup voltage at 365 V, then the BLK resistor divider ratio can be calculated as below:

365V

k_BLK

=

= 365

1V

(44)

The desired power consumption of the BLK pin resistor divider is P_BLKsns= 10 mW. The BLK sense resistor total

value is given by:

V²

390²

IN nom

(

P_BLKsns

)

R_BLKsns

=

= 15.21MW

0.01

(45)

The lower BLK divider resistor value is given by:

R_BLKsns

15.21MW

365

R_BLKlower

=

= 41.67kW

k_BLK

(46)

A standard value of 41.2 kΩis selected for R_BLKlower.The higher BLK divider resistor value is given by:

R_BLKupper= R_BLKsns- R_BLKlower= 15.17MW

(47)

A standard value of 3x 4.99 MΩ in series is selected for R_BLKupper. The actual bulk voltage thresholds can be

calculated:

V_BulkStart= 365V

(48)

0.9

V_BulkStop= 365V ì

= 328.5V

1

(49)

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8.2.2.16 ISNS Pin Differentiator

ISNS pin sets the over current protection level. OCP1 is peak current protection level; OCP2 and OCP3 are

average current protection levels. The typical threshold voltages are 4.0 V, 0.6 V, and 0.43 V, respectively.

Set OCP3 level at 130% of full load. Thus, the sensed average input current level at full load is given by:

0.43V

V

=

= 0.331V

ISNSfullload

130%

(50)

The current sense ratio can then be calculated:

V

0.331V

180W

ISNSfullload

k_ISNS

=

= 0.66W

≈

∆

«

’

÷

◊

≈

∆

«

’

÷

◊

1

P_OUT

1

ì

0.92 390V

ꢀ

V_bulknom

(51)

(52)

Select a current sense capacitor first, since there are less high voltage capacitor choices than resistors:

C_ISNS= 150 pF

Then calculate the required ISNS resistor value:

k_ISNSC_r

C_ISNS

0.66Wì30nF

150 pF

R_ISNS

=

= 132 W

(53)

After the current sense ratio is determined, the peak ISNS pin voltage at full load can be calculated:

V

= 2I_rìk_ISNS= 2 ì1.367Aì0.66 W = 1.29V

ISNSpeak

(54)

The peak resonant current at OCP1 level is given by:

4V ìC_R

R_ISNSìC_ISNS133Wì150pF

4V ì30nF

I_respeakOCP1

=

= 6.02A

(55)

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The peak secondary-side current at OCP1 level is given by:

I_secpeakOCP1= I_respeakOCP1ìN_PS= 6.02Aì16.5 = 99.33A

8.2.2.17 VCR Pin Capacitor Divider

(56)

The capacitor divider on the VCR pin sets two parameters: (1) the divider ratio of the resonant capacitor voltage;

(2) the amount of frequency compensation to be added. The first criteria the capacitor divider needs to meet is

that under over load condition, the peak-to-peak voltage on the VCR pin is with in 6 V. It is recommended to size

the VCR capacitance to give a total peak to peak voltage between 3 V and 4.5 V at full load with the frequency

compensation ramp contributing between 1 V and 2 V to the total VCR peak to peak voltage. For this design, the

VCR pin capacitance was selected to give a maximum peak to peak voltage of approximately 4.25 V at full load

with the internal ramp contributing 1.75 V to the total VCR waveform.

The required VCR capacitance can be calculated directly from the resonant capacitor peak to peak voltage and

the minimum expected switching frequency.

V_CR(pk-pk)= V_CR(peak)- V_CR(valley)= 352V - 58V = 294V

(57)

Based on the expected peak to peak resonant capacitor voltage, the required capacitor divider ratio can be

derived

V_CR(pk-pk)

V_{VCRpin(pk-pk)}- V_Ramp(pk-pk)4.25V -1.75V

294V

k_CapDiv

=

= 117.6

(58)

From the expected minimum switching frequency, the lower VCR capacitance can be derived

I_Ramp

V_Ramp(pk-pk)2ìF_{SW _min}1.75V 2ì69.8kHz

1

2mA

C_VCRlower

=

ì

=

ì

= 8.2nF

(59)

A standard value of 8.2 nF is chosen for the lower VCR capacitor. From the selected lower VCR capacitor and

calculated capacitor divider ratio, the upper VCR capacitance is given by:

C_VCRlower

8.2nF

C_VCRupper

=

= 70.6pF

k_CapDiv-1 117.6 -1

(60)

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A standard value of 68 pF is selected for the upper VCR capacitor. From the selected upper and lower VCR

capacitors, the actual peak to peak voltage on the VCR pin can be calculated

C_VCRlower

8.2nF

68pF

k_CapDiv

=

+1=

+1= 121.59

C_VCRupper

(61)

I_Ramp

V_CR(pk-pk)

1

2mA

294V

V_{VCRpin(pk-pk)}

=

ì

+

=

ì

+

= 4.17V

C_VCRlower2ìF_SW(Mgmin)

k_CapDiv

8.2nF 2ì 69.8kHz 121.59

(62)

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8.2.2.18 BW Pin Voltage Divider

The BW pin programs the ratio between burst mode entry and exit thresholds as well as senses the output

voltage through the bias winding and protects the power stage from over voltage. The nominal output voltage is

12 V. The bias winding has 3 turns, and the secondary side winding has 2 turns. Assuming there is a 0.5-V drop

in the rectifier diodes (Vf) and a further 0.5-V drop due to other losses (Vloss), the nominal voltage of the bias

winding is given by:

3

V_{BiasWindingNom}= 12V + 0.5V + 0.5V ì = 19.5V

(

)

2

(63)

The desired OVP threshold in this design is 140% of the nominal value. The OVP threshold level in UCC25640x

device is 4 V, so the nominal BW pin voltage is given by:

4V

V_BWnom

=

= 2.86V

140%

(64)

The required BW divider ratio is then given by:

V_{BiasWindingNom}ì h_OVP

19.5V ì140%

4V

k_BW

=

= 6.825

V_BWOVP

(65)

In this design, the burst mode threshold ratio is chosen to be 0.6 (Option 6).The target programming resistance

is then:

R_{BMT _Pr ogram}= 4.59kW

(66)

The lower BW resistor can be calculated by:

≈

’

÷

◊

1

≈

’

R_BWlower= R_{BMT _Pr ogram}ì 1+

= 4.59kWì 1+

= 5.38kW

∆

÷

◊

k_BW-1

6.825 -1

«

(67)

A standard value of 5.36 kΩis chosen for the lower BW resistor.

The upper resistor can be calculated by:

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V

_{BiasWindingNom}- V_BWNom

≈

’

19.5V - 2.86V

2.86V

≈

’

R_BWUpper= R_BMWLower

ì

= 5.36kWì

= 31.32kW

∆

÷

∆

«

÷

◊

V_BWNom

«

◊

(68)

A standard value of 30.9 kΩis chosen for the upper BW resistor.

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8.2.2.19 Soft Start and Burst Mode Programming

The LL/SS and BW pins allow the designer to select a burst mode threshold as well as program hysteresis for

entering and exiting burst mode. The resistor divider of connected to the LL/SS pin sets the BMT_Hthreshold

while the BW pin sets the ratio between BMT_Land BMT_H. In addition to programming the burst mode threshold,

the LL/SS pin provides the capability to program an initial voltage onto the LL/SS pin in order to limit the

maximum switching frequency during startup. For initial selection of LL/SS components, it is recommended to

select an initial LL/SS pin voltage between 0 V and 1 V and to select burst mode threshold between 1 V and 2 V.

The LL/SS pin parameters can be fine tuned later based on bench measurement.

In this design, an initial LL/SS pin voltage of 0.3 V and a BMT_Hthreshold of 0.6 V are selected. The soft start

capacitor sets how quickly the voltage on the soft start capacitor rises. The soft start time varies with load

condition. At full load or over load condition, the soft start time is the longest. It is not easy to calculate the exact

soft start time value. However, it can be estimated that under full load condition, the longest possible soft start

time is determined by how quickly the soft start pin voltage rises to the maximum VCR peak to peak voltage. For

a start up time of 7.5 ms, the soft start capacitor is sized to be the following:

T_{SS _Max}

7.5ms

C_LL/SS= I_SS

ì

= 37.5mA ì

= 72.7nF

V_VCR(pk-pk)- V_{LL/SS _precharge}

4.17V - 0.3V

(69)

A standard value of 68nF is selected for the soft start capacitor. In order to properly select the resistors on

LL/SS, first define R_THas the equivalent resistance on the LL/SS pin and V_THas the equivalent voltage source

on the LL/SS pin.

R_TH= R_{LL/SS _Upper}|| R_{LL/SS _Lower}

(70)

R_THìRVCC

R_{LL/SS _Upper}

V_TH

=

(71)

During the SS pull low phase, the voltage on the LL/SS pin is internally pulled down through a 1.2 kΩ resistor.

During the SS initial program phase, the internal pulldown is released and the soft start capacitor is allowed to

naturally charge up from RVCC. The total voltage offset on the LL/SS soft start capacitor can be calculated using

the equation below.

-t

≈

’

≈

∆

’

÷

SSInitPr gm

∆

÷

1.2kWìRVCC

R_{LL/SS _Upper}

C_SS

◊

V_ssinit

=

+ V_TH1- e^«

∆

÷

◊

«

(72)

Substituting for RVCC/R_{LL/SS_Upper}and using a linear approximation for the exponential term, the equation can

be simplified to the following.

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V_THì t_{SSInitVolPr gm}

1.2kWì V_TH

R_TH

V_ssinit

=

+

R_THìC_SS

(73)

The current used by the LL/SS pin to program BMT_H, I_BMT, has the following relationships. I_BMTcan be directly

solved for based on the desired BMT_Hthreshold.

BMT_H

R_LL

0.6V

I_BMT

=

= 6.12mA

98kW

(74)

(75)

V_TH- 3.5V

R_TH

I_BMT

=

Rearranging 方程式73, V_THand R_THcan now be calculated.

3.5V

V_TH

=

= 4.71V

t_{SSInitVolPr gm}

6.12mA

0.3V

776ms

68nF

≈

’

≈

’

I_BMT

1-

1.2kW +

1-

1.2kW +

∆

÷

◊

∆

÷

«

V_ssinit

C_SS

«

◊

(76)

(77)

4.71V - 3.5V

I_BMT

R_TH

=

= 197kW

Values for R_{LL/SS_Upper}and R_{LL/SS_Lower}can be determined from V_THand R_TH

R_THìRVCC

V_TH

197kWì13V

4.71V

R_{LL/SS _Upper}

=

= 544kW

(78)

A standard value of 549 kΩis selected for R_{LL/SS_Upper}

.

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R_THìR_{LL/SS_Upper}

197kWì549kW

R_{LL/SS_Lower}

=

= 307kW

R_{LL/SS_Upper}-R_TH549kW -197kW

(79)

A standard value of 316 kΩis selected for R_{LL/SS_Lower}

.

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8.2.3 Application Curves

Light Load Power Consumption

0.33

0.3

0.27

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

Input Voltage

390Vin

0

0.05

0.1 0.15

Output Power (W)

0.2

0.25

D000

图8-2. Light Load Power Consumption

图8-1. Efficiency

图8-3. Burst Mode with Soft On/Off (Ch2 = VCR, Ch3 = LO, Ch4 = Resonant Current)

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8 Power Supply Recommendations

8.1 VCC Pin Capacitor

The VCC capacitor should be sized based on the total start-up charge required by the system. The start-up

charge will mostly be consumed by the gate driver circuit. Thus the total start-up charge can be estimated by the

start-up switching frequency, MOSFET gate charge, and the soft-start time.

Assume the total start-up charge required by the system is shown in 方程式80

Q

= 1.6mC

tot

(80)

During PFC and LLC startup phase, the maximum VCC voltage drop allowed is

V_ccdropmax= 26V - 9.65V = 16.35V

(81)

The minimum VCC capacitor needed:

Q_tot

C_VCC

=

= 97.86 ꢀF

V_ccdropmax

(82)

Choose at least 100 µF capacitor or combination of capacitors.

8.2 Boot Capacitor

During burst off period, power consumed by the high-side gate driver from the HB pin must be drawn from C_BOOT

and will cause its voltage to decay. At the start of the next burst period there must be sufficient voltage remaining

on C_BOOTto power the high-side gate driver until the conduction period of LO allows it to be replenished from

C_RVCC. The power consumed by the high-side driver during this burst off period will therefore have a direct

impact on the size and cost of capacitors that must be connected to HB and RVCC.

Assume the system has a maximum burst off period of 150 ms and the bootstrap diode has a forward voltage

drop of 1V. Target a minimum bootstrap voltage of 8 V to avoid UVLO fault. The maximum allowable voltage

drop on the boot capacitor is:

V_bootmaxdrop=V_RVCC-V_{bootforwarddrop}- 8V = 13V -1V - 8V = 4V

(83)

Boot capacitor can then be sized:

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I_{BOOT _ QUIESCENT}ì t_maxoff

62mA ì150ms

4V

C_boot

=

= 2.32mF

V_{bootforwarddrop}

(84)

8.3 RVCC Pin Capacitor

The RVCC capacitor needs to be at least 5 times greater than boot capacitor. In addition, sizing of the RVCC

capacitor depends on the stability of the RVCC LDO. If the load is light on RVCC, smaller capacitors can be

used. The larger the load, the larger the capacitor is needed. In a typical system, the RVCC LDO powers the

PFC and LLC gate drivers.

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9 Layout

9.1 Layout Guidelines

• Put a 2.2-µF ceramic capacitor on VCC pin in addition to the energy storage electrolytic capacitor. The 2.2-µF

ceramic capacitor should be put as close as possible to the VCC pin.

• RVCC pin should have a bypass capacitor of 4.7 µF or more. It is recommended to add a 0.1-µF ceramic

capacitor in addition to the 4.7 µF. The capacitors should be put as close as possible to the RVCC pin. RVCC

cap is recommended to be size at least 5 times of boot capacitor.

• Minimum recommended boot capacitor, C_BOOT, is 0.1 µF. The minimum value of the boot capacitor needs to

be determined by the minimum burst frequency. The boot capacitor should be large enough to hold the

bootstrap voltage during the lowest burst frequency. Please refer to the boot leakage current in the electrical

table.

• Signal ground and power ground should be single-point connected. Power ground is recommended to

connect to the negative terminal of the LLC input bulk capacitor.

• The filtering capacitors for ISNS and BLK should be put as close as possible to the pins.

• The bottom capacitor on VCR should be put as close as possible to the VCR pin.

• FB trace should be as short as possible

• Soft-start capacitor should be put as close as possible to LL/SS pin

• Use film capacitors or C0G, NP0 ceramic capacitors for the VCR divider and ISNS capacitor for low distortion

• Add necessary filtering capacitors on the BW pin to filter out the high spikes on the bias winding waveform. It

is critical to filter out the high spikes because internally the signal is peak detected and then sampled at the

low-side turn off edge.

• Keep necessary high voltage clearance and creepage.

• If 2 kV HBM ESD rating is needed on HV pin, it is acceptable to place a 100 pF capacitor from the HV pin to

ground in order to pass up to 2 kV HBM ESD.

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9.2 Layout Example

HV

HS

HO

HB

1

16

15

14

VCC

BLK

FB

3

4

5

6

7

8

UCC25640x

LLC

Controller

L

N

RVCC

GND

LO

12

11

10

9

ISNS

VCR

BW

+

LL/SS

图9-1. Layout Example for Single-Layer PCB

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HV

HS

HO

HB

1

16

15

14

VCC

3

UCC25640x

LLC

Controller

BLK

FB

4

5

6

7

8

RVCC

GND

LO

12

11

10

9

+

ISNS

VCR

BW

LL/SS

L

N

图9-2. Layout Example for Double-Layer PCB

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

• Design Spreadsheet, UCC25640x Design Calculator

• User Guide, Using UCC25640EVM-020

10.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

表10-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

UCC256402

UCC256403

UCC256404

Click here

10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

10.4 Community Resources

10.5 Trademarks

所有商标均为其各自所有者的财产。

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

DDB0014A

SOIC - 1.75 mm max height

S

C

A

L

E

1

.

8

0

SOIC

C

6.2

5.8

TYP

SEATING PLANE

0.1 C

PIN 1 ID

AREA

A

10X 1.27

16

1

10.0

9.8

NOTE 3

2X

8.89

8

9

0.51

14X

4.0

3.8

NOTE 4

0.31

B

1.75 MAX

0.25

C A B

0.25

TYP

0.13

0.25

GAGE PLANE

SEE DETAIL A

0.25

1.27

0 - 8

0.10

0.40

DETAIL A

TYPICAL

4222925/A 04/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.

5. Reference JEDEC registration MS-012, variation AC.

www.ti.com

EXAMPLE BOARD LAYOUT

DDB0014A

SOIC - 1.75 mm max height

SOIC

14X (1.55)

14X (0.6)

SYMM

1

16

(4.445)

TYP

10X (1.27)

SYMM

(R0.05)

TYP

9

8

(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222925/A 04/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDB0014A

SOIC - 1.75 mm max height

SOIC

14X (1.55)

14X (0.6)

SYMM

1

16

(4.445)

TYP

14X (1.27)

SYMM

8

9

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:8X

4222925/A 04/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC256402ADDBR
厂家：	TEXAS INSTRUMENTS
描述：	具有超低待机功耗和高电压启动功能的 LLC 谐振控制器 \| DDB \| 14 \| -40 to 125 控制器开关光电二极管
文件：	总79页 (文件大小：3767K)
中文：	中文翻译
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UCC256402ADDBR [TI]

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