UCC25800L-Q1 [TI]
UCC25800-Q1 Open-Loop LLC Transformer Driver for Isolated Bias Supplies;
| 型号： | UCC25800L-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | UCC25800-Q1 Open-Loop LLC Transformer Driver for Isolated Bias Supplies |
| 文件： | 总44页 (文件大小：2579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC25800-Q1
SLUSDX3B – NOVEMBER 2020 – REVISED NOVEMBER 2021
UCC25800-Q1 Ultra-low EMI Transformer Driver for Isolated Bias Supplies
The transformer driver has a programmable frequency
1 Features
range of 100 kHz to 1.2 MHz. This high switching
frequency reduces the transformer size and footprint,
as well as the overall cost of the bias supply. The
integrated SYNC function allows the system bias
supplies to synchronize with an external clock signal,
further reducing the system level noise.
•
•
•
High-efficiency half-bridge transformer driver
Ultra-low EMI with low interwinding capacitance
Smaller and lower-cost transformer
– Programmable frequency: 0.1 MHz to 1.2 MHz
Wide input voltage range: 9 V to 34 V
– 9 W from 34-V input
•
The dead-time adjusts automatically to minimize
the conduction loss and simplify the design. The
programmable maximum dead-time ensures power
stage design flexibility.
– 6 W from 24-V input
– 4 W from 15-V input
•
Automatic dead-time adjustment with maximum
dead-time programming
With the integrated, low-resistance switching power
stage, the transformer driver can achieve a 6-W
design with 24-V input, and up to 9-W from 34-V
input. With a fixed input voltage, the open-loop control
also helps the output regulation to remain ±5% when
the load is above 10%.
•
•
External clock synchronization for low noise
Robust protection features
– Undervoltage lockout (UVLO)
– Programmable over-current protection (OCP)
– Input overvoltage protection (OVP)
– Over temperature protection (TSD)
– Integrated soft-start to reduce in-rush current
– External disable function with fault-code output
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
The programmable overcurrent protection (OCP)
allows flexibility on the power stage design to
minimize the transformer size. The protection features
such as adjustable OCP, input OVP, TSD and the
protection from pin faults ensure robust operation.
A fixed 1.5-ms soft-start period reduces the inrush
current during start-up and fault recovery.
•
•
•
8-Pin DGN package with thermal pad
The transformer driver also provides a dedicated
multi-function pin for external disabling, and fault code
reporting. The fault code reporting sends the fault
code once the bias supply is in the protection mode.
2 Applications
•
•
•
•
•
•
•
Automotive traction inverter & motor control
Automotive on-board charger (OBC)
Automotive DC/DC converter
EV charging station, DC fast charging station
UPS and solar inverters
Industrial motors, elevators and escalators
GaN, IGBT and SiC gate transformer driver bias
supply
The UCC25800-Q1 transformer driver is offered in an
8-pin DGN package with the thermal pad to enhance
its thermal handling capability.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
UCC25800-Q1
HVSSOP (8)
3.00 mm × 3.00 mm
3 Description
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
The UCC25800-Q1 ultra-low EMI transformer driver
integrates the switching power stage, the control, and
the protection circuits to simplify isolated bias supply
designs. It allows the design to utilize a transformer
with higher leakage inductance, but much smaller
parasitic primary-to-secondary capacitance. This low-
capacitance transformer design enables an order of
magnitude reduction in the common-mode current
injection through the bias transformer. This makes the
transformer driver an ideal solution for the isolated
bias supply in various automotive applications to
minimize the EMI noise caused by the high-speed
switching devices. The soft-switching feature further
reduces the EMI noise.
VIN
SYNC
VCC
DIS/FLT
VREG
SW
VOUT
GND
OC/DT
RT
Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC25800-Q1
SLUSDX3B – NOVEMBER 2020 – REVISED NOVEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................23
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Application.................................................... 25
8.3 What to Do and What Not to Do .............................. 33
9 Power Supply Recommendations................................34
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 35
11 Device and Documentation Support..........................36
11.1 Documentation Support ......................................... 36
11.2 Receiving Notification of Documentation Updates..36
11.3 Support Resources................................................. 36
11.4 Trademarks............................................................. 36
11.5 Electrostatic Discharge Caution..............................36
11.6 Glossary..................................................................36
12 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2021) to Revision B (November 2021)
Page
•
Updated data sheet status from Advance Information to Production Data ........................................................1
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5 Pin Configuration and Functions
SYNC
VCC
SW
1
2
3
4
8
7
6
5
DIS/FLT
VREG
GND
RT
Thermal pad
OC/DT
Figure 5-1. DGN Package, 8-Pin PDSO (Top View)
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
DIS/FLT
2
I/O
G
UCC25800-Q1 disable pin (active low) and fault code output pin.
The GND pin is the return for all the control and power signals. The layout should separate the
power and control signals.
GND
6
4
Voltage on this pin sets the maximum dead-time between the internal switching power devices.
The Thevenin resistance on the pin is measured at start-up to set the OCP level.
OC/DT
I
Switching frequency setting pin. Connect a resistor from RT pin to GND to set the converter
switching frequency. The RT pin can be left open to operate the converter at the default 1.2-MHz
switching frequency.
RT
5
–
SW
7
1
–
I
The switch node of the integrated half-bridge. Connect this pin directly to the transformer.
External clock input for frequency synchronization. The internal MOSFETs are switched
synchronized with the rising edge of the SYNC signal, with half of the SYNC pin signal frequency.
SYNC
The input for power and control of UCC25800-Q1. A good high-frequency by-pass capacitor
between VCC and GND is needed to ensure high-efficiency, low-EMI design. Use the bypass
capacitor layout to minimize the VCC-GND-bypass capacitor loop to reduce the stresses on
internal power devices. Referring to Section 10 for layout guidelines.
VCC
8
3
I
Internal regulated reference. Put a decoupling capacitor right across VREG pin and GND with
shortest distance. The VREG pin can also be used as an external supply.
VREG
O
–
Connect this pad to GND pin to provide thermal management for the device. Thermal vias are
recommended if the design uses multilayer PCB.
Thermal Pad
(1) I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
MAX
40
UNIT
V
VCC
VREG
RT
5.5
V
5.5
V
DIS/FLT
SYNC
OC/DT
Pin voltage
5.5
V
5.5
V
5.5
V
VCC + 1
7
V
Current transient (100ns)
SW
–7
A
Lower of
(VCC+5V) or
41V
higher of -5V or
(VCC-41V)
Voltage transient (50ns)
V
IQrms
TJ
MOSFET RMS current
Junction temperature
Ambient temperature
Storage temperature
600
150
125
150
mA
°C
℃
–40
-40
-65
TAMB
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
V
V(ESD) Electrostatic discharge
Corner pins (SYNC, OC/DT, RT,
and VCC)
Charged device model (CDM), per
AEC Q100-011
CDM ESD classification level C4B
±750
±500
V
V
Other pins
(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
9
NOM
MAX
34
1
UNIT
V
VCC
Supply voltage
VREG
CVREG
RRT
VREG current
0
mA
µF
kΩ
pF
V
VREG capacitor
0.1
10
1
Switching frequency set pin resistor
Capacitor on RT
CRT
1000
VREG
3.9
DIS/FLT
OC/DT
ROC/DT
COC/DT
SYNC
Disable pin
0
1
OCP/Dead Time setting pin
Thevenin resistance
V
2.5
22.7
kΩ
pF
V
Capacitor on OC/DT
External sync input voltage
Minimum SYNC pulse width, high
Minimum SYNC pulse width, low
1000
VREG
0
150
150
ns
ns
tSYNCmin
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over operating free-air temperature range (unless otherwise noted)
MIN
–0.6
100
NOM
MAX
VCC + 0.6
1200
UNIT
V
SW
Half bridge output pin
fSW
Switching frequency range
kHz
mA
A
IQRMS
IQPeak
Internal MOSFET RMS current rating
Internal MOSFET peak current rating, steady state
500
1
6.4 Thermal Information
UCC25800-Q1
THERMAL METRIC(1)
DGN (HVSSOP)
UNIT
8 PINS
47.9
59.1
18.4
1.6
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
18.4
5.6
RΘJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Unless otherwise stated: VVCC = 15 V, RRT = open, CVREG = 470 nF, and -40 °C <TJ =TA < 125 °C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
UVLOR
VCC turn on threshold
VCC turn off threshold
VCC rising
VCC falling
8
8.6
8
9
V
V
UVLOF
7.5
8.5
VCC overvoltage shutdown
threshold
OVSD
VCC rising
VCC falling
35
37
39
V
OVRS
VCC overvoltage reset
34
36
38
2
V
OVBLNK
Overvoltage blanking time
VVCC = 40 V
0.75
1.3
µs
SUPPLY CURRENT
IVCCUVLO
VCC current during UVLO
VVCC = 7.5 V
200
14
500
20
µA
mA
µA
Input current, not including
FET current (3)
fSW = 1.2 MHz, DIS/FLT = 1, SW open,
IVREG = 0 mA, VCC = 12 V
IVCCRUN
IVCCDIS
Supply current when disabled No switching, DIS/FLT = 0, IVREG = 0 mA
660
800
VREG OUTPUT
VREG
Internal regulated reference
Line Regulation
IVREG = 0 mA, DIS/FLT = 0
IVREG = 0 mA, 9 V ≤ VVCC ≤ 34 V
0 mA ≤ IVREG ≤ 1 mA
VREG rising
4.75
5
5.25
10
V
mV
mV
V
VREGLINE
VREGLOAD
VREGOK
Load Regulation
-100
4.05
3.6
Threshold for VREG GOOD
VREG fault threshold
4.5
4
4.95
4.4
VREGLOW
MOSFETs
VREG falling
V
PMOS ISW = -500 mA
NMOS ISW = +500 mA
0.45
0.3
0.75
0.5
Ω
Ω
RDSON
On Resistance
OSCILLATOR
VRT = 0.25 V
94
0.94
100
1
106
1.06
kHz
MHz
MHz
fSW
SW switching frequency
VRT = 2.5 V
Default switching frequency, RT open
1.128
1.2
1.272
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Unless otherwise stated: VVCC = 15 V, RRT = open, CVREG = 470 nF, and -40 °C <TJ =TA < 125 °C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
%
fSWtol
Tolerance
10 kΩ ≤ RRT ≤ 100 kΩ
94
106
51
Duty
Duty cycle
RT open
49
50
%
RTSHORT
Short circuit fault theshold
130
150
170
mV
Open-circuit default fOSC
threshold
RTOPEN
2.9
3
3.1
V
SYNC
SYNCRISNG
SYNCFALLING
SYNC rising threshold
SYNC falling threshold
VSYNC rising
VSYNC falling
2.0
2.2
1.7
2.4
V
V
1.53
1.87
ADAPTIVE DEAD-TIME
High-side dead-time detection
threshold with respect to VCC
DT_HSTH
SW rising
SW falling
-1.2
0.8
-1
1
-0.8
1.2
45
V
V
Low-side dead-time detection
threshold
DT_LSTH
From SW crossing DT_HSTH to HS
turning on
DT_HSDELAY
DT_LSDELAY
High-side turn on delay
Low-side turn on delay
20
20
ns
ns
From SW crossing DT_LSTH to LS turning
on
45
PROGRAMMABLE MAXIMUM DEAD-TIME
OC/DTSHORT
OC/DTOPEN
short threshold for OC/DT pin
open threshold for OC/DT pin
450
4.3
45
500
4.5
50
550
4.7
55
mV
V
VOC/DT = 3.9 V
VOC/DT = 1.9 V
ns
ns
Programmable maximum
dead-time
DTMAX
135
150
165
OVER-CURRENT PROTECTION
First level maximum OCP
setting threshold
IOCP1max
Low side only
0.9
1.9
1
2.1
5
1.1
2.3
A
ms
A
Peak current exceeds threshold time out
to trigger OCP1 fault
OCP1TO
IOCP2max
OCP1 time out
Second level maximum OCP
threshold
Low side and high side
4.25
80
5.75
120
Continuous over-current to trigger OCP2
fault, low side and high side
OCP2FILTER
OCP2 filter time
100
ns
OVER-TEMPERATURE PROTECTION
(1)
TSD
Thermal shutdown threshold
Hysteresis
TJ = TA
160
20
°C
°C
(1)
THYST
TJ = TA
ENABLE_DISABLE FUNCTION
ENTH
Enable threshold
DIS/FLT rising
DIS/FLT falling
2
2.2
1.7
2.4
V
V
DISTH
Disable threshold
1.53
1.87
Internal pull down disable
current
Ipd_DIS
VDIS/FLT = 5 V
650
750
100
850
μA
ms
RESTARTDEL
Restart delay after fault (2)
(1) Specified by design. No production tested.
(2) Specified by bench characterization. No production tested.
(3) This current includes the SW pin parasitic capaticor charge and discharge current. When operating with LLC, soft switching removes
the capacitor charge and discharge current. Actual current is smaller.
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6.6 Typical Characteristics
Figure 6-2. OVP thresholds vs junction
temperature
Figure 6-1. UVLO thresholds vs junction
temperature
IC is set in test mode. The oscillator is enabled but the internal
gate driver and power stage are disabled. TJ = 25 oC
IC is set in test mode. The oscillator is enabled but the internal
gate driver and power stage are disabled. VVCC = 15 V
Figure 6-4. VCC current vs switching frequency
and VCC voltage (Test mode, driver disabled)
Figure 6-3. VCC current vs junction temperature
and switching frequency (Test mode, driver
disabled)
TJ = 25 oC
VVCC = 15 V
Figure 6-6. VCC current vs switching frequency
and VCC voltage
Figure 6-5. VCC current vs junction temperature
and switching frequency
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1
Low-side NMOS
High-side PMOS
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
125
150
Junction temperature (oC)
VVCC = 15 V
Figure 6-7. RDSON vs junction temperature
Figure 6-8. Switching frequency vs RT pin voltage
and temperature
5.5
5.4
5.3
5.2
5.1
5
4.9
4.8
4.7
High-side
Low-side
4.6
4.5
-50
-25
0
25
50
75
100
125
150
VVCC = 15 V
Junction temperature TJ (oC)
Figure 6-10. Maximum OCP2 thresholds vs
junction temperature
Figure 6-9. Programmed maximum dead-time vs
junction temperature
1.1
1.05
1
0.95
0.9
-50
-25
0
25
50
75
100
125
150
Junction temperature TJ (oC)
Figure 6-11. Maximum OCP1 threshold vs junction temperature
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7 Detailed Description
7.1 Overview
Modern high-voltage, high-power-inverter, and motor-drive applications require floating bias supply voltages to
power at least the high-side totem-pole switches, where source (and gate) voltages move up and down with
the inverter switch-node. The traditional way of providing small amounts of isolated bias power has been to
use a flyback converter. Often a single flyback converter with multiple outputs can generate the required rails
for all the switches. However, issues with reliability, redundancy, shock and vibration testing, noise immunity
and particularly EMI and common mode current have led to a trend away from the flyback topology and
centralized architecture toward distributed open-loop approaches. The open-loop approaches such as 50%
duty cycle push-pull, open-loop half bridge or full bridge without an output inductor are deployed while the
flyback converter or flybuck (an isolated buck converter) continue to be used by some designs to provide
regulated outputs despite the larger common-mode capacitance (transformer primary-side to secondary-side
parasitic capacitance). With the adoption of SiC and GaN devices, the inverter power stage switches at a
much higher dv/dt. This behavior causes much larger common-mode current injection through the isolated bias
transformers and drives the needs for a bias supply design with minimum parasitic capacitance. The need to
further reduce the primary-to-secondary capacitance without suffering performance degradation has led some
designs to deploy resonant topologies such as the LLC. As the leakage inductance in an LLC is a component of
the power train, the topology can enable a higher leakage inductance transformer to be used with an associated
reduction in the parasitic primary-secondary capacitance. The UCC25800-Q1 transformer driver is a small,
simple controller enabling this topology to be deployed with low component count, integrated protection features,
high switching frequency, high parameter tolerance and robust operation. An 8-pin DGN package with thermal
pad is used to provide up to 6-W power handling capability with 24-V input.
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7.2 Functional Block Diagram
VIN
VCC
8
VREG
5 V
VREF
3
VOCP1
VOCP2
1V
OCP
Setting
Ra
Td_auto_H
GD_High
+
Measure OCP Setpoint
Max_DT
Max
Dead Time
QH
4
Level
Shift
OC/DT
Td_auto_H
7
SW
Rb
VSW
VRT
+
+
Q
Q
T
GND
QL
SYNC
Qualify
1
SYNC
Soft
Start
+
Td_auto_L
GD_Low
Max_DT
Td_auto_L
SS_DONE
1V
VREF
Disable
PIN FAULT
VSW
VOCP1
+
OCP
OVP
TSD
2.1-ms
persist
25 µA
2
DIS/FLT
VVCC -VOCP2_H
Fault Code
output
+
+
RT
VRT
5
GD_High
GD_Low
VSW
VOCP2_L
GND
100-ns
persist
RRT
6
7.3 Feature Description
UCC25800-Q1 is an 8-pin open-loop half-bridge transformer driver that integrates all the control and power
devices. It converts a fixed input voltage to an isolated voltage source through an isolation transformer. The
relationship between the output voltage and input voltage is fixed, which is determined by the transformer turns-
ratio and the rectification method. The open-loop control, together with the LLC resonant converter operation,
makes the solution more robust, smaller size, higher efficiency, as well as lower EMI and common mode noise.
The transformer driver requires a minimum of external components while providing design flexibility and robust
protection features. The 1.2-MHz maximum switching frequency reduces the transformer size and cost, making
it easier to pass the shock and vibration test in the automotive applications. The fault code output allows the
designer to identify the protection mode, during the development stage, as well as during normal operation. This
makes the development process much easier. It also enables the system controller to make intelligent decisions
when bias supply faults happen.
7.3.1 Power Management
The VCC pin powers the UCC25800-Q1 transformer driver. When the VCC pin voltage is below the UVLO rising
threshold (UVLOR), the VREG pin 5-V regulator is disabled (VREG = 0 V). After the VCC pin voltage exceeds
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UVLOR, the 5-V regulator is enabled and VREG pin rises, while the DIS/FLT pin is internally pulled low through
an internal 750-μA current source, (DIS/FLT = 0 V). When the VREG exceeds 4.5 V (VREGOK), the DIS/FLT
pin is released. If the DIS/FLT pin is not pulled low externally, it rises to VREG pin voltage level via an internal
100-kΩ pull up resistor. When DIS/FLT pin voltage exceeds the rising enable threshold (ENTH), the internal
regulators and references are turned on and the transformer driver reads the Thevenin resistance on the OC/DT
pin to set the overcurrent protection (OCP) thresholds. After this process completes, the faults are checked and
if they are all cleared, the oscillator is enabled and the power stage starts switching. The time to complete this
process is approximately 500 μs.
If a fault is detected, the transformer driver activates the internal pull-down current source on the DIS/FLT pin,
the power stage stops switching, and the device outputs the fault code.
The rise time of the DIS/FLT pin depends on the external loading on the pin. An external pull-up can be added to
the pin if there is concern over noise immunity. The values are specified in Section 7.3.6.
When the VCC pin voltage is above the UVLOR threshold and DIS/FLT pin is pulled low externally the
transformer driver remains disabled with IVCCDIS = 660 µA.
If after a completed power-up sequence, VCC falls below the UVLO falling threshold (UVLOF), the power stage
switching is immediately stopped. The VREG pin voltage regulator is disabled making the VREG pin voltage fall.
The VCC pin current is a combination of the IC bias current and the power stage current. It is important to have
a low ESL bypass capacitor to minimize the current loop among this capacitor and VCC, GND pins. Refer to
Section 10 for details.
7.3.2 Oscillator
The internal oscillator of the UCC25800-Q1 transformer driver sets the switching frequency of the power stage.
It operates at a 50% duty cycle. The voltage on the RT pin sets the oscilator frequency. A 25-µA current source
flows out of the pin so that the switching frequency can be set by connecting a resistor to GND. Figure 7-1
shows the internal oscillator.
UCC25800-Q1
25µA
Voltage clamp
VRT
3 V
IRT=1.5ꢀS×VRT
RT
+
œ
To logic
œ
RRT
RT_short
+
2.5 V
150 mV
0.74 pF
1 V
1.5 ms
Disable
Figure 7-1. Equivalent circuit for internal oscillator
Use Equation 1 to calculate the RT pin resitance for a required switching frequency.
Hz
f
= R × 10
RT
Ω
(1)
SW
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If the RT pin is left open, or an RT pin resistor value results in an RT pin voltage at RTOPEN threshold or above,
the power stage operates with the default switching frequency of 1.2 MHz. If the RT pin voltage is below 150 mV,
the transformer driver considers the RT pin shorted to ground and declares a fault. The programmable voltage
range on the RT pin is 250 mV to 2.5 V. The relationship between the power stage switching frequency and the
RT-pin voltage is shown in Figure 7-2.
1600
1400
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2
2.5
3
RT pin voltage (V)
3.5
4
4.5
5
Figure 7-2. Relationship between switching frequency and RT-pin voltage
To avoid the excessive current stress during the start-up process, the transformer driver integrates a soft-start
function. The oscillator starts by ramping the oscillator reference from 1 V to 2.5 V, which results in the switching
frequency reducing from 2.5 times of the set frequency to the set frequency. Because the current source in
the oscillator remains the same while the reference changes, the switching cycle decays linearly. The soft-start
time is fixed internally at 1.5 ms. This long soft-start time limits the inrush current when charging large output
capacitors. The soft-start is enabled during the start-up and fault recovery process. Figure 7-3 shows the
switching frequency variation during the start-up time.
1.5 ms
2.5 V
Oscillator reference
1 V
0 V
2.5fSW
Switch frequency
fSW
0
Figure 7-3. Switching frequency during soft start time
During the soft-start sequence, the first pulse from the oscillator is a half of the second pulse width (25% of the
period at the starting switching frequency) and followed immediately by 50% duty cycle pulses. This process
ensures the LLC transformer magnetizing current is symmetrical from the first pulse to minimize ringing in the
system. The high-side switch is always turned on at the first pulse to avoid uncertainty of the circuit operation.
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High-side switch control logic
Low-side switch control logic
First pulse
Second pulse
½
Pulse
Full
Pulse
SW Pin Voltage
UCC25800-Q1 is off, SW pin voltage is
determined by external circuit
2.5fSW
Figure 7-4. SW pin voltage and control logic at the first switching cycle (dead-time is not shown)
7.3.3 External Synchronization
An external signal connected to the SYNC pin synchronizes the switching frequency of the UCC25800-Q1
transformer driver.
In the external synchronization mode, the switching frequency of the SW pin is half of the SYNC pin signal
frequency. Given that, to ensure the output voltage remains within the normal operation range, the half of
the frequency of external synchronization signal needs to be between 15% and 30% (nominal) above the
programmed switching frequency with a tolerance of 5% or less, as described in Equation 2. A minimum high
and low pulse width of 150 ns is required. The SYNC pin logic is compatible with TTL and CMOS levels for the
design simplicity. It is recommended to use 50% duty cycle signal.
1
2
1.15 × f
<
× f
< 1.3 × f
SYNC SW
(2)
SW
where
•
•
fSW is the RT pin programmed SW-pin switching frequency
fSYNC is the SYNC pin signal frequency
The transformer driver ignores the external synchronization signal during the 1.5-ms soft-start time. The
switching frequency during the soft-start time is based on the RT pin voltage as described in Section 7.3.2.
After the soft-start period ends, if an external synchronization signal is present and its frequency and pulse width
are within the specified range, the switch node is driven by the SYNC pin signal. The transformer driver also
integrates a hand-off algorithm so that when the switching frequency transitions from internal oscillator to the
external synchronization signal, the disturbance is minimal and transformer saturation is avoided.
The hand-off algorithm first confirms that the external synchronization signal is within the range. If the frequency
is not within the acceptable range, the hand-off doesn't happen. If the frequency is within the acceptable range,
the hand-off algorithm begins to search for the optimal transition point and locks the switching frequency with
the external SYNC signal. After the frequency is locked, the hand-off algorithm stops monitoring the SYNC pin
frequency. It is important to ensure external synchronization source has a stable frequency. There is an internal
watchdog timer to prevent the external frequency from falling below the set frequency (the watchdog time does
not monitor if the SYNC pin frequency goes above the range). If the SYNC pin frequency drops below the
set frequency, the transformer driver loses synchronization and the converter operates with the set frequency
determined by RT pin voltage.
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The Figure 7-5 shows an oscilloscope screen capture for the controller transition from internal oscillator to the
external synchronization signal. The smooth transition can be observed and the SW pin current sees minimal
disturbance.
Hand off
532 kHz
605 kHz
SW Pin voltage
SYNC pin
voltage
SW pin current
Figure 7-5. Transition from internal oscillator to external synchronization
The internal MOSFET gate drives are toggled on each SYNC pin voltage rising edge, so the switch-node
frequency is equal to half of the SYNC pin signal frequency, as shown in Figure 7-6. Due to the internal filter
delays, the SW pin switching edge is not aligned with the SYNC pin switching edge. There is a delay of
approximately 150 ns.
SW
~ 150 ns
~ 150 ns
SYNC
Time
Figure 7-6. External SYNC signal drives switching frequency
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7.3.4 Dead-Time
A dead-time is needed between the turn off of one switch and the turn on of the other switch to avoid shoot
through. This also allows the switch-node voltage to transition to the opposite rail voltage, which reduces
switching loss and EMI noise.
7.3.4.1 Adaptive Dead-time
The UCC25800-Q1 transformer driver automatically detects the dead-time after the switch-node voltage slews
to within 1 V of the opposite rail. This slewing of the node is driven by the current flowing through the SW
pin into the resonant tank at the end of the each MOSFET on-time. There must be sufficient current flowing
through the SW pin at the end of the on-time to drive the SW pin voltage to the opposite rail. the voltage on the
OC/DT pin programs the maximum dead-time. Even if the SW pin voltage crossing the threshold is not detected
within the maximum programmed dead-time, the internal MOSFET switches on when the maximum programmed
dead-time expires. Figure 7-7 and Figure 7-8 demonstrate the two adaptive dead-time operation conditions.
VCC
1 V
VCC
1 V
VCC
VCC
VSW
V
SW
1 V
0 V
1 V
0 V
GD_Low
GD_High
GD_Low
GD_High
Max_TD
Max_TD
Time
Time
Figure 7-7. Adaptive dead-time operation without
triggering maximum dead-time
Figure 7-8. Adaptive dead-time operation with
maximum dead-time
7.3.4.2 Maximum Programmable Dead-time
During operation, the voltage on the OC/DT pin sets a maximum duration of the dead-time. If the adaptive
dead-time has not triggered the turn-on of the internal MOSFET within this time, it switches on when the
maximum dead-time expires. The relationship between the OC/DT pin voltage and this maximum programmable
dead-time is shown in Figure 7-9 and given by Equation 3. The UCC25800-Q1 transformer driver also limits the
maximum dead-time to be 1/8 of the switching cycle. Therefore, the programmed maximum dead-time is the
lower value of these two.
150 ns × 1 V
DT
=
V
(3)
MAX
− 0.9 V
OC/CT
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Figure 7-9. Maximum dead time vs. OC/DT pin voltage
When the OC/DT pin voltage falls below 0.5 V, the transformer driver triggers the pin-short protection and it
shuts down. When the OC/DT pin voltage is between 0.5 V to 3.95 V, the maximum dead-time is set by Equation
3 with a clamped maximum value of 1.35 μs and a clamped minimum value of 50 ns. When the OC/DT pin
voltage is between 3.95 V and 4.5 V, it triggers the DT-out-of-range fault and the transformer driver shuts down.
When the OC/DT pin voltage is above 4.5 V, the transformer driver shuts down due to the OC/DT open pin fault
protection.
7.3.5 Protections
UCC25800-Q1 transformer driver provides a full set of protection functions to improve the system level
reliability, meeting automotive design requirements. The protection functions include programmable two-level
over current protection (OCP), input undervoltage protection (UVLO), input over-voltage protection (OVP), and
over-temperature protection (TSD). This design considers possible pin fault conditions such as pin open and pin
short.. Extra protection mechanisms are also integrated inside the design.
7.3.5.1 Overcurrent Protection
The UCC25800-Q1 transformer driver has two levels of overcurrent protection (OCP).
•
The first level (OCP1) triggers if the current through the low-side MOSFET exceeds programmed threshold
IOCP during its on-time in each switching cycle for 2.1 ms. Refer to OCP Threshold Setting for OCP1
threshold programming details.
– OCP1 detection is based on only the low-side MOSFET current, when the SW pin current flows into the
SW pin
•
The second level (OCP2) triggers if the current in either the high-side or low-side MOSFET exceeds 5 × IOCP
for 100 ns.
– The OCP2 threshold is set significantly above OCP1 threshold to allow the unit to cope with heavy
load surges for a short duration, or during the start-up to charge the large output capacitor. If OCP2 is
exceeded, it indicates that there is a serious fault in the system. OCP2 tracks OCP1 so that events like
output overload can still trip OCP2, even if the current limit is set well below the maximum current limit of
the transformer driver.
•
•
•
During soft-start
– The OCP1 is disabled
– The OCP2 threshold is fixed at its maximum value of 5 A
After soft-start
– OCP1 is enabled, with the threshold IOCP equal to the programmed value
– OCP2 threshold becomes 5 times of the programmed IOCP level.
The OCP1 overcurrent timer is implemented as an up-down counter to ensure that the repetitive short
over-current events as well as a sustained 2.1-ms over current trigger the OCP.
– OCP1 overcurrent timer counts up if the SW current crosses IOCP for longer than 100 ns in each switching
cycle
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– OCP1 overcurrent timer counts down if the SW current does not cross IOCP for longer than 100 ns in the
entire switching cycle
– The internal counter for OCP1 overcurrent timer counts up in 2.1 ms from 0 to the trip threshold and
counts down in 180 ms from the trip threshold down to 0.
•
OCP2 detection has an analog filter which filters out pulses of less than 100 ns.
The transformer driver imposes a restart time of 100 ms before restarting from overcurrent protection to maintain
the RMS current in the transformer driver below its limit. The OCP behaviors are illustrated in Figure 7-10 and
Figure 7-11.
IOCP
IQL
OCP1 counter
threshold
2.1-ms rise
slope
OCP1 counter
180-ms fall
slope
0
OCP1
Soft start
2.1 ms
100 ms
Figure 7-10. OCP1 protection and recovery behavior
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5IOCP
ISW
F 5IOCP
OCP2
Soft start
100 ms
Figure 7-11. OCP2 protection and recovery behavior
7.3.5.1.1 OCP Threshold Setting
The UCC25800-Q1 transformer driver can support 6-W output power with 24-V input. For designs with lower
power levels, the overcurrent protection (OCP) threshold can be adjusted accordingly to limit the maximum
output power to improve the system reliability.
The OCP threshold setting shares the same pin as the maximum dead-time programming through OC/DT pin.
During the transformer driver start-up sequence (after its VREG pin settles down to its final value) an internal
50-µA current source flowing out of OC/DT pin is turned on and off. The voltage on the OC/DT pin is measured
at the current source on and off conditions. The measured voltage difference is used to set the OCP threshold.
After the OCP setting is determined, the current source is turned off, so that the voltage on the OC/DT pin can
be used for the maximum dead-time setting.
VREG
VREG
50 µA
50 µA
Ra
Rb
Ra
Rb
OC/DT
GND
OC/DT
GND
V2(A)
V1
Figure 7-12. Current Source On
Figure 7-13. Current Source Off
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According to the Thevenin theorem, the measured voltage difference is the current source multiplied by the
Thevenin resistance on the voltage divider on OC/DT pin. The OCP settings using different Thevenin resistance
are summarized in Table 7-1. The Thevenin resistance can be calculated using Equation 5.
Ra × Rb
Ra + Rb
Rth =
(5)
Table 7-1. OCP Settings
OCP1 _1
OCP1_2
OCP1_3
OCP1_4
OCP1_5
OCP1_6
22.25 kΩ ~ 23.15
kΩ
Rth
16.4 kΩ ~ 17 kΩ 11.7 kΩ ~ 12.1 kΩ 7.95 kΩ ~ 8.25 kΩ 4.9 kΩ ~ 5.1 kΩ 2.45 kΩ ~ 2.55 kΩ
1/3 IOCP1max 1/2 IOCP1max 2/3 IOCP1max 5/6 IOCP1max IOCP1max
5 A 5 A 5 A 5 A 5 A
OCP1 threshold
(IOCP
1/6 IOCP1max
5 A
)
OCP2 threshold
during soft-start
OCP2 threshold
after soft-start
5/6 IOCP1max
5/3 IOCP1max
5/2 IOCP1max
10/3 IOCP1max
25/6 IOCP1max
5 IOCP1max
To ensure accurate reading of the Thevenin resistance, the time constant of Rth and any capacitance connected
to the OC/DT pin should not be greater than 20 µs. For this reason, the maximum recommended capacitance on
the pin is 1 nF. It is not required to add capacitance to the pin.
The OC/DT pin voltage during start-up is illustrated in Figure 7-14.
(B)
ꢀV
(A)
~ 150 µs
V
0
Time
Figure 7-14. OC/DT pin voltage during start-up
Rb
A.
B.
V = VREG ×
Ra + Rb
(6)
(7)
∆ V = 50 µA × Rth
7.3.5.1.2 Output Power Capability
Figure 7-15 shows the output power capability of the UCC25800-Q1 transformer driver at different input voltages
and switching frequencies with its highest OCP set-point (IOCP = IOCP1max = 1 A), based on an input-output
efficiency of 90%. There are two limiting factors on the power handling capability of the transformer driver; the
OCP1 threshold and the thermal stress.
OCP1 serves as an over-power limit rather than over current protection since it has a 2.1-ms timer. Given its
maximum value is 1 A and considering the sinusoidal current shaped, transformer driver limits its maximum
output power proportionally to the input voltage. In Figure 7-15, the 100-kHz line is approximately the OCP1 limit.
The thermal limitation is to prevent the junction temperature of the transformer driver from becoming too
high. Assuming its loss is only the IC bias consumption and the MOSFET conduction loss, at 125°C ambient
temperature and 90% efficiency, the maximum output power creates the loss to make the junction temperature
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reach 150°C. Figure 7-15 shows that with higher the switching frequency, the IC power consumption increases
and the maximum power capability decreases.
The power handling capability can be increased by increasing the input voltage or lowering the switching
frequency, but it cannot exceed the OCP1 limit.
10
8
6
100 kHz
200 kHz
500 kHz
4
750 kHz
1 MHz
1.2 MHz
29 34
2
9
14
19 24
Input Voltage (V)
Figure 7-15. Power rating curves
7.3.5.2 Input Overvoltage Protection (OVP)
Due to the lack of feedback, UCC25800-Q1 transformer driver includes input overvoltage protection to prevent
the output voltage from becoming too high, in case its input voltage becomes too high. If the VCC pin
voltage exceeds the overvoltage set-point of OVSD for overvoltage blanking time (OVBLNK, 1.3 µs typical),
the input overvoltage protection is triggered. When the input overvoltage protection is triggered, the fault
mode is activated, stops the switching, and discharges the DIS/FLT pin and disables the transformer driver.
Before restarting from an OVP fault, the input voltage must be below the OVP recovery threshold OVRS. The
transformer driver attempts to restart after 100 ms as described in Section 7.4.5.
The overvoltage protection threshold is a fixed value and cannot be programmed.
7.3.5.3 Over-Temperature Protection (TSD)
Over-temperature protection is required, primarily to stop the internal MOSFETs from failing in either
high ambient temperature operation conditions or due to self-heating from high switching current. An over-
temperature condition occurs when the junction temperature goes above the TSD threshold of 160°C (typical).
In this case, the fault mode is activated, the switching stops, discharging the DIS/FLT pin and disabling the
UCC25800-Q1 transformer driver. Before restarting from a TSD fault, the junction temperature must be below
the overtemperature protection recover threshold (TSD-THYST). Over-temperature protection parameters are
specified by design.
7.3.5.4 Pin-Fault Protections
Table 7-2 below shows the UCC25800-Q1 transformer driver response to open and short circuits on the pins.
For example, the SYNC function operates on the rising edge of the SYNC pin. Hence if the pin is open or short
the only impact is the loss of synchronization functionality. The transformer driver continues to operate as normal
at the switching frequency programmed by the RT pin. .
Table 7-2. Pin Open and Short Response
PIN
SYNC
DIS/FLT
VREG
OC/DT
RT
OPEN
Normal operation with the programmed frequency
Normal operation
SHORT TO GND
Normal operation with the programmed frequency
OFF
OFF (VREG open protection)
Fault (OC/DT open protection)
fSW = 1.2 MHz
OFF
Fault (OC/DT short protection)
Fault (RT short protection)
-
GND
Unknown
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Table 7-2. Pin Open and Short Response (continued)
PIN
SW
OPEN
VOUT = 0
OFF
SHORT TO GND
Fault (OCP) / ✖
OFF
VCC
Table 7-3. Pin-to-Pin Shorts Responses
1 2 3
SYNC
–
DIS/FLT
VREG
OC/DT
VCC
SW
GND
RT
SYNC
DIS/FLT
VREG
– / OFF
–
Always
enabled
No SYNC
–
– / OC/DT
Fault
Fault (OC/
DT_OPEN)
OC/DT
Indeterminate
-
VCC
SW
✖
✖
✖
✖
✖
✖
–
OCP Fault / ✖
Fault / ✖
Fault / ✖
-
Fault (OC/
DT_SHORT)
Fault (OCP)/
GND
RT
No SYNC
OFF
OFF
IC not biased
-
✖
Fault
(RT_OPEN)
Fault
(RT_SHORT)
Indeterminate Indeterminate
Indeterminate
✖
✖
–
1. ✖ indicates that the transformer driver will or may become damaged.
2. – indicates no effect on the circuit operation.
3. Indeterminate indicates the IC behavior is unpredictable
7.3.5.5 VREG Pin Protection
The VREG pin is an internal linear regulator output and the bias pin for most of the internal circuits. It is
important to ensure a good regulated voltage on VREG pin. A low ESL decoupling capacitor is recommended
between VREG to GND. The layout should follow the Layout Guidelines.
VREG pin is equipped with two sets of protection functions to prevent the pin from being left open or over loaded
from external circuit.
When VREG pin is left open, since there is no decoupling capacitor, the internal linear regulator becomes
unstable. The UCC25800-Q1 transformer driver detects this condition, stops the operation, shuts down the
internal linear regulator, and enters the latch-off mode. VCC must be recycled to clear this protection.
To prevent VREG pin from being over-loaded, the VREG pin has its own over-current protection. During start-up,
when VREG pin voltage is below 1 V, the VREG pin current is limited to 15-mA, to protect the IC from short
or over-load conditions. When the VREG pin voltage rises above 1 V, the VREG pin current limit increases to
40 mA for a fast start-up. When the voltage crosses the VREGOK value, the VREG pin current limit returns to
15 mA. Because the VREG pin provides current for both internal circuit and external circuit, it is recommended
to maintain the VREF pin external load to a value less than 1 mA. When the external VREG-pin current is
between 1 mA and 15 mA, excessive VREG pin current can cause the VREG pin voltage to drop. During normal
operation, if the VREG pin is over loaded and its voltage drops below the VREGlow threshold, the transformer
driver shuts down the linear regulator and enters latch-off mode. VCC must be recycled to clear this protection.
7.3.6 DIS/FLT Pin operation
The DIS/FLT pin is an input/output pin. It can be
•
•
Externally driven to enable or disable the transformer driver
Read as a status flag telling whether the transformer driver is in fault mode or not and specifically what fault it
is
•
Left floating to enable the transformer driver by default
Internally the pin is tied high through a 100-kΩ pullup resistor from VREG. This pullup resistor activates only
after the VREG pin is high. If the UCC25800-Q1 transformer driver enters the fault mode, the DIS/FLT pin is
pulled low internally via a 750-µA current source. When the pin is low, switching is inhibited.
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The DIS/FLT internal pulldown current source is activated during the power-up sequence once the VCC voltage
exceeds the UVLO rising threshold. After the VREG voltage has risen above the VREGOK threshold, the
pulldown current source is released and the DIS/FLT pin rises (unless it is externally pulled down). When
the DIS/FLT pin voltage exceeds the ENTH threshold, the transformer driver is enabled. When DIS/FLT pin
falls below the DISTH the transformer driver is disabled. When the transformer driver is disabled its power
consumption is reduced to IVCCDIS
.
If there is concern about noise coupling to the DIS/FLT pin it can be pulled up with an external resistor to an
external rail or to VREG. In order to read the pin as a status flag, the external resistor value must be high enough
that the 750-µA current source can pull the pin below the threshold level of the device reading the pin. It is
recommended that the value for an external pullup resistor to 5 V is 10 kΩ and the value for an external pullup
resistor to 3.3 V is 4.7 kΩ in order for the pin to be read as a fault output.
3V3 (external)
5V (external)
VREG (Internal)
100 k
VREG (Internal)
100 k
4.7 k
10 k
DIS/FLT
DIS/FLT
750 µA
750 µA
Figure 7-16. External Pullup for 3.3-V Supply
Figure 7-17. External Pullup for 5-V Supply
If the DIS/FLT pin functionality is not required, it can be left floating or tied to VREG to allow the transformer
driver to operate normally.
7.3.6.1 FAULT Codes
When the UCC25800-Q1 transformer driver enters fault mode, it outputs a train of pulses to indicate which faults
have occurred through the DIS/FLT pin. The pulse train consists of a number 50% duty cycle pulses at 50 kHz,
(that is, 10-μs wide pulses), where the number of pulses indicates the fault listed in Table 7-4. The pulse train
is created through controlling the internal 750-μA pull-down current source, together with the 100-kΩ pull-up
resistor.
Table 7-4. Fault codes
NO. OF
PULSES
FAULT
1
2
3
4
5
6
7
8
9
OCP1
OCP2
Input overvoltage protection
Over temperature protection
DT out of range
OC/DT open
OC/DT short
RT short
OTP (one-time-programmable bit ) error
The pulse train starts 10 µs after the fault has been asserted. Transmission of the fault code begins with a
100-µs wide high pulse. If more than one fault is detected, the codes are transmitted successively based on the
order in Table 7-4, separated by a 100-μs wide high pulse, as shown below in Figure 7-18.
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10µs
10µs
DIS/FLT
100µs
10µs
(a) Single fault code, OCP2 example
Fault event
10µs
10µs
DIS/FLT
100µs
100µs
10µs
10µs
(b) Multiple fault codes, OCP2 and input over-voltage example
Figure 7-18. Fault code diagram
7.4 Device Functional Modes
Depending on the operating condition, the UCC25800-Q1 transformer driver can operate in different modes,
including UVLO, soft-start, normal operation, disabled and the fault modes.
7.4.1 UVLO Mode
When the input voltage on VCC is less than the transformer driver UVLO threshold, the transformer driver is
disabled. There is no switching on the SW pin and VREG is off.
7.4.2 Soft-start Mode
After the VCC voltage is above the UVLO threshold, all the faults are cleared, and DIS/FLT is released,
the converter operates in the soft-start mode. During the soft-start period, the switching frequency gradually
decreases to reduce the current stress. The soft-start period duration is 1.5 ms. The UCC25800-Q1 transformer
driver always operates in soft-start mode during startup or after fault recovery. Refer to Section 7.3.2 for more
details of soft-start mode.
7.4.3 Normal Operation Mode
Most of the cases, the UCC25800-Q1 transformer driver operates in the normal operation mode. The switching
frequency is fixed, determined by eithert he RT pin voltage or external synchronization signal.
7.4.4 Disabled Mode
When the DIS/FLT pin is pulled low externally, the UCC25800-Q1 transformer driver enters disabled mode. In
this mode, the VREG pin is regulated while the SW pin remains off. The VCC current consumption reduces to
the disable current IVCCDIS
.
7.4.5 Fault Modes
Occasionally, different fault conditions occur and the UCC25800-Q1 transformer driver protects the system from
more severe damage by entering the following fault modes.
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Table 7-5. Fault Mode Summary
FAULT
DESCRIPTION
OCP1 occurs when the current in the internal low-side MOSFET during the low-side MOSFET on time exceeds
IOCP for 2.1 ms.
Overcurrent (OCP1)
Overcurrent (OCP2)
OCP2 occurs when the current in either MOSFET exceeds five times of the IOCP for more than 100 ns.
Over temperature protection (TSD) occurs when the junction temperature goes above TSD threshold.
Over temperature (TSD)
Input overvoltage protection occurs when VCC voltage is above the overvoltage shut-down (OVSD) threshold
for more than 1.3 μs.
Input overvoltage
OC/DT open
OC/DT short
OC/DT open protection occurs if the OC/DT pin exceeds 4.5 V after the OCP check has been completed.
OC/DT short protection occurs if the OC/DT pin falls below 500 mV.
OC/DT out-of-range protection occurs when the OC/DT pin voltage is between 3.95 V and 4.5 V during the
OCP programming check.
OC/DT out of range
RT short
RT short protection occurs when RT pin is below 150 mV.
OTP error fault occurs when, during the OTP reading at start-up, the OTP sanity check fails. In case of OTP
error fault, only OTP error fault code is transmitted while all other faults are ignored. The OTP error fault can be
cleared only with a power cycle that forces a new OTP reading.
OTP error
When any fault occurs the switching is immediately (after individual detection delays) stopped. The DIS/FLT pin
is internally pulled down. After the fault codes are transmitted, the transformer driver current consumption is
reduced to IVCCDIS. The VREG regulator remains enabled and the RT pin remains at its programmed level.
When the transformer driver enters fault mode it pulses the pull-down current on the DIS/FLT pin on and off to
output a fault code and signal which fault has been triggered as explained in Section 7.3.6.1.
After a delay time of 100 ms, the DIS/FLT pin is released and, if it is not pulled low externally. When it crosses
the ENTH, the transformer driver is enabled, the power up sequence occurs and the switching can start again.
Before starting switching, the faults are checked again. If the protection that caused the fault condition still
presents, or a new protection is triggered, the switching is not started and a new fault condition is asserted; fault
codes are transmitted again. And the transformer driver current consumption is reduced to IVCCDIS. This fault
and power-up sequence is automatically cycled until all the faults are cleared.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The isolated bias supply is required in many applications, such as the gate driver bias for the traction
inverters, on board chargers in electrical vehicles. It is also used in other sensing and control circuits in the
electrical vehicles to minimize the noise or provide safety isolation. The open-loop LLC converter based on the
UCC25800-Q1 transformer driver provides a reliable solution for these applications. It uses the open-loop control
to improve the noise immunity. The LLC topology is able to operate at a higher switching frequency with soft
switching, achieve high efficiency and low EMI, reducing the transformer size. Furthermore, the LLC topology
is able to absorb the transformer leakage inductance as part of the resonant circuit. This absorption allows
the transformer to have extremely low primary side to secondary side parasitic capacitance, which reduces the
system level common-mode noise. The LLC topology also helps to simplify the transformer construction and
reduces the transformer cost.
8.2 Typical Application
In the automotive traction inverters or on-board chargers, a regulated bus voltage is often generated from the
12-V battery and then processed by the isolated bias supplies to provide the gate driver bias power for the
inverter switches, as shown in Figure 8-1. The isolated bias supply can be used to bias the high-side drivers or
low-side drivers, to provide the isolation for function, safety, or noise immunity.
Intermediate
bus
Isolated bias supply
VOUT
+
Gate
Driver
–
VOUT
DC/DC
12-V battery
High-voltage
battery
Load
Pre-regulator
Figure 8-1. Gate driver bias supply example for automotive traction inverter
When the isolated based bias supply used in the inverter applications, especially for the high side switches, the
high dv/dt on the inverter switch-node can couple through the bias supply transformer and causes extra EMI
noise, as demonstrated in Figure 8-2.
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Intermediate
bus
Isolated bias supply
VOUT
+
Gate
Driver
–
VOUT
DC/DC
12-V battery
High-voltage
battery
Load
Pre-regulator
ICM
CPS
Figure 8-2. Noise coupling path from inverter power stage to isolated bias supply
Given the high dv/dt is caused by the inverter power stage, to minimize this noise coupling, it is desired
to minimize the transformer primary side to secondary side parasitic capacitor (inter-winding capacitor) CPS
.
Popular topologies, such as Flyback or Push-pull, require the minimum leakage inductance to improve the
efficiency, reduce the voltage and current stress, as well as minimize the noise created by the converter. In turn,
this type of transformers suffer from larger inter-winding capacitance. When they are used in the gate driver
bias supply applications, the high dv/dt from the inverter power stage could be coupled through the transformer
inter-winding capacitor to the low-voltage side. This creates a much severe EMI noise issue. Instead, the LLC
topology utilizes the transformer leakage inductance as its resonant component, allowing the converter to use
a transformer with larger leakage inductance but much smaller inter-winding capacitance. This results in less
system EMI noise challenges.
8.2.1 LLC Converter Operation Principle
Different than the traditional PWM converters, LLC converters adjust the output voltage through varying the
switching frequency. It is often called a PFM (pulse frequency modulation) converter. As shown in Figure 8-3,
the LLC converter has three resonant elements, the resonant inductor (Lr), the magnetizing inductor (Lm),
and the resonant capacitor (Cr). In the isolated bias supply design, the transformer leakage inductor, and the
magnetizing inductor can be used as part of the resonant circuit. In this case, the only external resonant
component is the resonant capacitor.
Lr
VOUT
VIN
Lm
Cr
Transformer
NP:NS
Figure 8-3. LLC Converter
At the resonant switching frequency (series resonant frequency of Lr and Cr), the impedance of the resonant
tank (Lr and Cr) is equal to zero. The input and output voltage are virtually connected together through the
transformer. Therefore, the gain of the converter is equal to the transformer turns ratio, as shown in Equation 8.
V
N
OUT
1
S
=
(8)
V
2 N
IN
P
In this equation, the ½ comes from the half-bridge architecture that the transformer primary side only sees half of
the input voltage.
UCC25800-Q1 transformer driver controls the LLC converter to operate at a fixed switching frequency very close
to the resonant frequency, to create an output voltage proportional to the input voltage, through a transformer
turns-ratio. Depending on the location of the resonant capacitor, the LLC converter can be configured as
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primary-side resonant (as shown in Figure 8-3), or secondary-side resonant (as shown in Figure 8-4). When
the resonant capacitor is moved to the secondary side, the magnetizing inductor no longer affects the converter
gain. Therefore, the converter is less sensitive to the switching frequency and resonant component tolerances.
The secondary-side resonant is more suitable for the open-loop LLC converter and it is a preferred configuration
for transformer driver.
Lr
Cr
VOUT
Lm
VIN
Transformer
NP:NS
Figure 8-4. Secondary side resonant LLC converter
Furthermore, the secondary-side full-wave rectifier can be replaced with a voltage-doubler rectifier. Together with
splitting the resonant capacitor into two, as shown in Figure 8-5, the converter configuration becomes simpler
and fewer diodes are used. In this case, the transformer primary side sees half of the input voltage and the
transformer secondary side sees half of the output voltage. The converter voltage gain becomes purely the
transformer turns-ratio, as shown in Equation 9.
V
N
N
OUT
S
=
(9)
V
IN
P
½ Cr
Lr
VOUT
Lm
VIN
½ Cr
Transformer
NP:NS
Figure 8-5. Secondary side resonant LLC converter with voltage doubler rectifier
The LLC operation waveforms are shown in Figure 8-6, when switching frequency is equal to the resonant
frequency or below the resonant frequency.
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VSW
VSW
IPK/NPS
IPK/NPS
Transformer
Primary side
current
Transformer
Primary side
current
IPK
IPK
Transformer
Secondary
side current
Transformer
Secondary
side current
½IPK
½IPK
Rectified
current
Rectified
current
(a) Switching frequency equal to resonant frequency
(b) Switching frequency below resonant frequency
Figure 8-6. LLC converter operation waveforms
8.2.2 Design Requirements
A 2-W traction inverter gate driver bias supply design demonstrates the design process based on the
UCC25800-Q1 transformer driver.
Table 8-1. Electrical Performance Specifications
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Input Characteristics
VIN, Input voltage, DC
Output Characteristics
VOUT1, set point, DC
IOUT1, output current range
VOUT1, regulation
15
V
17.93
18.10
-4.98
18.27
V
mA
%
0
85
1.0
-4.94
0
IOUT1 = IOUT2, 0 to full load
–1.0
–5.02
–85
VOUT2, set point
V
IOUT1, output current range
VOUT2, regulation
mA
%
IOUT1 = IOUT2, 0 to full load
IOUT1 = IOUT2, full load
IOUT1 = IOUT2, full load
-1.0
1.0
VOUT1, peak to peak ripple
VOUT2, peak to peak ripple
System Characteristics
fSW, switching frequency
IOC, Over current limit
50
35
mV
mV
Normal operation
500
100
kHz
mA
8.2.3 Detailed Design Procedure
The design of the isolated bias supply based on the UCC25800-Q1 transformer driver involves both the power-
stage design and the controller parameters design.
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The power-stage design involves the selection of the transformer and the resonant capacitors. Traditionally, the
LLC transformer design is complicated because the design goal is to optimize the efficiency performance, the
input and output voltage ranges, achieving ZVS, as well as minimizing the size of the transformer. It is a lot
easier when design the transformer for the isolated bias supply because the design goal is to make it simple
and robust. The efficiency is important but not critical since the gate driver power is a tiny portion of the overall
system power.
Step 1: Transformer turns-ratio selection
Because this isolated bias supply operates with open-loop control, the voltage accuracy is not able to get
down to 1%. The post regulators, such as a linear regulator can be used to achieve 1% regulation accuracy.
Therefore, when designing the LLC converter output voltage, the headroom for the post regulator stage needs to
be considered.
At the resonant frequency, together with the voltage doubler output, the LLC converter voltage gain is equal to
the transformer turns-ratio. Therefore, the transformer turns-ratio can be calculated as:
N
V
P
IN
+ 2 V + V
headroom
15V
15V
25V
= N
=
=
=
= 0.6
(10)
PS
N
V
+ V
OUT1 OUT2
18V + 5V + 2 × 0.5V + 1V
S
F
Where:
•
•
VF is the output diode forward voltage drop
Vheadroom is the extra headroom needed for the post regulator
Step 2: Calculate transformer volt-second rating
The transformer volt-second rating on the primary side can be calculated as:
V
IN
2
1
15V
2
1
VS =
×
=
×
= 3.75Vµs
(11)
4f
4 × 500kHz
SW
Step 3: Calculate the transformer currents
The transformer sees highest RMS current right before over current protection. According to Figure 8-6, the
output current is equal to the average current of the secondary-side rectified current. When load current is at the
over current protection level of 100 mA, the primary side current can be calculated. The transformer primary-side
and secondary-side peak and RMS current can be calculated based on Equation 12 through Equation 15.
π
2
π
2
I
=
I
=
OC
× 100mA = 222mA
(12)
rms
S
I
=
2I
= 314mA
(13)
pk
S
rms
S
I
rms
S
222mA
0.6
I
=
=
= 370mA
(14)
(15)
rms
N
P
PS
I
pk
S
314mA
= 523mA
0.6
I
=
=
pk
P
N
PS
From step 1 through 3, the key transformer information can be summarized in Table 8-2. It can be used to share
with transformer vender to get the transformer designed and manufactured. It is recommended to leave some
design margins (30%~50%) for the current ratings to consider the tolerance of the components.
Table 8-2. Transformer parameter summary
Parameter Name
Value
Unit
Primary side to secondary side turns ratio
Primary side volt-second
Primary side peak current
Primary side RMS current
0.6
3.75
523
Vμs
mA
mA
370
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Table 8-2. Transformer parameter summary (continued)
Parameter Name
Value
Unit
mA
mA
Secondary side peak current
Secondary side RMS current
314
222
To minimize the transformer inter-winding capacitance, the split chamber bobbin is recommended, as shown in
Figure 8-7.
Figure 8-7. Split chamber bobbin
Another key transformer parameter is the magnetizing inductance. In traditional LLC converter design, the
magnetizing inductor is used to achieve ZVS and the desired voltage gain to cover the entire input and output
voltage range. Given the open-loop LLC operates with fixed input and output voltages, the sole goal of the
magnetizing inductor is to achieve ZVS. Based on the ZVS criteria, the design target of the magnetizing
inductance can be calculated based on Equation 16. In this equation, Lm is the magnetizing inductor value, td
is the dead-time, fSW is the switching frequency, and CSW is the SW-pin parasitic capacitance (it has a typical
value of 170 pF). With 500-kHz switching frequency and 50-ns of dead-time, the magnetizing inductance can be
calculated as 73.5 μH. This inductor value gives an initial design target of the transformer and the final value
can be different. If the magnetizing inductance is larger, it does not have enough magnetizing current to achieve
full ZVS. With the low input voltage and small parasitic capacitance on the switch node, partial ZVS still brings
in the EMI and loss reduction benefit. If the magnetizing inductance is smaller than the target, it'll create more
current than needed, which results in extra conduction loss. But the loss increase is limited without causing
concerns on the thermal stress or efficiency. Normally, it is recommended to use the core without an air gap, and
the transformer magnetizing inductance is more than 20 times higher than the leakage inductance Otherwise, a
minimum air gap is recommended without causing extra manufacture cost.
t
d
f
L
=
(16)
m
8C
SW SW
Based on the calculation results, Wurth transformer 750319177 is selected to be the transformer. It has a turns
ratio of NPS = 1:1.67, which is 0.6. The magnetizing inductance measured from primary side is 16.5 μH and
the leakage inductance measured from primary side is 0.75 μH. Given the secondary-side resonant is used,
the leakage inductance should be measured from secondary side, with primary side shorted, at the resonant
frequency. The secondary-side leakage inductance is measured as 1.4 μH.
Step 4: Select resonant capacitor
The resonant capacitor selection is based on the resonant frequency. Choose the resonant tank resonant
frequency 10~15% above the switching frequency.
1
1
C =
=
= 60nF
2
(17)
r
2
2
2
4π L f
r r
4π L 1.1f
r
SW
When using the voltage double rectifier, each resonant capacitor value should be half of this value. Therefore, a
22-nF resonant capacitor can be used on each of the resonant capacitor.
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Step 5: Choose output capacitor
The output capacitor selection is based on the output voltage ripple requirement. The output capacitor can be
calculated based on Equation 18. Design the capacitor based on half of the ripple amplitude so that there is
margin for the voltage ripple caused by the capacitor ESR. Choose the output capacitor needs to consider both
the ripple requirement and the gate driver requirement. A 10-μF capacitor can be used in this case. It should be
noticed that the ceramic capacitor loses its capacitance when the voltage is applied.
0.421 × I
OUT
0.421 × 85mA
C
>
=
= 0.358µF
4 × 50mV × 500kHz
(18)
OUT
4V
f
ripple SW
Step 6: Choose primary side DC blocking capacitor
The primary-side half-bridge DC blocking capacitors need to be much larger than the resonant capacitor.
Given the high-switching frequency design, low ESR X7R capacitors with value between 1 μF and 10 μF are
recommended.
Once the power stage is set up, the programming pins of the IC can be set up accordingly. Given the minimum
external components, setting up the UCC25800-Q1 is extremely easy.
Step 7: Setting up RT pin resistor
To set the switching frequency to 500 kHz, according to the description in Oscillator, the RT pin resistor can be
calculated as:
f
SW
Hz
Ω
500kHz
R
=
=
= 50kΩ
(19)
RT
Hz
10
10
Ω
Given 50 kΩ is not a standard resistor value, choose an RRT value of 49.9 kΩ.
Step 8: Setting up OC/DT pin resistor divider
The OC/DT pin is a multi-function pin. It sets the maximum dead-time for the adaptive dead-time, and sets the
OCP levels for over current protection.
For the dead-time setting, generally choose 5 % to 10% of the switching cycle, as the maximum dead-time. This
value can be further adjusted according to the measurement result, depending on the soft switching conditions.
Equation 3 calculates the voltage on DT/CT pin:
150ns × 1V
150ns × 1V
+ 0.9V = 2.4V
0.05
500kHz
V
=
+ 0.9V =
(20)
OC/DT
DT
MAX
The OCP setting is determined by the primary-side peak current. In Equation 15, the primary-side peak current
is calculated as 523 mA. Leaving extra 30% margin, the OCP1 level should be roughly 680 mA. OCP1_4 can be
used as the OCP1 setting.
According to Table 7-1, the Thevenin resistance should be between 7.95 kΩ and 8.25 kΩ. We can use the value
in the middle to set up the resistor and verify the Thevenin resistance after the resistor values are calculated,
The pull-up resistor can be calculated as
Rth × V
REG
8.1kΩ × 5V
= 16.875kΩ ≌ 16.9kΩ
2.4V
Ra =
=
(21)
V
OC/DT
And the pull-down resistor can be calculated as
Rth × V
REG
8.1kΩ × 5V
Rb =
=
= 15.58kΩ ≌ 15.4kΩ
5V − 2.4V
(22)
V
− V
OC/DT
REG
It can be seen, due to the limited standard resistor value, the selected resistor values are different than the
calculated resistor values. The Thevenin resistance needs to be checked. In this case, the Thevenin resistance
is 8.058 kΩ and it is within the OCP1_4 setting range.
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The UCC25800-Q1 based LLC converter can output a single output. It needs some help to split it into the dual
outputs needed for the final designs. Depending on the regulation accuracy requirement, the splitting can be
done using a simple Zener diode, a shunt-regulator, or even with a linear regulator, as demonstrated in Figure
8-8.
V+
Output from
UCC25800-Q1
converter
V-
(a) Split the output voltage using Zener diode
V +
Output from
UCC25800-Q1
converter
œ
V
TL431LI-Q1
(b) Split the output voltage using shunt-regulator
+Output
TL431LI-Q1
Output from
UCC25800-Q1
converter
TL431LI-Q1
-Output
(c) splitting the output voltage using shunt-regulator and linear regulator
Figure 8-8. Different ways of splitting single output voltage to positive and negative outputs
Using the Zener diode, the negative rail voltage is determined by the Zener voltage and the rest of the output
voltage becomes the positive rail. Due to the tolerance of the Zener diode, a shunt-regulator can be used to
improve the negative rail voltage accuracy. Furthermore, a linear regulator can be added to improve the positive
rail voltage accuracy as well. The designer can choose the right solution based on the performance and cost
tradeoffs.
In this design, the shunt-regulator and linear-regulator are used to get 1% accuracy required for the positive and
negative rail. ATL431-Q1 is used as the shunt-regulator and the voltage reference for the linear regulator. Given
the reference voltage of ATL431-Q1 is 2.5 V, to create 5-V shunt-regulator voltage, a 1-kΩ and 1-kΩ voltage
divider can be used to set up the 5-V regulation voltage. On the positive rail side, to create 18-V output voltage,
6.34 kΩ and 1 kΩ can be used to set up the output voltage divider ((6.34+1)✕2.5V=18.35V).
With all the calculated circuit parameters, the design schematic is shown in Figure 8-9.
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J1
15V input
Vin_LLC
TP4
SMBT 2222A E6327
Q1
TP6
18Vo
D2
24Vo
R23
15V
C13
10µF
50V
C14
DNP
0
R5
549
CMSH1-40M TR13
D3
DNP
P1
C3
22nF
50V
TP9
C2
1µF
25V
R6
6.34k
1
2
C12
2.2µF
50V
FLT
R2
DNP
C6
2.2µF
50V
C5
2.2µF
50V
C1
10µF
50V
GND
+18V/85mA
8
3
2
7
5
9
6
TP1
VCC
DIS/FLT
U2
R7
1.0k
T1
TP8
VREG
18Vdc
1
3
8
6
ATL431-Q1
3
2
1
SW
RT
COM
R1
16.5k
SW Node
COM
R9
1.00k
-5Vdc
4
1
OC/DT
SYNC
R11
49.9k
R8
51
P3
EP
C4
1µF
TP10
SYNC
D1
5.1V
COM
C11
C9
22nF
50V
R3
DNP
2
4
5
7
-5Vdc/85mA
GND
NC
NC
NC
NC
50V
R12
16.5k
C8
1µF
25V
C10
2.2µF
10V
J2
R13
51
2.2µF
10V
U1
TP3
TP2
U3
R10
1.0k
UCC25800DGNRQ1
750319177r02
TP5
-Vo
TP7
GND
D4
ATL431-Q1
-5Vo
Fsw=500kHz
GND
GND
CMSH1-40M TR13
Figure 8-9. Circuit schematic for the designed isolated bias supply
8.2.4 Application Curves
25
24.9
24.8
24.7
24.6
24.5
24.4
24.3
24.2
24.1
24
VSW
Ipri
Figure 8-11. Switch-node Voltage (yellow) and
Current (Primary side, 0.2V/A) at Full Load
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
Load current (mA)
Figure 8-10. LLC output voltage load regulation
8.3 What to Do and What Not to Do
Do
•
•
•
Good decoupling between VCC and GND, minimize the loop of VCC-GND and the decoupling capacitor
Use transformer with split chamber bobbin to minimize the EMI noise coupling from the inverter power stage
The UCC25800-Q1 transformer driver can be used to drive single higher power transformer or multiple lower
power transformer
•
•
•
•
Setting the OCP1 level according to the designed load
Use post regulator if the voltage regulation requirement can't be met
Add Zener clamp at output if the output load can be completely removed
If cost is acceptable, use NP0 or C0G type resonant capacitor, or use X7R with much higher voltage rating
than needed
•
Sufficient copper area for thermal management if the ambient temperature is high or the power level is high
Not to Do
•
•
Long VCC-GND decoupling capacitor trace
Set up the OCP1 to the highest level for all designs
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9 Power Supply Recommendations
The UCC25800-Q1 transformer driver drives an LLC converter with constant switching frequency to make the
LLC converter operate near its resonant frequency. When LLC converter operates at its resonant frequency, the
impedance of the resonant tank is equal to zero. The input and output voltages are virtually connected together,
through the transformer turns-ratio. Given the LLC converter is a half-bridge converter, the transformer primary
side only sees half of the input voltage. If the secondary side uses voltage double rectifier, it also only sees
half of the output voltage. The relationship between the input and output voltages is simply the transformer
turns-ratio.
Given that, to achieve a fixed output voltage, the input voltage needs to be fixed. Even though the transformer
driver is recommended to operate with an input voltage source between 9 V and 34 V, it is meant to be one
fixed voltage within this voltage range. Because the relationship between input and output voltages is simply
the transformer turns-ratio, the accuracy of the input would impact the accuracy of the output. There is no
requirement from the transformer driver, while the input voltage accuracy is demanded by the output voltage
requirements.
When the input voltage is very close to 9 V (because it is very close to the UVLO threshold UVLOF) sufficient
input bypass capacitor is recommended to ensure the load transient does not cause the VCC voltage drops
below UVLO threshold UVLOF.
Copyright © 2021 Texas Instruments Incorporated
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UCC25800-Q1
SLUSDX3B – NOVEMBER 2020 – REVISED NOVEMBER 2021
www.ti.com
10 Layout
Given the minimum external components, transformer driver layout is straightforward. The main considerations
are the power loop and the grounding.
10.1 Layout Guidelines
•
The most important layout guideline is to minimize the VCC-GND-bypass capacitor loop. Because this loop
carries all the switching current, it is important to have a low ESL bypass capacitor between VCC and GND,
with the minimum loop. Refer to Layout Example for how to layout the bypass capacitor on VCC to GND.
Return all control signals to GND pin through a separated plane. Avoid sharing path between the signal
ground and the power ground. Use a short trace to connect GND pin to the thermal pad.
Separate the power stage components and signal component to minimize the coupling between these
components
Short VREG-GND-decoupling capacitor loop is recommended. A low ESL decoupling capacitor between
VREG and GND is needed to ensure stable operation of the internal linear regulator.
Add decoupling capacitors on RT and DT/OC pin to improve the noise immunity if it is needed. Refer to
Section 6.3 for recommended maximum capacitor values.
•
•
•
•
•
•
•
•
Short SYNC pin to GND when external synchronization is not used.
Minimize the current loop with high di/dt and minimize the copper area of the switch-node with high dv/dt.
Other general power supply design layout guidelines.
The secondary side of the LLC converter is often connected with the high dv/dt node in the end equipment. In
these cases, it is recommended to minimize the secondary-side copper area.
10.2 Layout Example
To VCC Supply
UCC25800-Q1
CVREG
To transformer
CVCC
Ra
To GND
RRT
Rb
Figure 10-1. Layout example
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UCC25800-Q1
SLUSDX3B – NOVEMBER 2020 – REVISED NOVEMBER 2021
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, UCC25800EVM-1, 2-W LLC converter with 6-V to 26-V DC input and 18-V and 5-V
outputs
Texas Instruments, Reference design PMP22835, Isolated IGBT and SiC driver bias supply reference design
for traction-inverter applications
Texas Instruments, Reference design PMP23061, Pre-regulated isolated driver bias supply reference design
for traction-inverter applications
•
•
•
•
Texas Instruments, UCC25800-Q1 design Calculator
Texas Instruments, UCC25800-Q1 SIMPLIS Transient Model
Texas Instruments, Application note, Bias Supply Design for Isolated Gate Driver Using UCC25800-Q1
Texas Instruments, Functional-safety information, UCC25800-Q1 Functional Safety, FIT Rate, Failure Mode
Distribution and Pin FMA
•
Texas, Instruments, White paper, Power Through the Isolation Barrier: The Landscape of Isolated DC/DC
Bias Power
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-side navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PUCC25800ADGNQ1
UCC25800AQDGNQ1
UCC25800AQDGNRQ1
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HVSSOP
HVSSOP
DGN
DGN
DGN
8
8
8
80
80
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
RoHS & Green
NIPDAUAG
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
580Q
580Q
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
(1.846)
SYMM
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
9
(2.15)
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(2.15)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.06 X 2.40
1.846 X 2.15 (SHOWN)
1.69 X 1.96
0.125
0.15
0.175
1.56 X 1.82
4225480/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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