UCC2581DG4 [TI]

Micropower Voltage Mode PWM; 微功耗电压模式PWM
UCC2581DG4
型号: UCC2581DG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Micropower Voltage Mode PWM
微功耗电压模式PWM

稳压器 开关式稳压器或控制器 电源电路 开关式控制器 光电二极管 信息通信管理
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application  
INFO  
UCC1581  
UCC2581  
UCC3581  
available  
Micropower Voltage Mode PWM  
BLOCK DIAGRAM  
FEATURES  
Low 85µA Startup Current  
Low 300µA Operating Current  
Automatically Disabled  
Startup Preregulator  
Programmable Minimum Duty  
Cycle with Cycle Skipping  
Programmable Maximum  
Duty Cycle  
Output Current 1A Peak  
Source and Sink  
Programmable Soft Start  
Programmable Oscillator  
Frequency  
External Oscillator  
Synchronization Capability  
UDG-95011-1  
Note: Pin Connection shown for 14-pin Package  
DESCRIPTION  
The UCC3581 voltage mode pulse width modulator is de- A linear preregulator driver in conjunction with an exter-  
signed to control low power isolated DC - DC converters nal depletion mode N-MOSFET provides initial controller  
in applications such as Subscriber Line Power (ISDN power. Once the bootstrap supply is functional, the  
I.430). Primarily used for single switch forward and preregulator is shut down to conserve power. During light  
flyback converters, the UCC3581 features BiCMOS cir- load, power is saved by providing a programmable mini-  
cuitry for low startup and operating current, while main- mum duty cycle clamp. When a duty cycle below the  
taining the ability to drive power MOSFETs at minimum is called for, the modulator skips cycles to pro-  
frequencies up to 100kHz. The UCC3581 oscillator al- vide the correct average duty cycle required for output  
lows the flexibility to program both the frequency and the regulation. This effectively reduces the switching fre-  
maximum duty cycle with two resistors and a capacitor. A quency, saving significant gate drive and power stage  
TTL level input is also provided to allow synchronization losses.  
to an external frequency source.  
The UCC3581 is available in 14-pin plastic and ceramic  
The UCC3581 includes programmable soft start circuitry, dual-in-line packages and in a 14-pin narrow body small  
overcurrent detection, a 7.5V linear preregulator to con- outline IC package (SOIC). The UCC1581 is specified for  
trol chip VDD during startup, and an on-board 4.0V logic  
supply.  
operation from 55°C to +125°C, the UCC2581 is speci-  
fied for operation from 40°C to +85°C, and the  
UCC3581 is specified for operation from 0°C to +70°C.  
The UCC3581 provides functions to maximize light load  
efficiency that are not normally found in PWM controllers.  
MARCH 1999 - REVISED MARCH 2003 - SLUS295B  
UCC1581  
UCC2581  
UCC3581  
CONNECTION DIAGRAMS  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage (IDD 10mA). . . . . . . . . . . . . . . . . . . . . . . . 15V  
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA  
DIL-14, SOIC-14 (Top View)  
N or J, D Packages  
V
REF Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA  
OUT Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 1A  
Analog Inputs  
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to (VDD + 0.3V)  
VC, ISEN, SYNC, DCMIN. . . . . . . . . . –0.3V to (VREF + 0.3V)  
Power Dissipation at TD = 25°C  
(N, J, Q, L Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W  
(D Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65W  
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature . . . . . . . . . . . . . . . . . . . –55C to +150°C  
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C  
Unless otherwise specified, all voltages are with respect to  
Ground. Currents positive into, negative out of the specified ter-  
minal. Consult Packaging Section of Databook for thermal limi-  
tations and considerations of packages.  
ORDERING INFORMATION  
TEMPERATURE RANGE  
–55°C to +125°C  
PACKAGE  
CDIP  
UCC1581J  
UCC2581D  
UCC2581N  
UCC3581D  
UCC3581N  
–40°C to +85°C  
–40°C to +85°C  
0°C to +70°C  
0°C to +70°C  
SOIC  
PDIP  
SOIC  
PDIP  
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VDD = 10V, 0.1µF capacitor  
from VDD to GND, 1.0µF capacitor from REF to GND, RT1 = 680k, RT2 = 12k, CT = 750pF and TA = TJ.  
PARAMETER  
Reference Section  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Output Voltage  
I = –0.2mA  
3.94  
4.0  
20  
4.06  
45  
V
Load Regulation  
–5.0mA < I < –0.2mA  
mV  
Undervoltage Lockout Section  
Start Threshold  
6.7  
6.2  
0.2  
7.3  
6.8  
0.5  
7.9  
7.4  
0.8  
V
V
V
Minimum Operating Voltage After Start  
Hysteresis  
Linear Preregulator Section  
Regulated VDD Voltage  
Regulated VDD to UVLO Delta  
VDD Override Threshold  
Oscillator Section  
Frequency  
7.0  
7.5  
8.0  
600  
8.2  
V
mV  
V
100  
230  
25°C  
18  
19.5  
3.0  
2.5  
1.0  
2.1  
1.8  
21  
kHz  
%
V
Temperature Stability  
CT Peak Voltage  
(Note 1)  
(Note 1)  
(Note 1)  
CT Valley Voltage  
V
SYNC VIH  
1.9  
81  
2.3  
V
SYNC VIL  
(Note 1)  
V
PWM SECTION  
Maximum Duty Cycle  
Minimum Duty Cycle  
84  
87  
0
%
%
(VC < 1.0V) DCMIN = 0V  
(VC > 1.0V at start of cycle) DCMIN = 1.18V  
(DCMIN), (Note 1)  
7
10  
20  
20  
13  
%
Input Bias Current  
–150  
–150  
150  
150  
nA  
nA  
(VC), (Note 1)  
2
UCC1581  
UCC2581  
UCC3581  
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VDD = 10V, 0.1µF capacitor  
from VDD to GND, 1.0µF capacitor from REF to GND, RT1 = 680k, RT2 = 12k, CT = 750pF and TA = TJ.  
PARAMETER  
Current Sense Section  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Input Bias Current  
Overcurrent Threshold  
Output Section  
OUT Low Level  
–150  
0.4  
20  
150  
0.6  
nA  
V
0.5  
I = 100mA  
0.6  
0.6  
20  
1.2  
1.2  
100  
V
V
OUT High Level  
Rise/Fall Time  
I = –100mA, VDD – OUT  
(Note 1)  
ns  
Soft start Section  
Soft start Current  
Chip Enable Section  
VIH  
SS = 2V  
–9  
–11.5  
–14  
µA  
1.9  
1.7  
180  
5
2.0  
1.8  
230  
10  
2.1  
1.9  
280  
15  
V
V
VIL  
Hysteresis  
mV  
µA  
Source Current  
Overall Section  
Start-Up Current  
Operating Supply Current  
VDD Zener Shunt Voltage  
IDD Stand-by Shunt Voltage  
VDD < Start Threshold  
VC = 0V  
85  
300  
15  
130  
600  
16.5  
150  
µA  
µA  
V
IDD = 10mA  
13.5  
EN = 0V  
100  
µA  
Note 1: Guaranteed by design. Not 100% tested in production  
PIN DESCRIPTIONS  
2.0V  
RT1  
CT: Oscillator timing capacitor pin. Minimum value is  
100pF.  
The oscillator charging current is 9.2•  
.
DCMIN: Input for programming minimum duty cycle  
where pulse skipping begins. This pin can be grounded  
to disable minimum duty cycle feature and pulse  
skipping.  
See Application Diagram Fig. 1.  
2.0V  
The current into this pin is  
.
RT1  
The value of RT1 should be between 220k and 1M.  
EN: Enable input. This pin has an internal 10µA pull-up.  
A logic low input inhibits the PWM output and causes the  
soft start capacitor to be discharged.  
RT2: Resistor pin to program oscillator discharge time.  
The minimum value of RT2 is 10k. See Application  
Diagram Fig. 1.  
GND: Circuit ground.  
SS: Soft start capacitor pin. The charging current out of  
SS is 3.75X the current in RT1.  
GT: Pin for controlling the gate of an external depletion  
mode N-MOSFET for the startup supply. The external  
N-MOSFET regulates VDD to 7.5V until the bootstrap  
supply comes up, then GT goes low.  
SYNC: Oscillator synchronization pin. Rising edge  
triggered CMOS/TTL compatible input with a 2.1V  
threshold. SYNC should be grounded if not used. The  
minimum pulse width of the SYNC signal is 100ns.  
ISEN: Input for overcurrent comparator. This function can  
be used for pulse-by-pulse current limiting. The threshold  
is 0.5V nominal.  
VC: Control voltage input to PWM comparator. The  
nominal control range of VC is 1.0V to 2.5V.  
OUT: Gate drive output to external N-MOSFET.  
VDD: Chip input power with an 15V internal clamp. VDD  
is regulated by startup FET to 7.5V until the bootstrap  
voltage comes up. VDD should be bypassed at the chip  
with a 0.1µF minimum capacitor.  
REF: 4.0V reference output. A minimum value bypass  
capacitor of 1.0µF is required for stability.  
RT1: Resistor pin to program oscillator charging current.  
3
UCC1581  
UCC2581  
UCC3581  
APPLICATION INFORMATION  
The UCC3581’s oscillator allows the user the flexibility to  
program the frequency and the duty cycle by adjusting  
two resistors and a capacitor. Application Diagram Fig. 1  
shows these components as RT1, RT2, and CT. RT1 pro-  
grams the timing capacitor charging current which results  
in a linear ramp charging CT. Discharge of CT is accom-  
plished though RT2 which results in a standard RC dis-  
charge waveform. The oscillator on-time (CT charging) is  
calculated by the formula  
RT2  
UCC3581  
1
CT  
RT2 14  
SYNC 13  
RT1 12  
V
IN  
C
T
BSS129 OR  
EQUIV.  
D2  
2
3
GT  
VDD  
1µF  
RT1  
tON =0.082RT1CT .  
EN 11  
SS 10  
The off-time (CT discharging) is calculated by the formula  
tOFF =0.95 RT1CT .  
Q1  
4
OUT  
C
SS  
REF  
Resistor RT1 programs the charging current. The current  
is:  
5
6
GND  
REF  
DCMIN  
9
8
2.0V  
.
RT1  
REF  
1µF  
REF  
CT charging current is 9.2 times the current in RT1. RT1  
can range from 220kto 1M. Minimum capacitor size  
is 100pF, and minimum RT2 size is 10k.  
7
ISEN  
VC  
V
IN  
U1  
D1  
A Block Diagram of the Oscillator is shown in Fig. 2. The  
oscillator also has an external synchronization pin.  
When a low to high level is detected, and if the oscilla-  
tor’s output is in the high state (CT charging), the oscilla-  
tor output immediately goes low and CT starts  
discharging. The sync input is rising edge sensitive and  
is ignored when the oscillator output is low.  
REF &  
E/A  
U1  
R
L
T1  
UDG-99043  
Figure 1. Application diagram.  
UDG-96105  
Figure 2. Oscillator.  
4
UCC1581  
UCC2581  
UCC3581  
APPLICATION INFORMATION (cont.)  
The externally bypassed 4.0V reference is controlled by  
undervoltage lockout and chip enable circuitry. The en-  
able input is internally tied to a 10µA current source  
which allows the pin to be driven by an open collector  
driver. The part is also enabled if EN floats. The  
UCC3581 has a soft start function which requires a user  
supplied external timing capacitor. When in soft start  
mode, the soft start capacitor, CSS, is charged with a  
constant current source. The soft start current is 3.75X  
the current in RT1.  
A Typical Micropower Application  
The circuit shown in Fig. 3 illustrates the use of the  
UCC3581 in a micropower application. The isolated 5V  
flyback power supply uses a minimum of parts and oper-  
ates over an 8:1 input voltage range (15VDC to 120VDC)  
while delivering a regulated 5V output with a load swing  
from 0W to 1W. It operates in the discontinuous mode at  
light load or high line, and continuous mode at heavier  
loads and lower line voltages. Higher input line voltages  
are possible by simply increasing the voltage ratings of  
C1, Q1, D1 and D2.  
There is an on-chip control amplifier, which when driving  
the gate of an external depletion mode N-MOSFET, acts  
as a 7.5V linear preregulator supplying VDD directly from  
the primary input power line. The preregulator may sub-  
sequently be fully disabled by a tertiary bootstrap winding  
providing a minimum of 8.2V to the VDD pin.  
The most notable feature of the design is its efficiency.  
With a load of 1 watt, the typical efficiency is 82%, drop-  
ping to 70% around 50mW. With a load of only 12.5mW,  
the efficiency remains as high as 50%. At this load, with  
an input of 50V, the total input current is only 500µA.  
Note that the power supply can be disabled by pulling the  
UCC3581 enable pin low, in which case the input current  
drops to less than 150µA.  
Computation of DCMIN  
DCMIN for a given duty cycle is calculated as follows:  
(
)
tON +tOFF  
The UCC3581 achieves very low losses by means of low  
quiescent current and pulse skipping at light loads which  
reduces switching losses. The degree of pulse skipping is  
controlled by programming the minimum duty cycle. In  
this example, the frequency is 35kHz at maximum load  
and drops to <2kHz at 12.5mW load (minimum pulse  
width of around 6µsec, or 21% duty cycle at 35kHz).  
Another way losses are reduced is operating with a VDD  
of around 10V rather than the more common 12V to 16V.  
At such light primary currents, the MOSFET remains in  
full saturation with a gate drive voltage well below 10V.  
V =iOSC DC •  
CT  
where:  
i = oscillator charge current = 9.2 . (2.0V/RT1)  
DC = Duty Cycle, as a fraction of 1  
tON = 0.082 RT1 CT  
tOFF = 0.95 RT2 CT  
CT = Oscillator Capacitor  
The CT pin ramp slews from 1V to 2.5V. Therefore, add  
V to 1V to get DCMIN voltage.  
Gate drive losses are minimized by choosing a MOSFET  
with low total gate charge, in this case only 8nC maxi-  
mum. By choosing a large gate drive resistor, EMI is min-  
imized by reducing peak currents. Due to pulse skipping,  
switching times are less critical for efficiency at light load.  
Example: For 10% duty cycle with RT1 = 680k, RT2 =  
12k, and CT = 705pF,  
The shunt regulator (LM3411) and optocoupler  
(MOC8100) are also key to the efficiency at such light  
loads, and were chosen for their low operating current.  
The LM3411 has a quiescent current of only 150µA max-  
imum (compared to 1mA for the more common TL431).  
In addition, because it is not a three terminal device, the  
LM3411’s quiescent current does not flow in the  
optocoupler LED. Since this bias current is not in the  
feedback control path, a higher value pull-up resistor can  
be used on the optocoupler output transistor, further re-  
ducing losses.  
(
)
tON +tOFF  
V =iOSC DC •  
CT  
2.0V  
(0.1)4.18210  
9.2•  
5 sec+8.55 106 sec  
680k  
=
750 1012  
V =0.18V  
Therefore,  
DCMIN =1V +0.18V =1.18V  
5
UCC1581  
UCC2581  
UCC3581  
TYPICAL APPLICATION  
UDG-96104  
Figure 3. Micropower power supply with 50% efficiency at 12.5mW load.  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
25V Line  
100V Line  
10  
100  
1000  
Output Load [mW]  
Figure 4. UCC3581 efficiency vs. line and load.  
6
UCC1581  
UCC2581  
UCC3581  
APPLICATION INFORMATION (cont.)  
A rather large soft start capacitor was chosen to give a If the sync input is used, it should not be left in a high im-  
startup time of several hundred milliseconds, reducing pedance state where noise could cause false triggering.  
the input surge current while the output is coming up.  
If unused, it should be grounded.  
Note that for stability, the UCC3581 VREF bypass capaci- The transformer was designed with a standard Magnetics  
RM8 ferrite core using P material, gapped for an AL of  
1600mH/1000Turn2. The primary consists of 44 turns,  
while the 5V secondary has 10 turns and the bootstrap  
winding 18 turns. For simplicity, all the windings can be  
#28 AWG. A two section bobbin was used to provide high  
primary to secondary isolation. A much smaller design,  
with reduced isolation, could have been done for this low  
power level.  
tor needs to be at least 1µF. The VDD supply also needs  
some capacitance to hold it up between pulses at light  
load and high line, where the frequency may drop to less  
than 1kHz due to pulse skipping. Otherwise it may drop  
low enough for the startup MOSFET to be biased on,  
lowering efficiency.  
TYPICAL CHARACTERISTIC CURVES  
140  
4.10  
4.08  
4.06  
4.04  
4.02  
4.00  
3.98  
3.96  
3.94  
3.92  
3.90  
470k/47k  
120  
100  
680k/12k  
80  
60  
40  
20  
0
1M/10k  
220k/10k  
-75 -50 -25  
0
25  
50  
75 100 125  
100  
1000  
CT [pF]  
10000  
TEMPERATURE [°C]  
Figure 5. Reference voltage vs. temperature.  
Figure 6. Frequency vs. CT vs. RT1 and RT2.  
1600  
100  
1nF LOAD  
1M/10K  
1400  
90  
80  
70  
60  
50  
40  
30  
1200  
1000  
800  
600  
400  
200  
0
680K/12K  
220K/10K  
NO  
LOAD  
470K/47K  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
FREQUENCY [kHz]  
FREQUENCY [kHz]  
Figure 7. Duty cycle vs. frequency vs. RT1 / RT2.  
Figure 8. IDD vs. frequency RT1 = 680k, RT2 = 12k.  
7
UCC1581  
UCC2581  
UCC3581  
TYPICAL CHARACTERISTIC CURVES (cont.)  
40  
35  
30  
25  
20  
15  
10  
5
0
200  
400  
600  
800  
1000  
1200  
RT1 [kW]  
Figure 9. Soft start current vs. RT1.  
UNITRODE CORPORATION  
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054  
TEL. (603) 424-2410 FAX (603) 424-3460  
8
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
UCC2581D  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
D
14  
14  
14  
14  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
UCC2581D  
UCC2581DG4  
UCC2581DTR  
UCC2581DTRG4  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
D
50  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
UCC2581D  
UCC2581D  
UCC2581D  
2500  
2500  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
UCC2581J  
UCC2581Q  
UCC3581D  
OBSOLETE  
OBSOLETE  
ACTIVE  
UTR  
UTR  
D
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 85  
-40 to 85  
0 to 70  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
14  
14  
14  
14  
14  
14  
50  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
UCC3581D  
UCC3581D  
UCC3581D  
UCC3581D  
UCC3581N  
UCC3581N  
UCC3581DG4  
UCC3581DTR  
UCC3581DTRG4  
UCC3581N  
ACTIVE  
ACTIVE  
D
D
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Call TI  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
2500  
2500  
25  
Green (RoHS  
& no Sb/Br)  
ACTIVE  
D
Green (RoHS  
& no Sb/Br)  
ACTIVE  
N
Green (RoHS  
& no Sb/Br)  
UCC3581NG4  
UCC3581Q  
ACTIVE  
N
25  
Green (RoHS  
& no Sb/Br)  
OBSOLETE  
UTR  
TBD  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
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Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Mar-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
UCC3581DTR  
SOIC  
D
14  
2500  
330.0  
16.4  
6.5  
9.0  
2.1  
8.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Mar-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOIC 14  
SPQ  
Length (mm) Width (mm) Height (mm)  
367.0 367.0 38.0  
UCC3581DTR  
D
2500  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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