UCC2583NG4 [TI]
Switch Mode Secondary Side Post Regulator; 开关模式二次侧后稳压器
| 型号： | UCC2583NG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Switch Mode Secondary Side Post Regulator |
| 文件： | 总18页 (文件大小：1097K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC1583
UCC2583
UCC3583
Switch Mode Secondary Side Post Regulator
FEATURES
DESCRIPTION
• Precision Secondary Side Post
Regulation for Multiple Output Power
Supplies
The UCC3583 is a synchronizable secondary side post regulator for preci-
sion regulation of the auxiliary outputs of multiple output power supplies. It
contains a leading edge pulse width modulator, which generates the gate
drive signal for a FET power switch connected in series with the rectifying
diode. The turn-on of the power switch is delayed from the leading edge of
the secondary power pulse to regulate the output voltage. The UCC3583
contains a ramp generator slaved to the secondary power pulse, a voltage
error amplifier, a current error amplifier, a PWM comparator and associ-
ated logic, a gate driver, a precision reference, and protection circuitry.
• Useful for Both Single Ended and
Center Tapped Secondary Circuits
• Ideal Replacement for Complex
Magnetic Amplifier Regulated Circuits
• Leading Edge Modulation
The ramp discharge and termination of the gate drive signal are triggered
by the synchronization pulse, typically derived from the falling edge of the
transformer secondary voltage. The ramp starts charging again once its
low threshold is reached. The gate drive signal is turned on when the ramp
voltage exceeds the control voltage. This leading edge modulation tech-
nique prevents instability when the UCC3583 is used in peak current mode
primary controlled systems.
• Does Not Require Gate Drive
Transformer
• High Frequency (>500kHz) Operation
• Applicable for Wide Range of Output
Voltages
• High Current Gate Driver (0.5A
The controller operates from a floating power supply referenced to the out-
put voltage being controlled. It features an undervoltage lockout (UVLO)
circuit, a soft start circuit, and an averaging current limit amplifier. The cur-
rent limit can be programmed to be proportional to the output voltage, thus
achieving foldback operation to minimize the dissipation under short circuit
conditions.
Sink/1.5A Source)
• Average Current Limiting Loop
(continued)
TYPICAL APPLICATION AND BLOCK DIAGRAM
UDG-96201-2
Note: Pin connections shown for 14-pin packages.
SLUS299B - OCTOBER 1998 - REVISED JANUARY 2005
UCC1583
UCC2583
UCC3583
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
IVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VDD + 1V
IRAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30mA
PCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.2V to 0.2V
DIL-14, SOIC-14 (Top View)
J, N, or D Packages
I
GATE (twp < 1µS and Duty Cycle < 10%) . . . . . . –0.8A to 1.8A
ICOMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5mA to 5mA
ICAO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5mA to 5mA
VSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6V to VREF +0.3V
ISYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –05mA to 5mA
INV, SS, ILIM, ISENSE. . . . . . . . . . . . . . –0.3V to VREF + 0.3V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
All voltages are with respect to the COM terminal unless other-
wise stated. Currents are positive into, negative out of the
specified terminal. Consult Packaging Section of Databook for
thermal limitations and considerations of packages.
PLCC-20 (Top View)
Q Package
THERMAL IMPEDANCE
PACKAGE
N-14
J-14
D-14
PLCC-20
qja
90
90-120
50-120
43-75
qjc
45
28
35
34
Note 1. qja (junction to ambient) is for devices mounted to 5 in2
FR4 PC board with one ounce copper where noted. When re-
sistance range is given, lower values are for 5 in2 aluminum
PC board. Test PWB was .062 in thick and typically used 0.635
mm trace widths for power pkgs and 1.3 mm trace widths for
non-power pkgs with a 100x100 mil probe land area at the end
of each trace
Note 2. qjc data values stated were derived from
MIL-STD-1835B. MIL-STD-1835B states that “The baseline
values shown are worst case (mean + 2s) for a 60x60 mil
microcircuit device silicon die and applicable for devices with
die sizes up to 14400 square mils. For device die sizes greater
than14400 square mils use the following values; dual-in-line,
11°C/W; flat pack, 10°C/W; pin grid array, 10°C/W”.
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to 125°C for
UCC1583, –40°C to 85°C for UCC2583, and 0°C to 70°C for UCC3583; VDD = 12V, RT = 60k, CT = 100pF, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Ramp Generation and Synchronization
Maximum Input Operating Frequency
Ramp Frequency, Free Running
For input with 5% to 90% duty cycle (Note 1)
500
95
kHz
T
T
A = 25°C
100
100
3.6
0
105
110
kHz
kHz
mA
V
A = -55°C to 125°C
90
Ramp Discharge Current
VRAMP = 0.5V
2.0
Low Threshold Voltage
No min, no max, 0=TYP
High Threshold Voltage
3.75
4
4.25
V
Synchronizing Threshold Voltage (On)
Synchronizing Comparator Hysteresis
(Note 1)
1
V
1
V
2
UCC1583
UCC2583
UCC3583
ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to 125°C for
UCC1583, –40°C to 85°C for UCC2583, and 0°C to 70°C for UCC3583; VDD = 12V, RT = 60k, CT = 100pF, TA = TJ.
PARAMETER
Output Duty Cycle
TEST CONDITIONS
MIN
TYP
MAX UNITS
Minimum Duty Cycle
Maximum Duty Cycle
Voltage Error Amplifier
VINV
Output D/C = Output PW / Input PW
Output D/C = Output PW / Input PW
0
%
%
100
VCOMP = VINV, 0°C to 70°C (UCC3583)
2.462
2.45
2.5
2.5
300
450
5.5
90
2.538
2.55
500
700
6.0
V
V
VCOMP = VINV, All Other Temperature Ranges
IINV
VCOMP = VINV
nA
mV
V
VCOMP Low
VINV = 2.6V, ICOMP = 100µA
VINV = 2.4V, ICOMP = –100µA
No Load
V
COMP High
5.0
70
3
AVOL
dB
MHz
GBW Product
At f = 100kHz, TA = 25°C (Note 1)
5
Current Error Amplifier
Input Offset Voltage
Input CM Low
10
0
mV
V
Common Mode for CS and ILIM (Note 1)
Common Mode for CS and ILIM (Note 1)
V+IN = 0V, V–IN = 0.1V, ICAO = 100µA
V+IN = 0V, V–IN = 0.1V, ICAO = –100µA
Input CM High
2
V
V
V
CAO Low
CAO High
250
5.5
0
500
6.0
50
mV
V
5.0
–50
70
2
Input Current (ILIM and CS Pins)
AVOL
nA
dB
MHz
µA
No Load
90
4
GBW Product
At f = 100kHz, TA = 25°C
Soft Start Current
10
25
UVLO
VDD On Threshold Voltage
VDD Off Threshold Voltage
UVLO Hysteresis
Bias Supply
8.5
7.9
0.3
9.0
8.4
0.6
9.5
8.9
0.9
V
V
V
Supply Clamp Voltage
Supply Current (VDD)
Output Driver
VSAT High
13
14
3
15
5
V
f = 100kHz With No Gate Output Load
mA
IGATE = –150mA
IGATE = 50mA
CGATE = 1nF
0.6
0.4
50
1.0
0.75
75
V
V
VSAT Low
Rise Time
ns
ns
Fall Time
CGATE = 330pF
20
40
Reference
VREF
IREF = 0, 0°C to 70°C (UCC3583)
IREF = 0, All Other Temperature Ranges
VDD = 10V to 14V
4.925
4.900
5
5
2
1
5.075
5.100
30
V
V
Line Regulation
Load Regulation
mV
mV
IREF = 0mA to 2mA
20
Note 1: Ensured by design. Not 100% tested in production.
3
UCC1583
UCC2583
UCC3583
PIN DESCRIPTIONS
CAO: Output of the current error amplifier. Averaging of 1mA discharges RAMP when synchronization signal
the sensed current signal is provided by connecting an appears or when RAMP crosses a 4V threshold. In the
integrating capacitor between ILIM and CAO. CAO feeds intended mode of operation, the switching frequency is
into the PWM comparator input and controls the loop determined by the secondary power pulse. The RC
when its voltage is higher than the voltage at COMP components at RAMP should be selected to give an
(output of the voltage error amplifier).
appropriately sized ramp signal. In the absence of a
synchronizing pulse, these RC components determine
the free running frequency of the controller.
COM: Signal ground for the chip. It is connected to the
positive terminal of the output voltage being regulated by
the IC.
REF: Precision 5V reference pin. REF stays off until VDD
exceeds 9V and turns off again when VDD drops below
8.4V. Bypass REF to COM.
COMP: Output of the voltage error amplifier fed into the
PWM comparator. Loop compensation components are
connected between COMP and INV.
SS: This pin provides a soft start function. A capacitor to
REF programs the soft start time. During soft start, the
PWM comparator is controlled by the soft start voltage
resulting in a slow increase in output duty cycle. Once
the soft start capacitor is discharged, output control is
dictated by the larger of the output at CAO or COMP.
CS: Non-inverting input of the current error amplifier. The
sensed current signal from the current sense resistor is
connected to this pin. By making the signal at CS
proportional to the output voltage, effective current
foldback limiting can be provided.
SYNC: Synchronization input pin. It is connected to a
signal representative of the secondary power pulse. One
possible implementation is to use a resistive divider
between terminal S2 of the secondary winding shown in
Figure 1 and REF for generating the input to the SYNC
pin. The synchronizing comparator is referenced to 0.5V
and has ±500mV of hysteresis. The trip levels are
approximate 1.0V and 0.0V. The designer should prevent
the SYNC pin from exceeding 0.3V below ground as this
will turn on the ESD diode.
GATE: Gate drive output for the power switch FET. The
drive pin has a 0.5A sink/1.5A source capability and very
low output off-state impedance.
ILIM: Inverting input of the current error amplifier. It sets
the DC limit for the output current.
INV: Inverting input of the voltage error amplifier. The
feedback signal is connected to this pin using a resistive
divider between REF and –VO.
PCOM: Power ground for the chip. It is connected to the
VD: Power supply for the output driver. VD should be tied
to VDD in the application.
source terminal of the MOSFET being regulated by the
IC.
VDD: Power supply for the chip. VDD should be
bypassed to COM. VDD has to be 9V for the IC to start
and 8.4V for it to remain operational. A shunt clamp from
VDD to COM limits the supply voltage to 14V.
RAMP: This pin is the input to the PWM comparator and
provides a ramp signal for generation of the PWM signal.
A capacitor to COM and a resistor to REF set the
charging rate for the ramp. An internal current source of
APPLICATION INFORMATION
Power Stage Circuit Configuration
and terminations easier to implement. Typical set-up and
circuit waveforms of the UCC3583 system application
are shown in Figure 1. Figure 2 shows waveforms for a
single ended output rectifier application of the UCC3583
shown on page 1. The UCC3583 can also be used in
half bridge rectifier applications as shown by the circuit
and waveforms depicted in Figures 3 and 4. Referencing
the IC to the positive output terminal creates a require-
ment for a floating bias voltage for the IC which can be
referenced to the same positive voltage terminal. Possi-
ble implementations of deriving the floating bias voltage
are shown in Figure 5.
The UCC3583 is designed for use in a post regulator ap-
plication for tightly regulating auxiliary outputs in a multi-
ple output converter. The post regulation is applied to the
secondary side power pulse of a power transformer
where the power pulse is controlled by the feedback sig-
nal from the main output. In order to simplify the applica-
tion of the UCC3583, it is required that the IC be
referenced to the positive output terminal and the output
filter inductor be placed in the return path. The placement
of the inductor in the return path facilitates better EMI
performance, in addition to making magnetic designs
4
UCC1583
UCC2583
UCC3583
APPLICATION INFORMATION (cont.)
CT •VRAMP p– p
For the circuit shown in Figure 5a, CC1 is charged when
the transformer voltage is positive and the synchronous
switch is on. During the off period of Q-SYNC, the charge
is transferred to CC2 through diode DC2. Diode DC3
charges CC2 during the blocking interval of Q-SYNC.
This method is preferable when the transformer positive
voltage is high enough to generate the required bias volt-
age. For the circuit shown in Figure 5b, CC1 is charged
during the period when reverse (reset) voltage appears
across the secondary. The charge on CC1 is transferred
to CC2 through DC2 when Q-SYNC turns on. This
method is preferable when the reverse voltage is high
enough to generate the required bias voltage. The series
resistor should be chosen to handle the required voltage
drop at full IC operating current when the zener clamp
across VDD and COM is activated.
(
)
tDIS
=
≈ 3000 • CT
IRAMP
(
)
dis
The values of RT and CT are also dictated by the fact that
the ramp is discharged through an internal impedance of
2k. The value of RT needs to be at least 50k to ensure
that the internal discharge current is the current through
RT during the entire discharge period. This results in
making the value of CT relatively small for a desired fre-
quency of operation.
When the synchronizing signal is available, the oscillator
frequency should be programmed to be lower than the
synchronizing frequency to ensure proper operation. A
large difference in self-running and synchronizing fre-
quencies leads to smaller ramp amplitude and higher
noise sensitivity. The ramp capacitor is discharged when
the synchronization signal arrives and begins charging
when the low threshold is crossed.
The following is a description of the major functional
blocks of the UCC3583. Refer to Figure 6 (Typical Appli-
cation Circuit) for component designations.
There are two methods to synchronize to the secondary
pulse. One method is to use the rising edge of the sec-
ondary pulse, which reduces the maximum duty cycle
available. Subsequently, the post regulator switch cannot
be turned on during the CT discharge time. The other
method is to use the falling edge of the secondary pulse
for synchronization. This method is preferable because it
allows a slower discharge of the ramp capacitor without
affecting the maximum available duty cycle of the post
regulator. The UCC3583 SYNC input needs to reach a
fixed threshold (1.0V typical) for synchronization to take
effect. Hence the IC is usable with either method of syn-
chronization. However, the UCC3583 oscillator configu-
ration is better suited for synchronization to the falling
edge. A recommended method to implement the syn-
chronization is shown in Figure 6. By connecting SYNC
to a resistive divider between REF and the secondary
terminal S2, the synchronization is achieved whenever
the voltage on S2 goes from a negative value to zero. RA
and RB should be selected so that the voltage on the
SYNC pin varies from 0V to 1V. Placement of a Schottky
diode from SYNC to COM prevents the voltage at SYNC
from going negative. The internal hysteretic SYNC com-
parator has an inverting input set to 0.5V with about
±0.5V hysteresis.
UVLO and Start Up
The UCC3583 has an internal undervoltage lockout cir-
cuit which keeps the internal circuitry inactive until VDD
exceeds the upper threshold (9V). Once the chip is acti-
vated, VDD has to be above the lower UVLO threshold
(8.4V) for it to remain functional. The IC requires a low
startup current of only 100µA when VDD is under the
UVLO threshold. VDD has an internal clamp of 14V
which can sink up to 10mA. Measures must be taken not
to exceed this current. The internal reference (REF) is
brought up when the UVLO on threshold is exceeded.
The soft start pin provides an effective means to start the
IC in a controlled manner. An internal current of 10µA
starts discharging a capacitor connected to SS when the
UVLO conditions have been removed. The voltage on
SS controls the duty cycle of the output during the dis-
charge period.
Synchronizing Circuit and Oscillator
UCC3583 is primarily intended for synchronizable opera-
tion where its switching frequency is determined by the
secondary pulse of the power transformer. However, it
has an internal oscillator which allows it to operate in
free-running mode when an external synchronization
pulse is not available. The switching frequency is deter-
mined by resistor RT connected between REF and
RAMP and capacitor CT connected from RAMP to GND.
The frequency is given by:
PWM Comparator
The UCC3583 uses a leading edge PWM scheme. In a
leading edge PWM, the output pulse (gate signal) is
turned on when the error amplifier crosses the PWM
ramp and turned off by the clock/oscillator. Leading edge
modulation is naturally provided by magamp type post
regulators and is an essential feature for post regulators.
Without the leading edge modulation in a multiple output
1
freq =
where tCH =1.56 • RT • CT
tCH +tDIS
and
5
UCC1583
UCC2583
UCC3583
APPLICATION INFORMATION (cont.)
converter with post regulation on one or more outputs, pacitor controls the pulse width. The third control loop is
the primary current shape does not remain monotonic provided by the average current amplifier. By sensing the
and can lead to instability when the primary current is instantaneous inductor current and filtering/averaging it
used for current mode control or current limiting. When with the current error amplifier, accurate current limiting
compared to conventional trailing edge PWMs, the lead- is achieved. This loop is in effect only during the overcur-
ing edge modulation leads to a phase inversion that rent mode and provides a more accurate and noise free
needs to be accounted for in the feedback loop. For the control of the maximum output current compared to con-
UCC3583, this inversion is automatically provided since ventional peak current limiting circuits. The current limit is
the sensed voltage at the power supply output negative set by programming the voltage at ILIM based on the
terminal has a negative polarity with respect to the chip current sense resistor chosen. In addition, the current
common. Thus, UCC3583 does not require inverting limit can be made proportional to the output voltage in or-
buffers which would otherwise be needed.
der to limit the power dissipation under short circuit con-
ditions. This is implemented by inserting a bias voltage
on CS which is proportional to the output voltage.
Error Signal Generation and Current Limiting
The PWM comparator in the UCC3583 is controlled by
three parallel loops with only one of them in effect at a
Gate Drive Circuit
time. During normal operation, the voltage error amplifier The gate drive circuit of the UCC3583 provides high cur-
output is fed to the PWM comparator. The voltage error rent drive capability and is very easy to implement as a
amplifier can be compensated using commonly used result of tying the chip common to the source of the
feedback techniques to achieve the desired dynamic per- switching device. Turn on current is higher (1.5A) as fast
formance. The ouput drive capability of the voltage am- turn on is essential for low losses and effective operation.
During the turn off, the drain voltage disappears, so turn
off time can be slower without increasing switching
losses.
plifier is limited to 100µA, so appropriately high
impedances should be used to utilize the full output
swing of the amplifier. During startup, the soft start ca-
PRIMARY CLOCK
ISOLATION
PRIMARY
PULSE
MAIN OUTPUT
PRIMARY
S1
CURRENT
+
PRIMARY
SIDE
CHIP
COMMON
SSPR
V
V
O
GS
CLOCK
AUXILIARY
OUTPUT
CONTROLLER
S2
–
RAMP
I
SENSE
UCC3583
SYNC
SSPR
VOLTAGE FEEDBACK
POWER
PULSE
UDG-98195
Figure 1. UCC3583 SSPR system application and typical waveforms.
6
UCC1583
UCC2583
UCC3583
APPLICATION INFORMATION (cont.)
Note: All waveforms are referenced to chip common.
UDG-96141-1
Figure 2. Single ended post regulator waveforms.
UDG-96142-1
Figure 3. Half-bridge synchronous post regulator application.
7
UCC1583
UCC2583
UCC3583
APPLICATION INFORMATION (cont.)
UDG-96143-1
Figure 4. Half-bridge synchronous post regulator to waveforms.
8
UCC1583
UCC2583
UCC3583
APPLICATION INFORMATION (cont.)
UDG-96175-1
Figure 5. Possible implementation for floating bias voltage generation.
U N I-
TROD
R
B
UDG-96072-2
Figure 6. Typical application circuit.
9
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
PACKAGING INFORMATION
Orderable Device
UCC2583D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UCC2583D
UCC2583DG4
UCC2583DTR
UCC2583DTRG4
UCC2583N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
N
N
50
2500
2500
25
Green (RoHS
& no Sb/Br)
UCC2583D
UCC2583D
UCC2583D
UCC2583N
UCC2583N
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UCC2583NG4
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UCC2583QTR
UCC2583QTRG3
UCC3583D
ACTIVE
ACTIVE
ACTIVE
PLCC
PLCC
SOIC
FN
FN
D
20
20
14
1000
1000
50
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
0 to 70
UCC2583Q
UCC2583Q
UCC3583D
TBD
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
UCC3583DG4
UCC3583DTR
UCC3583DTRG4
UCC3583N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
N
N
14
14
14
14
14
50
2500
2500
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
UCC3583D
UCC3583D
UCC3583D
UCC3583N
UCC3583N
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UCC3583NG4
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC3583DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
UCC3583DTR
D
2500
Pack Materials-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
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