UCC27201A-Q1 [TI]
具有 8V UVLO 和负电压处理能力的汽车类 3A、120V 半桥栅极驱动器;
| 型号： | UCC27201A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8V UVLO 和负电压处理能力的汽车类 3A、120V 半桥栅极驱动器 栅极驱动 驱动器 |
| 文件： | 总31页 (文件大小：1830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC27201A-Q1
ZHCSDP7 –MAY 2015
UCC27201A-Q1 120V 3A 峰值电流的高频高侧/低侧驱动器
1 特性
3 说明
1
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
UCC27201A-Q1 高频 N 沟道 MOSFET 驱动器由
120V 自举二极管和高侧/低侧驱动器组成，其中高侧/
低侧驱动器配有独立输入，可最大限度提高控制灵活
性。 这可在半桥式、全桥式、两开关正激式和有源箝
位正激式转换器中提供N沟道 MOSFET 控制。 低端和
高端栅极驱动器是独立控制的，并在彼此的接通和关断
之间实现了至 1ns 的匹配。 UCC27201A-Q1 基于常
见的 UCC27200 和 UCC27201 驱动器，但提供了一
些增强功能。 UCC27201A-Q1 的 HS 引脚最高能够承
受 -18V 电压，这使得其在电源噪声环境下的性能得到
了改善。
•
–
器件温度等级 1：-40°C 至 140°C 的环境运行
温度范围
–
–
器件人体模型 (HBM) 分类等级 1C
器件充电器件模型 (CDM) 分类等级 C3
•
•
HS 引脚具备 -18V 的负电压处理能力
可驱动两个采用高侧/低侧配置的 N 沟道金属氧化
物半导体场效应晶体管 (MOSFET)
•
•
•
•
•
•
•
最大启动电压：120V
最大 VDD 电压：20V
片载0.65V VF， 0.6Ω RD 自举二极管
工作频率高于 1MHz
由于在芯片上集成了一个自举二极管，因此无需采用外
部分立式二极管。 为高端和低端驱动器提供了欠压闭
锁功能，如果驱动电压低于规定的门限，则强制输出为
低电平。
20ns 传播延迟时间
3A 吸收，3A 供电输出电流
8ns 上升时间和 7ns 下降时间（采用 1000pF 负载
时）
UCC27201A-Q1 具有 TTL 兼容阈值，并且采用带有散
热焊盘的 8 引脚 SOIC 封装。
•
•
•
1ns 延迟匹配
用于高端和低端驱动器的欠压闭锁功能
器件信息(1)
采用 8 引脚 PowerPad™ 小尺寸集成电路 (SOIC)-
8 (DDA) 封装
器件型号
封装
封装尺寸（标称值）
UCC27201A-Q1
DDA (8)
4.89mm × 3.90mm
2 应用
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
•
•
•
•
•
•
辅助反相器
简化的应用示意图
功率传输电路的 DC-DC 转换器
开关模式电源
+12V
+100V
电机控制
SECONDARY
SIDE
CIRCUIT
VDD
HB
半桥式应用和全桥式转换器
两开关正激式转换器
有源箝位正激式转换器
高电压同步降压型转换器
D 类音频放大器
HI
DRIVE
HI
HO
HS
PWM
CONTROLLER
LI
LO
DRIVE
LO
UCC27201A
VSS
ISOLATION
AND
FEEDBACK
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSC72
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 20
11.1 文档支持................................................................ 20
11.2 商标....................................................................... 20
11.3 静电放电警告......................................................... 20
11.4 术语表 ................................................................... 20
12 机械、封装和可订购信息....................................... 20
7
4 修订历史记录
日期
修订版本
注释
2015 年 3 月
*
首次发布。
2
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
5 Pin Configuration and Functions
8-Pin SOIC-8 Power Pad
Package DDA
(Top View)
1
2
3
4
8
7
6
5
LO
VDD
HB
Exposed
Thermal
Die Pad
VSS
LI
HO
HS
HI
Pin VSS and the exposed thermal die pad are internally connected.
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
DDA
High-side bootstrap supply. The bootstrap diode is on-chip but the external
bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to
this pin. Typical range of HB bypass capacitor is 0.022 μF to 0.1 μF, the value is
dependant on the gate charge of the high-side MOSFET however.
HB
2
P
HI
5
3
I
High-side input.
HO
O
High-side output. Connect to the gate of the high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET.
Connect negative side of bootstrap capacitor to this pin.
HS
4
P
LI
6
8
-
I
O
-
Low-side input.
LO
N/C
Low-side output. Connect to the gate of the low-side power MOSFET.
No connection. Pins labeled N/C have no connection.
Connect to a large thermal mass trace or GND plane to dramatically improve
thermal performance.
PowerPAD™
Pad(2)
G
Positive supply to the lower gate driver. De-couple this pin to VSS (GND). Typical
decoupling capacitor range is 0.22 μF to 1.0 μF.
VDD
VSS
1
7
P
G
Negative supply terminal for the device which is generally grounded.
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
(2) Pin VSS and the exposed thermal die pad are internally connected on the DDA package. Electrically referenced to VSS (GND).
Copyright © 2015, Texas Instruments Incorporated
3
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted). All voltages are with respect to VSS
(1)
PARAMETER
Supply voltage range(2)
Input voltages on LI and HI
DC
MIN
-0.3
MAX
20
UNIT
VDD
VHI, VLI
-0.3
20
-0.3
VDD + 0.3
VDD + 0.3
VHB + 0.3
VLO
Output voltage on LO
Output voltage on HO
Voltage on HS
Repetitive pulse <100 ns(3)
-2
DC
VHS – 0.3
VHO
V
VHB + 0.3,
(VHB - VHS <20)
Repetitive pulse <100 ns(3)
VHS - 2
DC
-1
120
120
120
20
VHS
VHB
Repetitive pulse <100 ns(3)
-18
-0.3
-0.3
Voltage on HB
Voltage on HB-HS
Operating virtual
junction temperature
TJ
-40
-65
+150
+150
+300
Tstg
Storage temperature
°C
W
Lead temperature
(soldering, 10 sec.)
Power dissipation at TA
= 25°C (DDA package)
2.7
(4)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
(3) Values are verified by characterization and are not production tested.
(4) This data was taken using the JEDEC proposed high-K test PCB. See Thermal Information for details.
6.2 ESD Ratings
VALUE
±1000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
8
NOM
MAX
17
UNIT
VDD
VHS
Supply voltage range
Voltage on HS
12
-1
105
110
V
Voltage on HS, (repetitive pulse <100 ns)
-15
VHB
VHS + 8,
VDD –1
VHS + 17,
115
Voltage on HB
Vsr
TJ
Voltage slew rate on HS
50
V / ns
°C
Operating junction temperature range
-40
+140
4
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
6.4 Thermal Information
DDA
(SOIC-8)
THERMAL METRIC
UNITS
8 PINS
40.5
49.0
10.2
3.1
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
9.7
θJCbot
1.5
6.5 Electrical Characteristics
over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = -40°C to
+140°C, (unless otherwise noted)
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD
VDD quiescent current
VLI = VHI = 0
0.4
3.8
0.8
IDDO
IHB
VDD operating current
f = 500 kHz, CLOAD = 0
VLI = VHI = 0 V
5.5
mA
0.8
Boot voltage quiescent current
Boot voltage operating current
HB to VSS quiescent current
HB to VSS operating current
0.4
IHBO
IHBS
IHBSO
INPUT
VHIT
VLIT
f = 500 kHz, CLOAD = 0
VHS = VHB = 110 V
f = 500 kHz, CLOAD = 0
2.5
4
0.0005
0.1
1
uA
mA
Input voltage threshold
Input voltage threshold
Input voltage Hysteresis
Input pulldown resistance
1.7
1.6
2.5
0.8
100
6.2
VIHYS
RIN
100
200
mV
350
7.8
7.2
kΩ
UNDERVOLTAGE PROTECTION (UVLO)
VDD rising threshold
7.1
0.5
6.7
0.4
VDD threshold hysteresis
VHB rising threshold
V
5.8
VHB threshold hysteresis
BOOTSTRAP DIODE
VF
Low-current forward voltage
High-current forward voltage
I VDD - HB = 100 μA
0.65
0.85
0.85
1.1
V
VFI
I VDD - HB = 100 mA
I VDD - HB = 100 mA and 80
mA
RD
Dynamic resistance, ΔVF/ΔI
0.6
1.0
Ω
LO GATE DRIVER
VLOL Low level output voltage
ILO = 100 mA
0.18
0.25
0.4
0.4
ILO = -100 mA, VLOH = VDD
VLO
-
TJ = -40 to 125°C
TJ = -40 to 140°C
V
A
VLOH
High level output voltage
ILO = -100 mA, VLOH = VDD
VLO
-
0.25
0.42
Peak pull-up current
VLO = 0 V
3
3
Peak pull-down current
VLO = 12 V
Copyright © 2015, Texas Instruments Incorporated
5
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = -40°C to
+140°C, (unless otherwise noted)
PARAMETER
HO GATE DRIVER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VHOL
Low level output voltage
IHO = 100 mA
0.18
0.25
0.4
IHO = -100 mA, VHOH = VHB
VHO
-
-
TJ = -40 to 125°C
TJ = -40 to 140°C
0.4
V
VHOH
High level output voltage
IHO = -100 mA, VHOH = VHB
VHO
0.25
0.42
Peak pull-up current
VHO = 0 V
3
3
A
Peak pull-down current
VHO = 12 V
6.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
PROPAGATION DELAYS
TJ = -40 to 125°C
TJ = -40 to 140°C
TJ = -40 to 125°C
TJ = -40 to 140°C
TJ = -40 to 125°C
TJ = -40 to 140°C
TJ = -40 to 125°C
TJ = -40 to 140°C
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
20
20
20
20
20
20
20
20
45
50
45
tDLFF
VLI falling to VLO falling
tDHFF VHI falling to VHO falling
tDLRR VLI rising to VLO rising
50
ns
45
50
45
50
tDHRR VHI rising to VHO rising
DELAY MATCHING
tMON
LI ON, HI OFF
1
1
7
ns
7
tMOFF LI OFF, HI ON
OUTPUT RISE AND FALL TIME
tR
tF
tR
tF
LO, HO
CLOAD = 1000 pF
CLOAD = 1000 pF
CLOAD = 0.1 μF
CLOAD = 0.1 μF
8
7
ns
LO, HO
LO, HO (3 V to 9 V)
LO, HO (3 V to 9 V)
0.35
0.3
0.6
us
0.6
MISCELLANEOUS
Minimum input pulse width that changes the output
Bootstrap diode turn-off time
50
20
ns
IF = 20 mA, IREV = 0.5 A(1) (2)
(1) Typical values for TA = 25°C
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
LI
Input
HI
(HI, LI)
TDLRR, TDHRR
LO
Output
(HO, LO)
TDLFF, TDHFF
HO
TMON
TMOFF
Figure 1. Timing Requirements
6
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
6.7 Typical Characteristics
10.0
10.0
150oC
25oC
150oC
125oC
125oC
1.0
1.0
-40oC
25oC
-40oC
0.1
0.1
10
100
Frequency - kHz
1000
10
100
1000
Frequency - kHz
VDD = 12 V
No Load on Outputs
HB = 12 V
No Load on Outputs
Figure 2. IDD Operating Current vs Frequency
Figure 3. Boot Voltage Operating Current
vs Frequency
1.0
2.0
1.8
Rising
0.1
150oC
Falling
1.6
1.4
25oC
0.01
1.2
1.0
125oC
-40oC
0.001
10
100
1000
8
10
12
14
16
18
20
Frequency - kHz
VDD - Supply Voltage - V
HB = 12 V
No Load on Outputs
T = 25°C
Figure 4. HB TO VSS Operating Current
vs Frequency
Figure 5. Input Threshold vs Supply Voltage
2.0
0.45
0.40
1.8
1.6
0.35
VDD = VHB = 16 V
Rising
0.30
VDD = VHB = 12 V
0.25
Falling
VDD = VHB = 8 V
0.20
1.4
0.15
0.10
1.2
1.0
0.05
VDD = VHB = 20 V
0.0
-50
-25
0
25
50
75
100 125 150
-50
-25
0
25
50
75
100 125 150
TA - Temperature - o
C
TA - Temperature - o
C
ILO = IHO = -100 mA
VDD = VHB = 16 V
VDD = 12 V
Figure 6. Input Threshold vs Temperature
Figure 7. LO and HO High Level Output Voltage
vs Temperature
Copyright © 2015, Texas Instruments Incorporated
7
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
Typical Characteristics (continued)
0.45
7.8
VDD = VHB = 16 V
0.40
7.6
7.4
0.35
VDD = VHB = 12 V
VDD Rising Threshold
0.30
0.25
0.20
0.15
0.10
7.2
7.0
VDD = VHB = 8 V
6.8
6.6
HB Rising Threshold
6.4
6.2
6.0
VDD = VHB = 20 V
0.05
0.0
5.8
-50
-25
0
25
50
75
100 125 150
-50
-25
0
25
50
75
100 125 150
TA - Temperature - o
C
TA - Temperature - o
C
ILO = IHO = 100 mA
Figure 9. Undervoltage Lockout Threshold
Figure 8. LO and HO Low Level Output Voltage
vs Temperature
vs Temperature
36
0.8
0.7
34
32
30
0.6
VDD UVLO Hysteresis
28
26
0.5
0.4
24
TDLFF
22
TDLRR
0.3
0.2
0.1
0
HB UVLO Hysteresis
20
18
TDHFF
16
TDHRR
14
-50
-25
0
25
50
75
100 125 150
TA - Temperature - o
C
-50
-25
0
25
50
75
100 125 150
TA - Temperature - o
C
VDD = VHB = 12 V
Figure 11. Propagation Delays vs Temperature
Figure 10. Undervoltage Lockout Threshold Hysteresis
vs Temperature
26
7
6
24
5
4
LI Falling
UCC27200TMOFF
22
LI Rising
3
2
UCC27201TMOFF
UCC27200TMON
UCC27201TMON
20
18
HI Rising
1
0
HI Falling
14
8
10
12
16
18
20
-50
-25
0
25
50
75
100 125 150
VDD = VHB - Supply Voltage - V
TA - Temperature - ?
C
T = 25°C
VDD = VHB = 12 V
Figure 12. Propagation Delay vs Supply Voltage
Figure 13. Delay Matching vs Temperature
8
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
Typical Characteristics (continued)
3.5
100.0
10.0
3.0
2.5
2.0
Pull-Down Current
Pull-Up Current
1.0
0.1
1.5
1.0
0.01
0.5
0
0.001
0
2
4
6
8
10
12
0.5
0.6
0.7
0.8
0.9
VLO, VHO - Output Voltage - V
Diode Voltage - V
VDD = VHB = 12 V
Figure 15. Diode Current vs Diode Voltage
Figure 14. Output Current vs Output Voltage
700
600
500
400
IHB
300
200
100
IDD
0
0
4
8
12
16
20
VDD, VHB - Supply Voltage - V
Inputs Low
T = 25°C
Figure 16. Quiescent Current vs Supply Voltage
Copyright © 2015, Texas Instruments Incorporated
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ZHCSDP7 –MAY 2015
www.ti.com.cn
7 Detailed Description
7.1 Overview
The UCC27201A-Q1 is a high-side/low-side driver. The high-side and low-side each have independent inputs
which allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver
bias supply is internal to the UCC27201A-Q1. The UCC27201-Q1 inputs are TTL-compatible. The high-side
driver is referenced to the switch node (HS) which is typically the source pin of the high side MOSFET and drain
pin of the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions
contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages.
7.2 Functional Block Diagram
2
HB
UVLO
3
4
HO
HS
LEVEL
SHIFT
5
1
HI
VDD
UVLO
LO
8
7
6
VSS
LI
7.3 Feature Description
7.3.1 Input Stages
The input stages provide the interface to the PWM output signals. The input stages of the UCC27201A-Q1
incorporate an open drain configuration to provide the lower input thresholds. The input impedance is 200 kΩ
nominal and input capacitance is approximately 4 pF. The 200 kΩ is a pull-down resistance to VSS (ground).
The logic level compatible input provides a rising threshold of 1.7 V and a falling threshold of 1.6 V.
7.3.1.1 UVLO (Under Voltage Lockout)
The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS
differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified
threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side
driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold
is 6.7 V with 0.4-V hysteresis.
7.3.1.2 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
10
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UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
Feature Description (continued)
7.3.1.3 Boot Diode
The boot diode necessary to generate the high-side bias is included in the UCC27201A-Q1 driver. The diode
anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the
HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot
diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and
reliable operation.
7.3.1.4 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.
7.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See UVLO (Under Voltage Lockout) for more information
on UVLO operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.
Table 1. Device Logic Table
HI PIN
LI PIN
HO(1)
LO(2)
L
L
L
H
L
L
L
L
H
L
H
H
H
H
H
H
(1) HO is measured with respect to HS.
(2) LO is measured with respect to VSS.
Copyright © 2015, Texas Instruments Incorporated
11
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
8.2 Typical Application
An open loop half-bridge converter was used to calculate performance in an actual application.
+
+
+
Figure 17. Open Loop Half-Bridge Converter
12
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
8.2.1 Design Requirements
Table 2. UCC27201A-Q1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Supply Voltage, VDD
Voltage on HS, VHS
Voltage on HB, VHB
Output
12 V
0 V to 100 V
12 V to 112 V
4 V, 20 A
Frequency
200 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Switching the MOSFETs
Achieving optimum drive performance at high frequency efficiently requires special attention to layout and
minimizing parasitic inductances. Care must be taken at the driver die and package level as well as the PCB
layout to reduce parasitic inductances as much as possible. Figure 18 shows the main parasitic inductance
elements and current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its
CGS capacitance.
L bond wire
L trace
L pin
VDD
1
8
7
Cvdd
I SOURCE
Rsource
L trace
L pin
L bond wire
Driver
Output
Stage
Rg
LO
Rsink
I sink
Cgs
L pin
Vss
L bond wire
L trace
L trace
Figure 18. MOSFET Drive Paths and Circuit Parasitics
Copyright © 2015, Texas Instruments Incorporated
13
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
The ISOURCE current charges the CGS gate capacitor and the ISINK current discharges it. The rise and fall time of
the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual
measurements, the analytical curves in Figure 19 and Figure 20 indicate the output voltage and current of the
drivers during the discharge of the load capacitor. Figure 19 shows voltage and current as a function of time.
Figure 20 indicates the relationship of voltage and current during fast switching. These figures demonstrate the
actual switching process and limitations due to parasitic inductances.
12
11
10
9
12
11
10
9
Voltage
Current
8
7
8
6
7
5
6
4
3
5
2
4
1
3
0
2
1
2
1
3
0
4
1
5
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
t (ns)
3
2
1
0
1
2
3
4
5
LO Current (A)
Figure 20. Turn-Off Voltage and Current Switching
Diagram
Figure 19. Turn-Off Voltage and Current vs Time
Turning off the MOSFET needs to be achieved as fast as possible to minimize switching losses. For this reason,
the UCC27201A-Q1 driver is designed for high peak currents and low output resistance. The sink capability is
specified as 0.18 V at 100-mA dc current implying 1.8-Ω RDS(on). With 12-V drive voltage, no parasitic inductance
and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side
drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current
waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver
MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately
3.3 A as shown in Figure 14. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The
internal parasitic inductance of the SOIC-8 package is estimated to be 2 nH including bond wires and leads.
14
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
Actual measured waveforms are shown in Figure 21 and Figure 22. As shown, the typical rise time of 8 ns and
fall time of 7 ns is conservatively rated.
UCC27200A
UCC27200A
Figure 21. VLO and VHO Rise Time, 1-nF Load, 5 ns/Div
Figure 22. VLO and VHO Fall Time, 1-nF Load, 5-ns/Div
8.2.2.2 Dynamic Switching of the MOSFETs
The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold
voltage. Using the turn off case as the example, when the gate to source threshold voltage is reached the drain
voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turn off
plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be
removed (Miller charge) makes good driver performance necessary for efficient switching. An open loop half
bridge power converter was utilized to evaluate performance in actual applications. The schematic of the half-
bridge converter is shown in Figure 17. The turn off waveforms of the UCC27201A-Q1 driving two MOSFETs in
parallel is shown in Figure 23 and Figure 24.
UCC27200A
UCC27200A
Figure 24. VHO Fall Time in Half-Bridge Converter
Figure 23. VLO Fall Time in Half-Bridge Converter
Copyright © 2015, Texas Instruments Incorporated
15
UCC27201A-Q1
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www.ti.com.cn
8.2.2.3 Delay Matching and Narrow Pulse Widths
The total delays encountered in the PWM, driver and power stage need to be considered for a number of
reasons, primarily delay in current limit response. Also to be considered are differences in delays between the
drivers which can lead to various concerns depending on the topology. The sync-buck topology switching
requires careful selection of dead-time between the high- and low-side switches to avoid 1) cross conduction and
2) excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the
transformer if there is imbalance in the high and low side pulse widths in a steady state condition.
Narrow pulse width performance is an important consideration when transient and short circuit conditions are
encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very
narrow pulses may be encountered in 1) soft start, 2) large load transients, and 3) short circuit conditions.
The UCC27201A-Q1 driver offers excellent performance regarding high and low-side driver delay matching and
narrow pulse width performance. The delay matching waveforms are shown in Figure 25 and Figure 26. The
UCC27201A-Q1 driver narrow pulse performance is shown in Figure 27 and Figure 28.
Figure 25. VLO and VHO Rising Edge Delay Matching
Figure 26. VLO and VHO Falling Edge Delay Matching
Figure 27. 20-ns Input Pulse Delay Matching
Figure 28. 10-ns Input Pulse Delay Matching
16
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
8.2.2.4 Boot Diode Performance
The UCC27201A-Q1 driver incorporates the bootstrap diode necessary to generate the high side bias internally.
The characteristics of this diode are important to achieve efficient, reliable operation. The dc characteristics to
consider are VF and dynamic resistance. A low VF and high dynamic resistance results in a high forward voltage
during charging of the bootstrap capacitor. The UCC27201A-Q1 has a boot diode rated at 0.65-V VF and
dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic characteristics to
consider are diode recovery time and stored charge. Diode recovery times that are specified with no conditions
can be misleading. Diode recovery times at no forward current (IF) can be noticeably less than with forward
current applied. The UCC27201A-Q1 boot diode recovery is specified at 20 ns at IF = 20 mA, IREV = 0.5 A. At 0
mA IF, the reverse recovery time is 15 ns.
Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every
switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to
charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the
voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC27201A-Q1 PN diode is
often less than a comparable Schottky diode.
8.2.3 Application Curves
UCC27200A
UCC27200A
Figure 30. VHO Fall Time in Half-Bridge Converter
Figure 29. VLO Fall Time in Half-Bridge Converter
Copyright © 2015, Texas Instruments Incorporated
17
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
9 Power Supply Recommendations
The bias supply voltage range for which the device is rated to operate is from 8 V to 17 V. The lower end of this
range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating).
Keeping a 3-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin
is 17 V. The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias
voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the
device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification
VDD(hys).Therefore, ensuring that, while operating at or near the 8-V range, the voltage ripple on the auxiliary
power supply output is smaller than the hysteresis specification of the device is important to avoid triggering
device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has
dropped below the V(OFF) threshold which must be accounted for while evaluating system shutdown timing
design requirements. Likewise, at system startup, the device does not begin operation until the VDD pin voltage
has exceeded above the V(ON) threshold. The quiescent current consumed by the internal circuit blocks of the
device is supplied through the VDD pin. Although this fact is well known, recognizing that the charge for source
current pulses delivered by the HO pin is also supplied through the same VDD pin is important. As a result, every
time a current is sourced out of the HO pin a corresponding current pulse is delivered into the device through the
VDD pin. Thus ensuring that a local bypass capacitor is provided between the VDD and GND pins and located
as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount
capacitor is a must. TI recommends using a capacitor in the range 0.22 uF to 4.7 uF between VDD and GND. In
a similar manner, the current pulses delivered by the LO pin are sourced from the HB pin. Therefore a 0.022-uF
to 0.1-uF local decoupling capacitor is recommended between the HB and HS pins.
18
Copyright © 2015, Texas Instruments Incorporated
UCC27201A-Q1
www.ti.com.cn
ZHCSDP7 –MAY 2015
10 Layout
10.1 Layout Guidelines
To improve the switching characteristics and efficiency of a design, the following layout rules should be followed.
•
•
•
Locate the driver as close as possible to the MOSFETs.
Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver.
Pay close attention to the GND trace. Use the thermal pad of the DDA package as GND by connecting it to
the VSS pin (GND). Note: The GND trace from the driver goes directly to the source of the MOSFET but
should not be in the high current path of the MOSFET(S) drain or source current.
•
•
Use similar rules for the HS node as for GND for the high side driver.
Use wide traces for LO and HO closely following the associated GND or HS traces. 60 mil to 100 mil width is
preferable where possible.
•
Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another.
For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic
inductance.
•
•
Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can
even lead to decreased reliability of the whole system.
10.2 Layout Example
Figure 31. Example Component Placement
版权 © 2015, Texas Instruments Incorporated
19
UCC27201A-Q1
ZHCSDP7 –MAY 2015
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
更多信息，请参见以下文档：
1. 《QFN/SON PCB 连接应用报告》（文献编号：SLUA271）
2. 《PowerPAD™ 散热增强型封装》（文献编号：SLMA002）
3. 《PowerPAD™ 速成》（文献编号：SLMA004）
11.2 商标
PowerPad is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
20
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC27201AQDDARQ1
UCC27201AQDMKRQ1
ACTIVE SO PowerPAD
DDA
DMK
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
201AQ1
ACTIVE
VSON
10
NIPDAU
UCC
27201AQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DMK0010A
VSON - 1 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
C
1 MAX
SEATING PLANE
0.08 C
(0.2) TYP
EXPOSED
THERMAL PAD
0.05
0.00
2.6±0.1
5
6
2X
3.2
3±0.1
8X 0.8
1
10
0.35
0.25
0.1
10X
0.5
0.3
10X
PIN 1 ID
(OPTIONAL)
C A
C
B
0.05
4222146/A 08/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMK0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.6)
10X (0.6)
SYMM
1
10
10X (0.3)
(1.25)
SYMM
(3)
8X (0.8)
6
5
(1.05)
(
0.2) VIA
TYP
(R0.05) TYP
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222146/A 08/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DMK0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
10X (0.6)
METAL
TYP
1
(0.68)
10
10X (0.3)
(0.76)
SYMM
8X (0.8)
4X
(1.31)
5
6
4X (1.15)
(R0.05) TYP
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4222146/A 08/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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