UCC27284 [TI]
具有 5V UVLO 和使能端的 3A、120V 半桥栅极驱动器;型号: | UCC27284 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 5V UVLO 和使能端的 3A、120V 半桥栅极驱动器 栅极驱动 驱动器 |
文件: | 总38页 (文件大小:2517K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
UCC27284 具有负电压处理能力和低开关损耗的
3A 120V 半桥驱动器
1 特性
3 说明
• 可驱动两个采用高侧/低侧配置的N 沟道MOSFET
• 5V 典型欠压锁定
• 在DRC 封装中启用/禁用功能
• 16ns 典型传播延迟
• 1.8nF 负载时的上升时间为12ns,下降时间为
10ns
• 1ns 典型延迟匹配
• 输入上的5V 负电压处理能力
• HS 上的14V 负电压处理能力
• ±3A 峰值输出电流
UCC27284 是一款功能强大的 N 沟道 MOSFET 驱动
器,最大开关节点 (HS) 额定电压为 100V。借助此器
件,可在基于半桥或同步降压配置的拓扑中控制两个 N
沟道 MOSFET。由于具有 3A 的峰值灌电流和拉电流
以及较低的上拉和下拉电阻, UCC27284 能够在
MOSFET 米勒平台转换期间以极低开关损耗驱动大功
率 MOSFET 。由于输入与电源电压无关, 因此
UCC27284 与模拟控制器和数字控制器均可结合使
用。在次级侧全桥同步整流等应用中,如需要,可实现
两路输入及其各自输出的重叠。
• 绝对最大启动电压为120V
• 禁用时消耗的电流很低(7µA)
• 集成式自举二极管
输入引脚和 HS 引脚能够承受较大的负电压,因此提高
了系统稳健性。启用和禁用功能通过降低栅极驱动器的
功耗并快速响应系统内的故障事件,提供额外的系统灵
活性。5V UVLO 允许系统在较低的偏置电压下工作,
这在许多高频应用中是必需的,并可在某些工作模式下
提高系统效率。较小的传播延迟和延迟匹配规格可尽可
能降低死区时间要求,从而进一步提高效率。
• 额定结温范围为–40°C 至140°C
2 应用
• 商用网络和服务器PSU
• 商用通信电源整流器
• 直流输入BLDC 电机驱动器
• 测试和测量设备
高侧和低侧驱动器级均配有欠压锁定(UVLO) 功能,因
此可在 VDD 电压低于指定阈值时强制将输出置为低电
平。在许多应用中,集成自举二极管无需使用外部分立
式二极管,节省布板空间和降低系统成本。UCC27284
采用小型封装,因此可支持高密度设计。
• 太阳能电源优化器
7V
75V
器件信息(1)
封装(标识符)(大小)
器件型号
SON10 (DRC) (3mm × 3mm)
VDD
HO
UCC27284
SON8 (DRM) (4mm × 4mm)
SON10 (DPR) (4mm × 4mm)
EN
NC
HI
HB
HS
To Load
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
LI
VSS
LO
简化版应用示意图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSE20
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 第三方产品免责声明................................................28
11.2 Receiving Notification of Documentation Updates..28
11.3 支持资源..................................................................28
11.4 Trademarks............................................................. 28
11.5 Electrostatic Discharge Caution..............................28
11.6 术语表..................................................................... 28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History B...........................................................2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Timing Diagrams.........................................................7
6.8 Typical Characteristics................................................7
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................13
Information.................................................................... 28
4 Revision History B
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2021) to Revision B (April 2022)
Page
• Updated typcal peak pullup/pulldown current from +2.5A/-3.5A to ±3A in Electrical Characteristics................. 5
• Updated IHBS typical leakage to 5.0μA and test voltage from 110V to 100V in Electrical Characteristics.........5
Changes from Revision * (March 2020) to Revision A (December 2021)
Page
• 将销售状态从“预告信息”更改为“初始发行版”.............................................................................................1
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
5 Pin Configuration and Functions
VDD
NC
HB
1
2
3
4
5
10
9
LO
VSS
LI
VDD
HB
1
2
3
4
8
7
6
5
LO
VSS
LI
Thermal
Pad
8
Thermal
Pad
HI
HO
HS
7
HO
HS
6
EN
HI
Not to scale
Not to scale
图5-1. DRC Package 10-Pin VSON With Exposed
图5-2. DRM Package 8-Pin SON Top View
Thermal Pad Top View
VDD
HB
1
2
3
4
5
10
LO
VSS
LI
9
8
7
6
Thermal
Pad
HO
HS
HI
NC
NC
Not to scale
图5-3. DPR Package 10-Pin SON Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
Name
DRC DRM DPR
Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low,
it disables the driver. A 1-nF filter capacitor is recommended for high-noise systems.
EN
6
3
I
—
—
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap
capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical
recommended value of HB bypass capacitor is 0.1 μF. This value primarily depends on the
gate charge of the high-side MOSFET. When using external boot diode, connect cathode of
the diode to this pin.
HB
2
2
P
HI
7
4
5
3
7
3
I
High-side input
High-side output. Connect to the gate of the high-side power MOSFET or one end of external
gate resistor, when used.
HO
O
High-side source connection. Connect to source of high-side power MOSFET. Connect
negative side of bootstrap capacitor to this pin.
HS
LI
5
8
4
6
4
8
P
I
Low-side input
Low-side output. Connect to the gate of the low-side power MOSFET or one end of external
gate resistor, when used.
LO
10
2
8
10
5,6
1
O
NC
VDD
VSS
n/a
1
Not connected internally
—
P
Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical decoupling
capacitor value is 1 μF. When using an external boot diode, connect the anode to this pin.
1
9
7
9
G
Negative supply terminal for the device which is generally the system ground
Thermal
pad
Connect to a large thermal mass trace (generally IC ground plane) to improve thermal
performance. This can only be electrically connected to VSS.
—
—
—
—
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
All voltages are with respect to Vss
MIN
–0.3
–5
MAX
20
UNIT
V
VDD
Supply voltage
VEN, VHI, VLI
Input voltages on EN, HI and LI
20
V
DC
VDD + 0.3
VDD + 0.3
VHB + 0.3
VHB + 0.3
100
–0.3
–2
VLO
VHO
VHS
Output voltage on LO
Output voltage on HO
Voltage on HS
V
V
V
Pulses andlt; 100 ns(3)
DC
VHS –0.3
VHS –2
–10
Pulses andlt; 100 ns(3)
DC
Pulses andlt; 100 ns(3)
100
–14
VHB
Voltage on HB
120
V
–0.3
–0.3
–40
VHB-HS
TJ
Voltage on HB with respect to HS
Operating junction temperature
Lead temperature (soldering, 10 s)
Storage temperature
20
V
150
°C
°C
°C
300
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
(3) Values are verified by characterization only.
6.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (3)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Pins HS, HB and HO are rated at 500V HBM
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5.5
NOM
MAX
16
UNIT
VDD
Supply voltage
12
V
VEN, VHI, VLI Input voltage
0
VDD
VDD
VHB
100
VLO
VHO
Low-side output voltage
0
High-side output voltage
Voltage on HS(1)
VHS
–8
VHS
V
Voltage on HS (pulses andlt; 100 ns)(1)
Voltage on HB
100
–12
VHS + 5.5
VHB
Vsr
TJ
VHS+16
50
V
Voltage slew rate on HS
Operating junction temperature
V/ns
°C
140
–40
(1) VHB-HS andlt; 16 V (Voltage on HB with respect to HS must be less than 16 V.)
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
6.4 Thermal Information
UCC27284
THERMAL METRIC(1)
DRC
DRM
DPR
UNIT
10 PINS 8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance
47.3
50.3
43.3
37.7
43.0
33.0
°C/W
°C/W
Rθ
Junction-to-case (top) thermal resistance
JC(top)
RθJB Junction-to-board thermal resistance
21.3
1.0
19.2
0.8
19.0
0.6
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJT
ψJB
21.2
19.2
19.0
Rθ
Junction-to-case (bottom) thermal resistance
4.4
6.3
6.2
°C/W
JC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report, SPRA953.
6.5 Electrical Characteristics
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +140°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY CURRENTS
IDD
VDD quiescent current
VDD operating current
VLI = VHI = 0
0.3
2.2
0.2
2.5
5.0
0.1
7.0
0.4
4.5
0.4
4
mA
mA
mA
mA
μA
mA
μA
IDDO
f = 500 kHz, CLOAD = 0
VLI = VHI = 0 V
IHB
HB quiescent current
IHBO
HB operating current
f = 500 kHz, CLOAD = 0
VHS = VHB = 100 V
f = 500 kHz, CLOAD = 0
VEN = 0
IHBS
HB to VSS quiescent current
HB to VSS operating current(1)
IDD when driver is disabled
50
IHBSO
IDD_DIS
INPUT
VHIT
Input rising threshold
Input falling threshold
Input voltage Hysteresis
Input pulldown resistance
1.9
0.9
2.1
1.1
1.0
250
2.4
1.3
V
V
VLIT
VIHYS
RIN
V
100
0.7
350
2.0
kΩ
ENABLE
VEN
Voltage threshold on EN pin to enable the driver
Voltage threshold on EN pin to disable the driver
Enable pin Hysteresis
1.54
1.21
0.3
V
V
VDIS
VENHYS
REN
V
EN pin internal Pulldown Resistor
250
kΩ
Time to enable the driver once the EN pin is
pulled high
TEN
VEN = 2 V
VEN = 0 V
18
μs
μs
Time to disable the driver once the EN pin is
pulled low
TDIS
1.5
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
VDDR
VDD rising threshold
4.7
4.2
5.0
4.5
0.5
3.7
3.3
0.3
5.4
4.9
V
V
V
V
V
V
VDDF
VDD falling threshold
VDDHYS
VHBR
VDD threshold hysteresis
HB rising threshold with respect to HS pin
HB falling threshold with respect to HS pin
HB threshold hysteresis
3.3
3.0
4.7
4.4
VHBF
VHBHYS
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
6.5 Electrical Characteristics (continued)
VDD = VHB = VEN =12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +140°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
BOOTSTRAP DIODE
VF
Low-current forward voltage
High-current forward voltage
Dynamic resistance, ΔVF/ΔI
0.65 0.85
V
V
Ω
IVDD-HB = 100 μA
VFI
RD
IVDD-HB = 80 mA
0.85
1.5
1.0
2.5
IVDD-HB = 100 mA and 80 mA
LO GATE DRIVER
VLOL
VLOH
Low level output voltage
ILO = 100 mA
0.085 0.4
0.13 0.42
3.0
V
V
A
A
High level output voltage
Peak pullup current (1)
Peak pulldown current (1)
ILO = –100 mA, VLOH = VDD –VLO
VLO = 0 V
VLO = 12 V
3.0
HO GATE DRIVER
VHOL
VHOH
Low level output voltage
IHO = 100 mA
0.1
0.4
V
V
A
A
High level output voltage
Peak pullup current (1)
Peak pulldown current (1)
0.12 0.42
IHO = –100 mA, VHOH = VHB –VHO
VHO = 0 V
3.0
3.0
VHO = 12 V
(1) Parameter not tested in production
6.6 Switching Characteristics
VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TJ = –40°C to +140°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PROPAGATION DELAYS
tDLFF
tDHFF
tDLRR
tDHRR
VLI falling to VLO falling
VHI falling to VHO falling
VLI rising to VLO rising
VHI rising to VHO rising
16
16
16
16
30
30
30
30
ns
ns
ns
ns
See 节6.7.
See 节6.7.
DELAY MATCHING
tMON
From LO being ON to HO being OFF
From LO being OFF to HO being ON
1
1
7
7
ns
ns
tMOFF
OUTPUT RISE AND FALL TIME
tR
tF
tR
tF
LO, HO rise time
CLOAD = 1800 pF, 10% to 90%
CLOAD = 1800 pF, 90% to 10%
CLOAD = 0.1 μF, 30% to 70%
CLOAD = 0.1 μF, 70% to 30%
12
10
ns
ns
LO, HO fall time
LO, HO (3 V to 9 V) rise time
LO, HO (3 V to 9 V) fall time
0.33
0.23
0.6
0.6
μs
μs
MISCELLANEOUS
TPW,min Minimum input pulse width that changes the output
Bootstrap diode turnoff time(1)
20
50
ns
ns
IF = 20 mA, IREV = 0.5 A
(1) Parameter not tested in production
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
6.7 Timing Diagrams
LI
HI
Input
(HI, LI)
LO
TDLRR, TDHRR
Output
(HO, LO)
HO
TDLFF
,
TDHFF
Time (s)
Time (s)
TMOFF
TMON
6.8 Typical Characteristics
Unless otherwise specified VVDD=VHB = 12 V, VHS=VVSS = 0 V, No load on outputs
0.3
0.28
0.26
0.24
0.22
0.2
0.22
0.18
0.14
0.1
0.18
0.16
0.14
0.12
0.1
0.06
5.5V
12V
16V
5.5V
12V
16V
0.02
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
IDDQ
IHBQ
A.
VHI = VLI = 0 V
A.
VHI = VLI = 0 V
图6-1. VDD Quiescent Current
图6-2. HB Quiescent Current
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
6
4.5
4
-40°C
25°°C
140°°C
-40°C
25°C
140°C
5
4
3
2
1
0
3.5
3
2.5
2
1.5
1
0.5
0
1
2
3 4 5 67 10
20 30 50 70100 200
Frequency (kHz)
500 1000
1
2
3 4 567 10
20 30 50 70100 200
Frequency (kHz)
500 1000
IDDO
IHBO
A.
CL = 0 F
VDD =VHB= 12V
A.
CL = 0 F
VDD =VHB= 12V
图6-3. VDD Operating Current
图6-4. HB Operating Current
14
12
10
8
20
18
16
14
12
10
8
5.5V
12V
16V
6
6
4
4
2
2
0
0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
IDD_
IHBS
A.
VHB=VHS=100V
A.
CL = 0 F
VEN = 0 V
图6-6. HB to VSS Quiescent Current
图6-5. VDD Current When Disabled
2.22
2.215
2.21
1.145
1.14
1.135
1.13
2.205
2.2
2.195
2.19
1.125
1.12
2.185
2.18
1.115
1.11
2.175
2.17
5.5V
12V
16V
5.5V
12V
16V
2.165
1.105
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
IN_R
IN_F
图6-7. Input Rising Threshold
图6-8. Input Falling Threshold
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
280
1.75
1.7
5.5V
12V
16V
1.65
1.6
270
260
250
240
1.55
1.5
1.45
1.4
1.35
1.3
1.25
1.2
-40
230
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20
0
20
40 60
Temperature (°C)
80
100 120 140
EN_T
R_IN
图6-10. Enable Threshold
图6-9. Input Pulldown Resistor
1.35
1.3
70
65
60
55
50
45
40
35
30
25
20
15
5.5V
12V
16V
5.5V
12V
16V
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Dis_
T_EN
图6-11. Disable Threshold
图6-12. Enable Delay
2.2
2.15
2.1
5.2
5
5.5V
12V
16V
2.05
2
4.8
4.6
4.4
4.2
1.95
1.9
1.85
1.8
1.75
1.7
Rise
Fall
1.65
1.6
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
T_Di
VDDU
图6-13. Disable Delay
图6-14. VDD UVLO Threshold
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
4
3.8
3.6
3.4
3.2
1
0.95
0.9
100uA
80mA
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
Rise
Fall
0.25
3
-40
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Vf
HBUV
图6-16. Boot Diode Forward Voltage Drop
图6-15. HB UVLO Threshold
1.8
0.135
0.13
1.75
1.7
0.125
0.12
1.65
1.6
0.115
0.11
1.55
1.5
0.105
0.1
0.095
0.09
1.45
1.4
0.085
1.35
1.3
0.08
0.075
0.07
5.5V
12V
16V
1.25
0.065
1.2
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
V_LO
R_Dy
IO=100mA
图6-17. Boot Diode Dynamic Resistance
图6-18. LO Low Output Voltage (VLOL
)
0.21
0.155
0.15
0.145
0.14
0.2
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
0.135
0.13
0.125
0.12
0.115
0.11
0.105
0.1
5.5V
12V
16V
5.5V
12V
16V
0.095
0.09
0.085
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
UV_CHCO2
V_LO
IO=100mA
IO=-100mA
图6-20. HO Low Output Voltage (VHOL
)
图6-19. LO High Output Voltage (VLOH
)
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
15
14.5
14
5.5V
12V
16V
13.5
13
12.5
12
11.5
11
10.5
10
5.5V
12V
16V
0.09
-40
9.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20
0
20
40 60
Temperature (°C)
80
100 120 140
V_HO
LO_R
IO=-100mA
CL=1800pF
图6-21. HO High Output Voltage (VHOH
)
图6-22. LO Rise Time
10.2
18
15
12
9
5.5V
12V
16V
5.5V
12V
16V
10
9.8
9.6
9.4
9.2
9
8.8
8.6
8.4
8.2
8
6
-40
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20
0
20
40 60
Temperature (°C)
80
100 120 140
LO_F
HO_R
CL=1800pF
CL=1800pF
图6-23. LO Fall Time
图6-24. HO Rise Time
9
8.8
8.6
8.4
8.2
8
0.4
5.5V
12V
16V
0.38
0.36
0.34
0.32
0.3
0.28
0.26
0.24
0.22
0.2
7.8
7.6
7.4
7.2
Rise
Fall
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
LO_R
HO_F
CL=100nF
CL=1800pF
图6-26. LO Rise andamp; Fall Time
图6-25. HO Fall Time
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
0.45
0.425
0.4
20
19.5
19
0.375
0.35
0.325
0.3
18.5
18
17.5
17
0.275
0.25
0.225
0.2
16.5
16
15.5
15
5.5V
12V
16V
Rise
Fall
0.175
14.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
HO_R
TDHR
CL=100nF
CL=No Load
图6-27. HO Rise andamp; Fall Time
图6-28. HO Rising Propagation Delay (TDHRR)
20.5
20
20
19.5
19
19.5
19
18.5
18
18.5
18
17.5
17
17.5
17
16.5
16
16.5
15.5
15
16
5.5V
12V
16V
5.5V
12V
16V
15.5
15
14.5
14
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
TDHF
TDLR
CL= No Load
CL= No Load
图6-29. HO Falling Propagation Delay (TDHFF)
图6-30. LO Rising Propagation Delay (TDLRR)
19
18.5
18
17.5
17
16.5
16
15.5
15
5.5V
12V
16V
14.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
TDLF
CL= No Load
图6-31. LO Falling Propagation Delay (TDLFF)
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
The UCC27284 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel
FETs in a synchronous buck or a half-bridge configuration. The two outputs are independently controlled with
two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long
as signals meet turn-on and turn-off threshold specifications of the UCC27284. The floating high-side driver is
capable of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated in the
UCC27284 device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high
speed while consuming low power and provides clean level transitions from the control logic to the high-side
gate driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin
is provided (in DRC packaged parts) to enable or disable the driver.
7.2 Functional Block Diagram
HB
UVLO
DRIVER
STAGE
HO
LEVEL
SHIFT
HS
HI
VDD
UVLO
EN
DRIVER
LO
STAGE
VSS
LI
Copyright © 2020, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Enable
The device in DRC package has an enable (EN) pin. The outputs will be active only if the EN pin voltage is
above the threshold voltage. Outputs will be held low if EN pin is left floating or pulled-down to ground. An
internal 250 kΩ resistor connects EN pin to VSS pin. Thus, leaving the EN pin floating disables the device.
Externally pulling EN pin to ground shall also disable the device. If the EN pin is not used, then it is
recommended to connect it to VDD pin. If a pullup resistor needs to be used then a strong pullup resistor is
recommended. For 12V supply voltage, a 10kΩ pull-up is suggested. In noise prone application, a small filter
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
capacitor, 1nF, should be connected from the EN pin to VSS pin as close to the device as possible. An analog or
a digital controller output pin could be connected to EN pin to enable or disable the device. Built-in hysteresis
helps prevent any nuisance tripping or chattering of the outputs.
7.3.2 Start-Up and UVLO
The high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply voltage
(VDD) and the bootstrap capacitor voltage (VHB–HS). The UVLO circuit inhibits each output until sufficient supply
voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chattering during
supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both the outputs are
held low until VDD exceeds the UVLO threshold, typically 5 V. Any UVLO condition on the bootstrap capacitor
(VHB–HS) disables only the high-side output (HO).
表7-1. VDD UVLO Logic Operation
Condition (VHB-HS andgt; VHBR and VEN andgt; Enable Threshold)
HI
H
L
LI
L
HO
L
LO
L
H
H
L
L
L
VDD-VSS andlt; VDDR during device start-up
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
VDD–VSS andlt; VDDR –VDDH after device start-up
H
L
L
L
L
L
表7-2. HB UVLO Logic Operation
Condition (VDD andgt; VDDR and VEN andgt; Enable Threshold)
HI
H
L
LI
L
HO
L
LO
L
H
H
L
L
H
H
L
VHB-HS andlt; VHBR during device start-up
H
L
L
L
H
L
L
L
L
H
H
L
L
H
H
L
VHB-HS andlt; VHBR –VHBH after device start-up
H
L
L
L
7.3.3 Input Stage
The two inputs operate independent of each other and also independent of VDD. The independence allows for
full control of two outputs compared to the gate drivers that have a single input. The overlap of inputs and
therefore respective outputs allow the use in applications such as secondary side synchronous rectification.
Whenever both the inputs are high, both the outputs shall be high as well. In other words, the outputs follow the
input logic in all operating conditions except when the driver is disabled or when the driver is in UVLO mode.
There is no fixed time de-glitch filter implemented in the device and therefore propagation delay and delay
matching are not sacrificed. In other words, there is no built-in dead-time feature. Because the inputs are
independent of supply voltage, they can be connected to outputs of either digital controller or analog controller.
Inputs can accept wide slew rate signals and input can withstand negative voltage to increase the robustness.
Small filter at the inputs of the driver further improves system robustness in noise prone applications. The inputs
have internal pulldown resistors with typical value of 250 kΩ. Thus, when the inputs are floating, the outputs are
held low.
7.3.4 Level Shifter
The level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-side
driver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO output
which is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible and
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
therefore the device provides excellent propagation delay characteristic and delay matching with the low-side
driver output. Low delay matching allows power stages to operate with less dead time. The reduction in dead-
time is very important in applications where high efficiency is required.
7.3.5 Output Stage
The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew
rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power
MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The device
output stages are robust to handle harsh environment, such as –2 V transient for 100 ns. The device can also
sustain positive transients on the outputs. The device output stages feature a pull-up structure which delivers the
highest peak source current when it is most needed, during the Miller plateau region of the power switch turn on
transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS structure.
7.3.6 Negative Voltage Transients
In most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground. In
some situations, board capacitance and inductance can cause the HS node to transiently swing several volts
below ground, before the body diode of the external low-side MOSFET clamps this swing. When used in
conjunction with the UCC27284, the HS node can swing below ground as long as specifications are not violated
and conditions mentioned in this section are followed.
HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions can
activate parasitic transistors which may result in excessive current flow from the HB supply. This may result in
damage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be
placed externally between HO and HS or LO and VSS to protect the device from this type of transient. The diode
must be placed as close to the device pins as possible in order to be effective.
Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V, then
VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally, when HS
swings negative, HB follows HS instantaneously and therefore the HB to HS voltage does not significantly
overshoot.
Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation of the gate
driver device. The capacitor should be located at the leads of the device to minimize series inductance. The
peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor causes
voltage ringing at the leads of the device which must be avoided for reliable operation.
Based on application board design and other operating parameters, along with HS pin, other pins such as
inputs, HI and LI, might also transiently swing below ground. To accommodate such operating conditions
UCC27284 input pins are capable of handling absolute maximum of -5V. As explained earlier, based on the
layout and other design constraints, sometimes the outputs, HO and LO, might also see transient voltages for
short durations. Therefore, UCC27284 gate drivers can also handle -2 V 100 ns transients on output pins, HO
and LO.
7.4 Device Functional Modes
When the device is enabled, the device operates in normal mode and UVLO mode. See 节 7.3.2 for more
information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold,
the output stage is dependent on the states of the EN, HI and LI pins. The output HO and LO will be low if input
state is floating.
表7-3. Input/Output Logic in Normal Mode of Operation
EN
HI
H
L
LI
H
H
L
HO (1)
LO (2)
L
L
L
L
L
L
L
L
L
H
L
L
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
表7-3. Input/Output Logic in Normal Mode of Operation (continued)
EN
HI
LI
HO (1)
LO (2)
H
H
H
L
H
L
L
L
L
H
L
H
H
L
L
L
H
L
L
L
L
H
H
H
L
L
L
Floating
Floating
L
L
H
H
Floating
Floating
Floating
H
Floating
Floating
(1) HO is measured with respect to HS
(2) LO is measured with respect to VSS
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
Most electronic devices and applications are becoming more and more power hungry. These applications are
also reducing in overall size. One way to achieve both high power and low size is to improve the efficiency and
distribute the power loss optimally. Most of these applications employ power MOSFETs and they are being
switched at higher and higher frequencies. To operate power MOSFETs at high switching frequencies and to
reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller
and the gates of the power semiconductor devices, such as power MOSFETs, IGBTs, SiC FETs, and GaN FETs.
Many of these applications require proper UVLO protection so that power semiconductor devices are turned ON
and OFF optimally. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly
drive the gates of the switching devices. With the advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a
power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V or 5
V) in order to fully turn-on the power device, minimize conduction losses, and minimize the switching losses.
Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove
inadequate with digital power because they lack level-shifting capability and undervoltage lockout protection.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also solve other
problems such as minimizing the effect of high-frequency switching noise (by placing the high-current driver
device physically close to the power switch), driving gate-drive transformers and controlling floating power device
gates. This helps reduce power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller IC to the gate driver.
UCC27284 gate drivers offer high voltage (100 V), small delays (16 ns), and good driving capability (±3 A) in a
single device. The floating high-side driver is capable of operating with switch node voltages up to 100 V. This
allows for N-channel MOSFETs control in half-bridge, full-bridge, synchronous buck, synchronous boost, and
active clamp topologies. UCC27284 gate driver IC also has built-in bootstrap diode to help power supply
designers optimize PWB area and to help reduce bill of material cost in most applications. The driver has an
enable/disable functionality to be used in applications where driver needs to be enabled or disabled based on
fault condition in other parts of the circuit. Each channel is controlled by its respective input pins (HI and LI),
allowing flexibility to control ON and OFF state of the output.
Switching power devices such as MOSFETs have two main loss components; switching losses and conduction
losses. Conduction loss is dominated by current through the device and ON resistance of the device. Switching
losses are dominated by gate charge of the switching device, gate voltage of the switching device, and switching
frequency. Applications where operating switching frequency is very high, the switching losses start to
significantly impact overall system efficiency. In such applications, to reduce the switching losses it becomes
essential to reduce the gate voltage. The gate voltage is determined by the supply voltage the gate driver ICs,
therefore, the gate driver IC needs to operate at lower supply voltage in such applications. UCC27284 gate
driver has typical UVLO level of 5V and therefore, they are perfectly suitable for such applications. There is
enough UVLO hysteresis provided to avoid any chattering or nuisance tripping which improves system
robustness.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
8.2 Typical Application
7 V
75 V
EN
VDD
SECONDARY
SIDE
CIRCUIT
HB
HO
HI
DRIVE
HI
HS
LO
PWM
CONTROLLER
LI
DRIVE
LO
UCC27284
ISOLATION
AND
FEEDBACK
Copyright © 2018, Texas Instruments Incorporated
图8-1. Typical Application
8.2.1 Design Requirements
Table below lists the system parameters. UCC27284 needs to operate satisfactorily in conjunction with them.
表8-1. Design Requirements
Parameter
MOSFET
Value
CSD19535KTT
75V
Maximum Bus/Input Voltage, Vin
Operating Bias Voltage, VDD
Switching Frequency, Fsw
Total Gate Charge of FET at given VDD, QG
MOSFET Internal Gate Resistance, RGFET_Int
Maximum Duty Cycle, DMax
Gate Driver
7V
300kHz
52nC
1.4
0.5
UCC27284
8.2.2 Detailed Design Procedure
8.2.2.1 Select Bootstrap and VDD Capacitor
The bootstrap capacitor must maintain the VHB-HS voltage above the UVLO threshold for normal operation.
Calculate the maximum allowable drop across the bootstrap capacitor, ΔVHB, with 方程式1.
¿VHB = VDD F VDH F VHBL
:
;
= 7 V ꢀ 1 V ꢀ (4.4 V ꢀ 0.37 V) = 1.97 V
(1)
where
• VDD is the supply voltage of gate driver device
• VDH is the bootstrap diode forward voltage drop
• VHBL is the HB falling threshold (VHBR(max) –VHBH
)
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
In this example the allowed voltage drop across bootstrap capacitor is 1.97 V.
It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be
minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of
0.5 V.
Use 方程式2 to estimate the total charge needed per switching cycle from bootstrap capacitor.
DMAX
fSW
IHB
fSW
QTOTAL = QG + IHBS × l
p + l
p
= 52 nC + 0.083 nC + 1.33 nC = 53.41 nC
(2)
where
• QG is the total MOSFET gate charge
• IHBS is the HB to VSS leakage current from datasheet
• DMax is the converter maximum duty cycle
• IHB is the HB quiescent current from the datasheet
The caculated total charge is 53.41 nC.
Next, use 方程式3 to estimate the minimum bootstrap capacitor value.
QTOTAL
53.41 nC
1.97 V
CBOOT min
=
;
=
= 27.11 nF
:
¿VHB
(3)
The calculated value of minimum bootstrap capacitor is 27.11 nF. It should be noted that, this value of
capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than
calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.
It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include
enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small
size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.
For this application, choose a CBOOT capacitor that has the following specifications: 0.1 µF, 25 V, X7R
As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value
(generally 10 times the bootstrap capacitor value). For this application choose a CVDD capacitor with the
following specifications: 1 µF , 25 V, X7R
CVDD capacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a
small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,
1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.
The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a
voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most
ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of
the system.
8.2.2.2 Estimate Driver Power Losses
The total power loss in gate driver device such as the UCC27284 is the summation of the power loss in different
functional blocks of the gate driver device. These power loss components are explained in this section.
1. 方程式4 describes how quiescent currents (IDD and IHB) affect the static power losses, PQC
.
:
;
:
;
PQC = VDD × IDD + VDD F VDH × IHB
= 7 V × 0.4 mA + 6 V × 0.4 mA = 5.2 mW
(4)
it is not shown here, but for better approximation, add no load operating current, IDDO and IHBO in above
equation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
2. 方程式5 shows how high-side to low-side leakage current (IHBS) affects level-shifter losses (PIHBS).
P
IHBS
= VHB × IHBS × D = 82 V × 50 µA × 0.5 = 2.05 mW
(5)
where
• D is the high-side MOSFET duty cycle
• VHB is the sum of input voltage and voltage across bootstrap capacitor.
3. 方程式6 shows how MOSFETs gate charge (QG) affects the dynamic losses, PQG
.
RGD _R
PQG = 2 × VDD × QG × fSW
×
RGD _R+ RGATE + RGFET int
:
;
= 2 × 7 V × 52 nC × 300 kHz × 0.74 = 0.16 W
(6)
where
• QG is the total MOSFET gate charge
• fSW is the switching frequency
• RGD_R is the average value of pullup and pulldown resistor
• RGATE is the external gate drive resistor
• RGFET(int) is the power MOSFETs internal gate resistor
Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull
down resistance of the driver output section is approximately 4 Ω. Substitute the application values to
calculate the dynamic loss due to gate charge, which is 160 mW here.
4. 方程式7 shows how parasitic level-shifter charge (QP) on each switching cycle affects dynamic losses, (PLS)
during high-side switching.
P = VHB × QP × fSW
LS
(7)
For this example and simplicity, it is assumed that value of parasitic charge QP is 1 nC. Substituting values
results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.
The sum of all the losses is 191.85 mW as a total gate driver loss. As shown in this example, in most
applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate
drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward
conduction loss is computed as product of average forward voltage drop and average forward current.
方程式8 estimates the maximum allowable power loss of the device for a given ambient temperature.
kT F TAo
J
PMAX
=
REJA
(8)
where
• PMAX is the maximum allowed power dissipation in the gate driver device
• TJ is the recommended maximum operating junction temperature
• TA is the ambient temperature of the gate driver device
• RθJA is the junction-to-ambient thermal resistance
To better estimate the junction temperature of the gate driver device in the application, it is recommended to first
accurately measure the case temperature and then determine the power dissipation in a given application. Then
use ψJT to calculate junction temperature. After estimating junction temperature and measuring ambient
temperature in the application, calculate θJA(effective). Then, if design parameters (such as the value of an
external gate resistor or power MOSFET) change during the development of the project, use θJA(effective) to
estimate how these changes affect junction temperature of the gate driver device.
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
For detailed information regarding the thermal information table, please refer to the Semiconductor and Device
Package Thermal Metrics application report.
8.2.2.3 Selecting External Gate Resistor
In high-frequency switching power supply applications where high-current gate drivers such as the UCC27284
are used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing on
the gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some
applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak
output current capability. In such applications external gate resistors can limit the peak output current of the gate
driver. it is recommended that there should be provision of external gate resistor whenever the layout or
application permits.
Use 方程式9 to calculate the driver high-side pull-up current.
VDD F VDH
RHOH + RGATE+ RGFET int
IOHH
=
:
;
(9)
where
• IOHH is the high-side, peak pull-up current
• VDH is the bootstrap diode forward voltage drop
• RHOH is the gate driver internal high-side pullup resistor. Value either directly provided in datasheet or can be
calculated from test conditions (RHOH = VHOH/IHO
)
• RGATE is the external gate resistance connected between driver output and power MOSFET gate
• RGFET(int) is the MOSFET internal gate resistance provided by MOSFET data sheet.
Use 方程式10 to calculate the driver high-side sink current.
VDD F VDH
RHOL + RGATE+ RGFET int
IOLH
=
:
;
(10)
(11)
(12)
where
• RHOL is the gate driver internal high-side pulldown resistance
Use 方程式11 to calculate the driver low-side source current.
VDD
IOHL
=
RLOH + RGATE+ RGFET int
:
;
where
• RLOH is the gate driver internal low-side pullpullup resistance
Use 方程式12 to calculate the driver low-side sink current.
VDD
IOLL
=
RLOL + RGATE+ RGFET int
:
;
where
• RLOL is the gate driver internal low-side pulldown resistance
Both high and low-side channels of the gate driver have a peak current rating of ±3 A. These equations help
reduce the peak current if needed. To establish different rise time value compared to fall time value, external
gate resistor can be anti-paralleled with diode-resistor combination as shown in 节 8.2. Generally selecting an
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
optimal value or configuration of external gate resistor is an iterative process. For additional information on
selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers.
8.2.2.4 Delays and Pulse Width
The total delay encountered in the PWM, driver and power stage need to be considered for a number of
reasons, primarily delay in current limit response. Also to be considered are differences in delays between the
drivers which can lead to various concerns depending on the topology. The synchronous buck topology
switching requires careful selection of dead-time between the high-side and low-side switches to avoid cross
conduction as well as excessive body diode conduction.
Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the
high-side and low-side pulse widths in any operating condition. The UCC27284 device has maximum
propagation delay, across process, and temperature variation, of 30 ns and delay matching of 7 ns, which is one
of the best in the industry.
Narrow input pulse width performance is an important consideration in gate driver devices, because output may
not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively
wide steady state PWM output signals from controller, very narrow pulses may be encountered under following
operating conditions.
• soft-start period
• large load transients
• short circuit conditions
These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to
respond properly to these narrow signals.
图 8-2 shows that the UCC27284 device produces reliable output pulse even when the input pulses are very
narrow and bias voltages are very low. The propagation delay and delay matching do not get affected when the
input pulse width is very narrow.
HI (2V/div)
BW=1GHz
LI (2V/div)
BW=1GHz
LO (5V/div)
BW=1GHz
HO (5V/div)
BW=1GHz
图8-2. Input and Output Pulse Width
8.2.2.5 External Bootstrap Diode
The UCC27284 incorporates the bootstrap diode necessary to generate the high-side bias for HO to work
satisfactorily. The characteristics of this diode are important to achieve efficient, reliable operation. The
characteristics to consider are forward voltage drop and dynamic resistance. Generally, low forward voltage drop
diodes are preferred for low power loss during charging of the bootstrap capacitor. The device has a boot diode
forward voltage drop rated at 0.85 V and dynamic resistance of 1.5 Ω for reliable charge transfer to the
bootstrap capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode
recovery times that are specified without operating conditions, can be misleading. Diode recovery times at no
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
forward current (IF) can be noticeably less than with forward current applied. The UCC27284 boot diode
recovery is specified as 50 ns at IF = 20 mA, IREV = 0.5 A. Dynamic impedance of UCC27284 bootstrap diode
naturally limits the peak forward current and prevents any damage if repetitive peak forward current pulses exist
in the system for most applications.
In applications where switching frequencies are very high, for example in excess of 1 MHz, and the low-side
minimum pulse widths are very small, the diode peak forward current could be very high and peak reverse
current could also be very high, specifically if high bootstrap capacitor value has been chosen. In such
applications it might be advisable to use external Schottkey diode as bootstrap diode. It is safe to at least make
a provision for such diode on the board if possible.
8.2.2.6 VDD and Input Filter
Some switching power supply applications are extremely noisy. Noise may come from ground bouncing and
ringing at the inputs, (which are the HI and LI pins of the gate driver device). To mitigate such situations, the
UCC27284 offers both negative input voltage handling capability and wide input threshold hysteresis. If these
features are not enough, then the application might need an input filter. Small filter such as 10-Ω resistor and
47-pF capacitor might be sufficient to filter noise at the inputs of the gate driver device. This RC filter would
introduce delay and therefore need to be considered carefully. High frequency noise on bias supply can cause
problems in performance of the gate driver device. To filter this noise it is recommended to use 1-Ω resistor in
series with bias supply as shown in 图 8-1. This resistor also acts as a current limiting element. In the event of
short circuit on the bias rail, this resistor opens up and prevents further damage. This resistor can also be helpful
in debugging the design during development phase.
8.2.2.7 Transient Protection
As mentioned in previous sections, high power high switching frequency power supplies are inherently noisy.
High dV/dt and dI/dt in the circuit can cause negative voltage on different pins such as HO, LO, and HS. The
device tolerates negative voltage on all of these pins as mentioned in specification tables. If parasitic elements of
the circuit cause very large negative swings, circuit might require additional protection. In such cases fast acting
and low leakage type Schottky diode should be used. This diode must be placed as close to the gate driver
device pin as possible for it to be effective in clamping excessive negative voltage on the gate driver device pin.
To avoid the possibility of driver device damage due to over-voltage on its output pins or supply pins, low
leakage Zener diode can be used. A 15-V Zener diode is often sufficient to clamp the voltage below the
maximum recommended value of 16 V.
8.2.3 Application Curves
To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be as
fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the UCC27284
is designed with high drive current capability and low resistance of the output stages. One of the common way to
test the drive capability of the gate driver device , is to test it under heavy load. Rise time and fall time of the
outputs would provide idea of drive capability of the gate driver device. There must not be any resistance in this
test circuit. 图 8-3 and 图 8-4 shows rise time and fall time of HO respectively of UCC27284. 图 8-5 and 图 8-6
shows rise time and fall time of LO respectively of UCC27284. For accuracy purpose, the VDD and HB pin of the
gate driver device were connected together. HS and VSS pins are also connected together for this test.
Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This
method is also useful in comparing performance of two or more gate driver devices.
As explained in 节8.2.2.4, propagation delay plays an important role in reliable operation of many applications.
图8-8 shows propagation delay and delay matching of UCC27284. 图8-9 shows input negative voltage handling
capability of UCC27284.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
VDD = VHB = 6 V, HS =
VSS
CLOAD = 10 nF
Ch4 = HO
VDD = VHB=6 V, HS =
VSS
CLOAD = 10
nF
Ch4 = HO
图8-3. HO Rise Time
图8-4. HO Fall Time
A.
VDD = VHB = 6 V, HS = VSS
CLOAD = 10 nF Ch4 = LO
A.
VDD = VHB = 6 V, HS =
VSS
CLOAD = 10 nF Ch4 = LO
图8-5. LO Rise Time
图8-6. LO Fall Time
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
A.
VDD = 6 V
CLOAD = 2
nF
Ch1 = HI Ch2 = LI Ch3 = HO Ch4
= LO
A.
VDD = 6 V CLOAD = 2 nF Ch1 = HI Ch2 = LI Ch3 = HO Ch4
= LO
图8-7. Propagation Delay and Delay Matching
图8-8. Propagation Delay and Delay Matching
A.
VDD = 10 V Vin = 100 V
CL = 1 nF
Ch1 = HI Ch2 = LI Ch3 = HO Ch4 = LO
图8-9. Input Negative Voltage
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
9 Power Supply Recommendations
The recommended bias supply voltage range for UCC27284 is from 5.5 V to 16 V. The lower end of this range is
governed by the internal undervoltage-lockout (UVLO) protection feature, 5 V typical, of the VDD supply circuit
block. The upper end of this range is driven by the 16-V recommended maximum voltage rating of the VDD. It is
recommended that voltage on VDD pin should be lower than maximum recommended voltage. In some transient
condition it is not possible to keep this voltage below recommended maximum level and therefore absolute
maximum voltage rating of the UCC27284 is 20 V.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDHYS. If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 5.5-V range, the voltage ripple on
the auxiliary power supply output should be smaller than the hysteresis specification of UCC27284 to avoid
triggering device shutdown.
A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as
close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is
recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor
for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surface-
mount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin
are sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value
small size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO
pulses.
UCC27284 has enable and disable functionality through the EN pin. Therefore, signal at the EN pin should be as
clean as possible. If EN pin is not used, then it is recommended to connect the pin to VDD pin. If EN pin is pulled
up through a resistor, then the pullup resistor needs to be strong. In noise prone applications, it is recommended
to filter the EN pin with small capacitor, such as X7R 0402 1 nF.
In power supplies where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is
recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the
design. In such applications. it is also recommended to have a place holder for power MOSFET external gate
resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which
impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is
recommended to use a resistor in series with the diode, which provides further control of fall time.
In power supply applications such as motor drives, there exist lot of transients through-out the system. This
sometime causes over voltage and undervoltage spikes on almost all pins of the gate driver device. To increase
the robustness of the design, it is recommended that the clamp diode should be used on HO and LO pins. If user
does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which
needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these
diodes across the temperature needs to be minimal.
In power supply applications where it is almost certain that there is excessive negative HS voltage, it is
recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit
current into the driver device up to some extent. This resistor will impact the high side drive capability and
therefore needs to be considered carefully.
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed
wiring board (PWB) layout guidelines.
• Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between
HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the
external MOSFETs.
• To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).
• In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the
source of the high-side MOSFET and the source of the low-side MOSFET (synchronous rectifier) must be
minimized.
• Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling
of switching noise into the ground plane is minimized.
• Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the
device. Generally it is connected to the ground plane which is the same as VSS of the device. It is
recommended to connect this pad to the VSS pin only.
• Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance
and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the
MOSFETs as possible.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
10.2 Layout Example
HB Bypass
Capacitor (Top)
Gate Driver
(Top)
External Gate
Resistor (Top)
Input Filters
(Top)
Boot Diode
(Bottom)
VDD Bypass
Capacitors (Top)
External Gate
Resistor (Bottom)
图10-1. Layout Example
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: UCC27284
UCC27284
ZHCSL21B –MARCH 2020 –REVISED APRIL 2022
www.ti.com.cn
11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: UCC27284
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PUCC27284DRCT
UCC27284DRCR
UCC27284DRCT
UCC27284DRMR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRM
10
10
10
8
250
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Samples
Samples
Samples
Samples
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
U284
U284
U284
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27284 :
Automotive : UCC27284-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27284DRCR
UCC27284DRCT
UCC27284DRMR
VSON
VSON
VSON
DRC
DRC
DRM
10
10
8
3000
250
330.0
180.0
330.0
12.4
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
3000
4.25
4.25
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC27284DRCR
UCC27284DRCT
UCC27284DRMR
VSON
VSON
VSON
DRC
DRC
DRM
10
10
8
3000
250
367.0
210.0
367.0
367.0
185.0
367.0
35.0
35.0
35.0
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
UCC27284-Q1
具有 5V UVLO 的汽车类 3A、120V 半桥栅极驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27284DRCR
具有 5V UVLO 和使能端的 3A、120V 半桥栅极驱动器 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27284DRCT
具有 5V UVLO 和使能端的 3A、120V 半桥栅极驱动器 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27284DRMR
具有 5V UVLO 和使能端的 3A、120V 半桥栅极驱动器 | DRM | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27284QDQ1
具有 5V UVLO 的汽车类 3A、120V 半桥栅极驱动器
| D | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27284QDRQ1
具有 5V UVLO 的汽车类 3A、120V 半桥栅极驱动器
| D | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27288
UCC27288 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and External Bootstrap DiodeWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27288D
UCC27288 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and External Bootstrap DiodeWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27288DR
UCC27288 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and External Bootstrap DiodeWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27288_V01
UCC27288 2.5-A/3.5-A 120V Half-Bridge Driver with 8V UVLO and No Internal Boostrap DiodeWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27288_V02
UCC27288 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and External Bootstrap DiodeWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCC27289
UCC27289 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and Negative Voltage HandlingWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明