UCC27289DRCR [TI]

UCC27289 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and Negative Voltage Handling;


型号：	UCC27289DRCR
厂家：	TEXAS INSTRUMENTS
描述：	UCC27289 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and Negative Voltage Handling
文件：	总32页 (文件大小：1540K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC27289

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SLUSDU4 – DECEMBER 2020

UCC27289 2.5-A/3.5-A 120-V Half-Bridge Driver

with 8-V UVLO and Negative Voltage Handling

1 Features

3 Description

•

Drives two N-channel MOSFETs in high-side low-

side configuration

The UCC27289 is a robust N-channel MOSFET driver

with a maximum switch node (HS) voltage rating of

100 V. It allows for two N-channel MOSFETs to be

controlled in half-bridge or synchronous buck

configuration based topologies. Its 3.5-A peak sink

current and 2.5-A peak source current along with low

pull-up and pull-down resistance allows the

UCC27289 to drive large power MOSFETs with

minimum switching losses during the transition of the

MOSFET Miller plateau. Since the inputs are

independent of the supply voltage, UCC27289 can be

used in conjunction with both analog and digital

controllers. Two inputs are completely independent of

each other and thus two outputs can be overlapped

by overlapping inputs, if needed. The enable and

disable functionality provides additional system

flexibility by reducing power consumption by the driver

and responds to fault events within the system.

•

Enable/disable functionality in DRC package

Low current (7-μA) consumption when disabled

16-ns typical propagation delay

12-ns rise, 10-ns fall time with 1800-pF load

(typical)

•

1-ns typical delay matching

Integrated 100V bootstrap diode

8-V typical undervoltage lockout

Absolute maximum negative voltage handling on

inputs (–5 V)

Absolute maximum negative voltage handling on

HS (–14 V)

3.5-A sink, 2.5-A Source output currents

Absolute maximum boot voltage 120 V

Inputs are independent of each other and VDD

Under voltage lockout for both channels

Specified from –40°C to 140°C junction

temperature

•

The input pins as well as the HS pin are able to

tolerate significant negative voltage, which improves

system robustness. Small propagation delay and

delay matching specifications minimize the dead-time

requirement which improves system efficiency.

2 Applications

•

Merchant network & server PSU

Merchant telecom rectifiers

DC input BLDC motor drive

Solar micro inverters

Under voltage lockout (UVLO) is provided for both the

high-side and low-side driver stages forcing the

outputs low if the VDD voltage is below the specified

threshold. An integrated bootstrap diode eliminates

the need for an external discrete diode in many

applications, which saves board space and reduces

system cost. UCC27289 is offered in multiple

packages to accommodate system requirements such

as robustness in harsh environments and density in

compact applications.

Test & measurement equipment

Simplified Application Diagram

10V

75V

Device Information

PART NUMBER

VDD

PACKAGE (SIZE)⁽¹⁾

UCC27289D

SOIC8 (6mm x 5mm)

To Load

UCC27289DRC

UCC27289DRM

UCC27289DPR

SON10 (3mm x 3mm)

SON8 (4mm x 4mm)

SON10 (4mm x 4mm)

VSS

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Switching Characteristics............................................6

6.7 Typical Characteristics................................................7

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................12

7.4 Device Functional Modes..........................................14

8 Application and Implementation..................................15

8.1 Application Information............................................. 15

8.2 Typical Application.................................................... 16

9 Power Supply Recommendations................................24

10 Layout...........................................................................25

10.1 Layout Guidelines................................................... 25

10.2 Layout Example...................................................... 25

11 Device and Documentation Support..........................26

11.1 Receiving Notification of Documentation Updates..26

11.2 Support Resources................................................. 26

11.3 Trademarks............................................................. 26

11.4 Electrostatic Discharge Caution..............................26

11.5 Glossary..................................................................26

12 Mechanical, Packaging, and Orderable

Information.................................................................... 26

4 Revision History

DATE

REVISION

NOTES

December 2020

Initial release

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5 Pin Configuration and Functions

VDD

VSS

VDD

VSS

Thermal

Pad

Not to scale

Figure 5-1. D Package 8-Pin SOIC Top View

Figure 5-2. DRC Package 10-Pin SON Top View

VDD

VSS

VDD

VSS

Thermal

Pad

Thermal

Pad

Not to scale

Figure 5-4. DPR Package 10-Pin SON Top View

Figure 5-3. DRM Package 8-Pin SON Top View

Pin Functions

DRM

I/O⁽¹⁾

DESCRIPTION

Name

DRC

DPR

Enable input. When this pin is pulled high, it will enable the driver. If left floating or

pulled low, it will disable the driver. 1 nF filter capacitor is recommended for high-

noise systems.

n/a

High-side bootstrap supply. The bootstrap diode is on-chip but the external

bootstrap capacitor is required to generate bootstrap supply from VDD. Connect

positive side of the bootstrap capacitor and cathode of an external diode to this pin.

The external diode should be 100V (minimum) rated. Higher voltage rated diode is

acceptable too. Typical recommended value of HB bypass capacitor is 0.1 μF, This

value primarily depends on the gate charge of the high-side MOSFET.

High-side input.

High-side output. Connect to the gate of the high-side power MOSFET or one end

of external gate resistor, when used.

High-side source connection. Connect to source of high-side power MOSFET.

Connect negative side of bootstrap capacitor to this pin.

Low-side input

Low-side output. Connect to the gate of the low-side power MOSFET or one end of

external gate resistor, when used.

5,6

n/a

Not connected internally.

Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical

decoupling capacitor value is 1 μF. When using an external boot diode, connect the

anode to this pin. If series resistor is used in series with the boot diode then

connect one end of series boot resistor to this pin and other end of the resistor

should be connected to the anode of the external boot diode.

VDD

VSS

Negative supply terminal for the device which is generally the system ground.

Thermal

Pad

Connect to a large thermal mass trace (generally IC ground plane) to improve

thermal performance. This can only be electrically connected to VSS.

n/a

(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output

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6 Specifications

6.1 Absolute Maximum Ratings

(1) (2)

All voltages are with respect to V_ss

MIN

–0.3

–5

MAX

UNIT

V_DD

Supply voltage

V_EN,V_HI, V_LI

Input voltages on EN, HI and LI

–0.3

–2

V_DD+ 0.3

V_HB+ 0.3

100

V_LO

V_HO

V_HS

Output voltage on LO

Output voltage on HO

Voltage on HS

Pulses < 100 ns⁽³⁾

V_HS– 0.3

V_HS– 2

–10

Pulses < 100 ns⁽³⁾

–14

100

V_HB

Voltage on HB

–0.3

–40

120

V_HB-HS

T_J

Voltage on HB with respect to HS

Operating junction temperature

Lead temperature (soldering, 10 sec.)

Storage temperature

150

°C

300

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages are with respect to V_ss. Currents are positive into, negative out of the specified terminal.

(3) Values are verified by characterization only.

6.2 ESD Ratings

VALUE

±2000

±1500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ^{(1) (2)}

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) Pins HS, HB and HO are rated at 500V HBM

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_DD

Supply voltage

V_EN, V_HI, V_LIInput Voltage

V_DD

V_HB

100

V_LO

V_HO

Low side output voltage

High side output voltage

Voltage on HS⁽¹⁾

V_HS

–8

V_HS

Voltage on HS (Pulses < 100 ns)⁽¹⁾

–12

V_HS+ 8

100

V_HB

V_sr

T_J

Voltage on HB

V_HS+16

Voltage slew rate on HS

Operating junction temperature

V/ns

°C

–40

140

(1) V_HB-HS< 16V (Voltage on HB with respect to HS must be less than 16V)

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6.4 Thermal Information

UCC27289

DRM DPR

10 PINS 8 PINS 10 PINS 8 PINS

THERMAL METRIC⁽¹⁾

DRC

UNIT

R_θJA

Junction-to-ambient thermal resistance

47.3

50.3

21.3

1.0

43.3

37.7

19.2

0.8

43.0

33.0

19.0

0.6

118.3 °C/W

R_θJC(top)Junction-to-case (top) thermal resistance

53.6

63.1

10.7

62.1

n/a

°C/W

R_θJB

ψ_JT

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

21.2

4.4

19.2

6.3

19.0

6.2

R_θJC(bot)Junction-to-case (bottom) thermal resistance

(1) For more information about thermal metrics see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

V_DD= V_EN= V_HB= 12 V, V_HS= V_SS= 0 V, No load on LO or HO, T_J= –40°C to +140°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SUPPLY CURRENTS

I_DD

VDD quiescent current

VDD operating current

V_LI= V_HI= 0

0.36 0.45 mA

I_DDO

f = 500 kHz, C_LOAD= 0

V_LI= V_HI= 0 V

2.2

0.2

2.5

2.0

0.1

7.0

4.5

0.4

μA

I_HB

HB quiescent current

I_HBO

HB operating current

f = 500 kHz, C_LOAD= 0

V_HS= V_HB= 110 V

f = 500 kHz, C_LOAD= 0

V_EN= 0

I_HBS

HB to VSS quiescent current

HB to VSS operating current⁽¹⁾

I_DDwhen driver is disabled

I_HBSO

I_{DD_DIS}

ENABLE

V_EN

μA

Voltage threshold on EN pin to enable the driver

Voltage threshold on EN pin to disable the driver

Enable pin Hysteresis

1.54

1.21

0.3

2.0

V_DIS

0.7

V_ENHYS

R_EN

EN pin internal pull-down resistor

250

kΩ

INPUT

V_HIT

Input rising threshold (HI and LI)

Input falling threshold (HI and LI)

Input voltage Hysteresis (HI and LI)

Input pulldown resistance (HI and LI)

1.9

0.9

2.1

1.1

1.0

250

2.4

1.3

V_LIT

V_IHYS

R_IN

100

350

kΩ

UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)

V_DDR

VDD rising threshold

6.5

5.7

7.0

6.5

0.5

6.3

5.8

0.5

7.8

7.3

V_DDF

VDD falling threshold

V_DDHYS

V_HBR

VDD threshold hysteresis

HB rising threshold with respect to HS pin

HB falling threshold with respect to HS pin

HB threshold hysteresis

5.5

5.0

7.1

6.6

V_HBF

V_HBHYS

BOOTSTRAP DIODE

V_F

Low-current forward voltage

I_VDD-HB= 100 μA

0.65 0.85

Ω

V_FI

R_D

High-current forward voltage

Dynamic resistance, ΔV_F/ΔI

I_VDD-HB= 80 mA

0.85

1.5

1.0

2.5

I_VDD-HB= 100 mA and 80 mA

LO GATE DRIVER

V_LOL

V_LOH

Low level output voltage

High level output voltage

I_LO= 100 mA

0.085 0.4

0.13 0.42

I_LO= -100 mA, V_LOH= V_DD– V_LO

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V_DD= V_EN= V_HB= 12 V, V_HS= V_SS= 0 V, No load on LO or HO, T_J= –40°C to +140°C, (unless otherwise noted)

PARAMETER

Peak pullup current ⁽¹⁾

Peak pulldown current ⁽¹⁾

HO GATE DRIVER

TEST CONDITIONS

MIN

TYP MAX UNIT

V_LO= 0 V

2.5

3.5

V_LO= 12 V

V_HOL

V_HOH

Low level output voltage

High level output voltage

Peak pullup current ⁽¹⁾

Peak pulldown current ⁽¹⁾

I_HO= 100 mA

0.1

0.4

I_HO= –100 mA, V_HOH= V_HB- V_HO

V_HO= 0 V

0.13 0.42

2.5

3.5

V_HO= 12 V

(1) Parameter not tested in production

6.6 Switching Characteristics

V_DD= V_HB= 12 V, V_HS= V_SS= 0 V, No load on LO or HO, T_J= –40°C to +140°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

PROPAGATION DELAYS

t_DLFF

t_DHFF

t_DLRR

t_DHRR

V_LIfalling to V_LOfalling

V_HIfalling to V_HOfalling

V_LIrising to V_LOrising

V_HIrising to V_HOrising

See Figure 6-1

DELAY MATCHING

t_MON

From LO being ON to HO being OFF

From LO being OFF to HO being ON

See Figure 6-1

t_MOFF

OUTPUT RISE AND FALL TIME

t_R

t_F

t_R

t_F

LO, HO rise time

C_LOAD= 1800 pF, 10% to 90%

C_LOAD= 1800 pF, 90% to 10%

C_LOAD= 0.1 μF, 30% to 70%

C_LOAD= 0.1 μF, 70% to 30%

μs

LO, HO fall time

LO, HO (3 V to 9 V) rise time

LO, HO (3 V to 9 V) fall time

0.33

0.23

0.6

MISCELLANEOUS

T_PW,minMinimum input pulse width that changes the output

Bootstrap diode turnoff time⁽¹⁾

I_F= 20 mA, I_REV= 0.5 A

(1) Parameter not tested in production

Input

(HI, LI)

T_DLRR, T_DHRR

Output

(HO, LO)

T_DLFF

T_DHFF

Time (s)

T_MOFF

T_MON

Figure 6-1. Timing Diagram

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6.7 Typical Characteristics

Unless otherwise specified V_VDD=V_HB= 12 V, V_HS=V_VSS= 0 V, No load on outputs

0.3

0.275

0.25

0.225

0.2

0.22

0.18

0.14

0.1

0.175

0.15

0.125

0.1

0.06

0.02

12V

16V

12V

16V

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

IDDQ

IHBQ

V_HI= V_LI= 0 V

Figure 6-2. VDD Quiescent Current

Figure 6-3. HB Quiescent Current

4.5

-40°C

25°°C

140°°C

-40°C

25°C

140°C

3.5

2.5

1.5

0.5

3 4 5 67 10

20 30 50 70100 200

Frequency (kHz)

500 1000

3 4 567 10

20 30 50 70100 200

Frequency (kHz)

500 1000

IDDO

IHBO

C_L= 0 F

V_DD=V_HB= 12V

C_L= 0 F

V_DD=V_HB= 12V

Figure 6-4. VDD Operating Current

Figure 6-5. HB Operating Current

2.22

2.21

2.2

2.19

2.18

2.17

2.16

12V

16V

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

IN_R

IHBS

Figure 6-7. Input Rising Threshold

V_HB=V_HS=100V

Figure 6-6. HB to VSS Quiescent Current

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1.145

1.14

280

270

260

250

240

230

1.135

1.13

1.125

1.12

1.115

1.11

12V

16V

1.105

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

IN_F

R_IN

Figure 6-8. Input Falling Threshold

Figure 6-9. Input Pull-down Resistor

7.6

7.5

7.4

7.3

7.2

7.1

6.8

6.6

6.4

6.2

6.9

6.8

5.8

5.6

Rise

Fall

Rise

Fall

5.4

6.7

6.6

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

VDD_

HB_U

Figure 6-10. VDD UVLO Threshold

Figure 6-11. HB UVLO Threshold

0.14

0.12

0.1

0.22

0.2

0.18

0.16

0.14

0.12

0.1

0.08

12V

16V

12V

16V

0.06

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

V_LO

I_O=100mA

I_O=-100mA

Figure 6-12. LO Low Output Voltage (V_LOL

)

Figure 6-13. LO High Output Voltage (V_LOH)

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0.16

0.2

0.18

0.16

0.14

0.12

0.1

0.14

0.12

0.1

12V

16V

12V

16V

0.08

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

UV_CHCO2

V_HO

I_O=100mA

I_O=-100mA

Figure 6-14. HO Low Output Voltage (V_HOL

)

Figure 6-15. HO High Output Voltage (V_HOH)

10.5

12V

16V

12V

16V

9.5

8.5

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

LO_F

LO_R

C_L=1800pF

Figure 6-17. LO Fall Time

Figure 6-16. LO Rise Time

8.7

8.4

8.1

7.8

7.5

7.2

12V

16V

-40

-20

40 60

Temperature (°C)

100 120 140

HO_F

C_L=1800pF

Figure 6-19. HO Fall Time

Figure 6-18. HO Rise Time

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0.4

0.38

0.36

0.34

0.32

0.3

0.45

0.425

0.4

0.375

0.35

0.325

0.3

0.28

0.26

0.24

0.22

0.2

0.275

0.25

0.225

0.2

Rise

Fall

Rise

Fall

0.175

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

HO_R

LO_R

C_L=100nF

VDD = 12 V

C_L=100nF

VDD = 12 V

Figure 6-21. HO Rise & Fall Time

Figure 6-20. LO Rise & Fall Time

12V

16V

12V

16V

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

TDHR

TDHF

C_L=No Load

C_L= No Load

Figure 6-22. HO Rising Propagation Delay (TDHRR) Figure 6-23. HO Falling Propagation Delay (TDHFF)

19.5

18.5

17.5

16.5

15.5

12V

16V

12V

16V

15.5

14.5

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

TDLR

TDLF

C_L= No Load

Figure 6-24. LO Rising Propagation Delay (TDLRR) Figure 6-25. LO Falling Propagation Delay (TDLFF)

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1.8

1.35

1.3

12V

16V

12V

16V

1.7

1.6

1.5

1.4

1.3

1.25

1.2

1.15

1.1

1.05

0.95

0.9

1.2

-40

-20

40 60

Temperature (°C)

100 120 140

-20

40 60

Temperature (°C)

100 120 140

Dis_

EN_T

Figure 6-27. Disable Threshold

Figure 6-26. Enable Threshold

2.2

2.1

12V

16V

12V

16V

1.9

1.8

1.7

1.6

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

T_Di

T_EN

Figure 6-29. Disable Delay

Figure 6-28. Enable Delay

0.95

0.9

1.8

100uA

80mA

1.75

1.7

0.85

0.8

1.65

1.6

0.75

0.7

1.55

1.5

0.65

0.6

1.45

1.4

0.55

0.5

0.45

0.4

1.35

1.3

0.35

0.3

1.25

0.25

1.2

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

R_Dy

Figure 6-30. Boot Diode Forward Voltage Drop

Figure 6-31. Boot Diode Dynamic Resistance

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7 Detailed Description

7.1 Overview

The UCC27289 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel

FETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with

two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long

as signals meet turn-on and turn-off threshold specifications of the UCC27289. The floating high-side driver is

capable of working with HS voltage up to 100 V with respect to VSS. There is an internal bootstrap diode in the

UCC27289 device to charge external high-side gate drive bootstrap capacitor. An external boot diode may be

used if needed by the application. A robust level shifter operates at high speed while consuming low power and

provides clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout (UVLO) is

provided on both the low-side and the high-side power rails.

7.2 Functional Block Diagram

UVLO

DRIVER

STAGE

LEVEL

SHIFT

VDD

UVLO

DRIVER

STAGE

VSS

7.3 Feature Description

7.3.1 Enable

The device in DRC package has an enable (EN) pin. The outputs will be active only if the EN pin voltage is

above the threshold voltage. Outputs will be held low if EN pin is left floating or pulled-down to ground. An

internal 250 kΩ resistor connects EN pin to VSS pin. Thus, leaving the EN pin floating disables the device.

Externally pulling EN pin to ground shall also disable the device. If the EN pin is not used, then it is

recommended to connect it to VDD pin. If a pull-up resistor needs to be used then a strong pull-up resistor is

recommended. For 12V supply voltage, a 10kΩ pull-up is suggested. In noise prone application, a small filter

capacitor, 1nF, should be connected from the EN pin to VSS pin as close to the device as possible. An analog or

a digital controller output pin could be connected to EN pin to enable or disable the device. Built-in hysteresis

helps prevent any nuisance tripping or chattering of the outputs.

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7.3.2 Start-up and UVLO

Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply

voltage (V_DD) and the bootstrap capacitor voltage (V_HB–HS). The UVLO circuit inhibits each output until sufficient

supply voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chattering

during supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both the

outputs are held low until VDD exceeds the UVLO threshold, typically 7.0 V. Any UVLO condition on the

bootstrap capacitor (V_HB–HS) disables only the high- side output (HO).

Table 7-1. VDD UVLO Logic Operation

Condition (V_HB-HS> V_HBR

V_DD-V_SS< V_DDRduring device start-up

V_DD-V_SS< V_DDR– V_DDHafter device start-up

Table 7-2. HB UVLO Logic Operation

Condition (V_DD> V_DDR

V_HB-HS< V_HBRduring device start-up

V_HB-HS< V_HBR– V_HBHafter device start-up

7.3.3 Input Stages

The two inputs operate independent of each other. The two inputs can overlap and output shall follow the input

signals. The independence allows for full control of two outputs compared to the gate drivers that have a single

input. There is no fixed time de-glitch filter implemented in the device and therefore propagation delay and delay

matching are not sacrificed. In other words, there is no built-in dead-time. If the dead time between two outputs

is desired then that shall be programmed through the micro-controller. If noise on the input signal is expected in

a way that could cause the inputs to overlap then the outputs shall follow the inputs and shoot-through may

occur. To avoid such situation small input filter shall be implemented at the front of the gate driver inputs, HI and

LI. Because the inputs are independent of supply voltage, they can be connected to outputs of either digital

controller or analog controller. Inputs can accept wide slew rate signals and input can withstand negative voltage

to increase the robustness. Small filter at the inputs of the driver further improves system robustness in noise

prone applications, as mentioned earlier. The inputs have internal pull down resistors with typical value of 250

kΩ. Thus, when the inputs are floating, the outputs are held low.

7.3.4 Level Shifter

The level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-side

driver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO output

which is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible and

therefore the device provides excellent propagation delay characteristic and delay matching with the low-side

driver output. Low delay matching allows power stages to operate with less dead time. The reduction in dead-

time is very important in applications where high efficiency is required.

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7.3.5 Output Stage

The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew

rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power

MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The device

output stages are robust to handle harsh environment, such as –2 V transient for 100 ns. The device can also

sustain positive transients on the outputs. The device output stages feature a pull-up structure which delivers the

highest peak source current when it is most needed, during the Miller plateau region of the power switch turn on

transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS structure.

7.3.6 Negative Voltage Transients

In most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground. In

some situations, board capacitances and inductances can cause the HS node to transiently swing several volts

below ground, before the body diode of the external low-side MOSFET clamps this swing. When used in

conjunction with the UCC27289, the HS node can swing below ground as long as specifications are not violated

and conditions mentioned in this section are followed.

HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions can

activate parasitic transistors which may result in excessive current flow from the HB supply. This may result in

damage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be

placed externally between HO and HS or LO and VSS to protect the device from this type of transient. The diode

must be placed as close to the device pins as possible in order to be effective.

Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V, then

VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally when HS

swings negative, HB follows HS instantaneously and therefore the HB to HS voltage may not significantly

overshoot.Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation

of the gate driver device. The capacitor should be located at the leads of the device to minimize series

inductance. The peak currents from LO and HO can be quite large. Any series inductances with the bypass

capacitor causes voltage ringing at the leads of the device which must be avoided for reliable operation.

Based on application board design and other operating parameters, along with HS pin, other pins such as inputs

may also transiently swing below ground. To accommodate such operating conditions UCC27289 input pins are

capable of handling -5V. Based on the layout and other design constraints, the outputs, HO and LO, may also

see transient voltages. Therefore, UCC27289 gate drivers can also handle -2 V 100 ns transients on output pins.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO

operation mode. In normal mode when the V_DDand V_HB–HSare above UVLO threshold, the output stage is

dependent on the states of the EN, HI and LI pins. The output HO and LO will be low if input state is floating.

Following truth table applies when the device is enabled (EN pin is pulled high).

Table 7-3. Input/Output Logic in Normal Mode of Operation

HO ⁽¹⁾

LO ⁽²⁾

Floating

(1) HO is measured with respect to HS

(2) LO is measured with respect to VSS

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

Most electronic devices and applications are becoming more and more power hungry. These applications are

also reducing in overall size. One way to achieve both high power and low size is to improve the efficiency and

distribute the power loss optimally. Most of these applications employ power MOSFETs and they are being

switched at higher and higher frequencies. To operate power MOSFETs at high switching frequencies and to

reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller

and the gates of the power semiconductor devices, such as power MOSFETs, IGBTs, SiC FETs, and GaN FETs.

Many of these applications require proper UVLO protection so that power semiconductor devices are turned ON

and OFF optimally. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly

drive the gates of the switching devices. With the advent of digital power, this situation is often encountered

because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a

power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V or 5

V) in order to fully turn-on the power device, minimize conduction losses, and minimize the switching losses.

Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove

inadequate with digital power because they lack level-shifting capability and under voltage lockout protection.

Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also solve other

problems such as minimizing the effect of high-frequency switching noise (by placing the high-current driver

device physically close to the power switch), driving gate-drive transformers and controlling floating power device

gates. This helps reduce power dissipation and thermal stress in controllers by moving gate charge power losses

from the controller IC to the gate driver.

UCC27289 gate drivers offer high voltage (100 V), small delays (16 ns), and good driving capability (2.5 A/3.5 A)

in a single device. The floating high-side driver is capable of operating with switch node voltages up to 100 V.

This allows for N-channel MOSFETs control in half-bridge, full-bridge, synchronous buck, synchronous boost,

and active clamp topologies. UCC27289 gate driver IC has integrated bootstrap diode and therefore to generate

high-side bias from the VDD voltage no external boot diode required in most applications. This allows users to

optimize board layout and reduce bill of material costs. If external bootstrap diode is used then it should be fast

recovery and low forward voltage drop Schottky diode. Each channel is controlled by its respective input pins (HI

and LI), allowing flexibility to control ON and OFF state of the output.

Switching power devices such as MOSFETs have two main loss components; switching losses and conduction

losses. Conduction loss is dominated by current through the device and ON resistance of the device. Switching

losses are dominated by gate charge of the switching device, gate voltage of the switching device, and switching

frequency. Applications where operating switching frequency is high, the switching losses start to impact overall

system efficiency. In such applications, to reduce the switching losses it becomes essential to reduce the gate

voltage. The gate voltage is determined by the supply voltage the gate driver ICs, therefore, the gate driver IC

needs to operate at lower supply voltage in such applications. UCC27289 gate driver has typical UVLO level of

7.0V and therefore, they are perfectly suitable for applications where bias voltage need to be reduced from 12V

to 10V or even 9.5V. HB UVLO is lower than the VDD UVLO so that bootstrap diode voltage drop does not

inhibit this lower bias voltage opearion. There is enough UVLO hysteresis provided to avoid any chattering or

nuisance tripping which improves system robustness.

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8.2 Typical Application

10 V

75 V

VDD

D_Boot

SECONDARY

SIDE

CIRCUIT

DRIVE

PWM

CONTROLLER

DRIVE

UCC27289

ISOLATION

AND

FEEDBACK

Figure 8-1. Typical Application

8.2.1 Design Requirements

Table below lists the system parameters. UCC27289 needs to operate satisfactorily in conjunction with them.

Table 8-1. Design Requirements

Parameter

MOSFET

Value

CSD19535KTT

75V

Maximum Bus/Input Voltage, V_in

Operating Bias Votage, V_DD

Switching Frequency, Fsw

Total Gate Charge of FET at given VDD, Q_G

MOSFET Internal Gate Resistance, R_{GFET_Int}

Maximum Duty Cycle, D_Max

Gate Driver

10V

300kHz

52nC

1.4

0.5

UCC27289

8.2.2 Detailed Design Procedure

8.2.2.1 Select Bootstrap and VDD Capacitor

The bootstrap capacitor must maintain the V _HB-HSvoltage above the UVLO threshold for normal operation.

Calculate the maximum allowable drop across the bootstrap capacitor, ΔV_HB, with Equation 1.

¿V_HB= V_DDF V_DHF V_HBL

;

= 10 V ꢀ 1 V ꢀ (7.1 V ꢀ 0.5 V) = 2.4 V

(1)

where

•

V_DDis the supply voltage of gate driver device

V_DHis the bootstrap diode forward voltage drop

V_HBLis the HB falling threshold ( V_HBR(max)– V_HBH

)

In this example the allowed voltage drop across bootstrap capacitor is 2.4 V.

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It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be

minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of

0.5 V.

Use Equation 2 to estimate the total charge needed per switching cycle from bootstrap capacitor.

D_MAX

Q_TOTAL= Q_G+ I_HBS× l

I_HB

p + l

f_SW

= 52 nC + 0.083 nC + 1.33 nC = 53.41 nC

(2)

where

•

Q_Gis the total MOSFET gate charge

I_HBSis the HB to VSS leakage current from datasheet

D_Maxis the converter maximum duty cycle

I_HBis the HB quiescent current from the datasheet

The caculated total charge is 53.41 nC.

Next, use Equation 3 to estimate the minimum bootstrap capacitor value.

Q_TOTAL

53.41 nC

2.4 V

C_BOOT

;

= 22.25 nF

min

¿V_HB

(3)

The calculated value of minimum bootstrap capacitor is 22.25 nF. It should be noted that, this value of

capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than

calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.

It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include

enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small

size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.

For this application, choose a C_BOOTcapacitor that has the following specifications: 0.1 µF, 25 V, X7R

As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value

(generally 10 times the bootstrap capacitor value). For this application choose a C _VDDcapacitor with the

following specifications: 1 µF , 25 V, X7R

C_VDDcapacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a

small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,

1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.

The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a

voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most

ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of

the system.

8.2.2.2 External Bootstrap Diode and Series Resistor

The UCC27289 has integrated bootstrap diode, necessary to generate the high-side bias for HO to work

satisfactorily. The characteristics of this diode are important to achieve efficient, reliable operation. If external

bootstrap diode is needed then the diode characteristics to consider are reverse voltage handling capability,

repetitive peak forward current, forward voltage drop, forward and reverse recovery time, and dynamic

resistance. As the UCC27289 is 100V rated gate driver, the external bootstrap diode must be at least 100V

rated. Peak forward current rating depends on multiple system parameters such as high-side and low-side duty

cycle, value of bootstrap capacitor, and allowed voltage ripple on the bootstrap capacitor. Generally, low forward

voltage drop diodes are preferred for low power loss during charging of the bootstrap capacitor. Schottky diodes

have low forward voltage drop and can be used with the UCC27289. The dynamic characteristics to consider are

diode recovery time and stored charge. Diode that has less than 50ns of forward and reverse recovery times is

suitable in most applications.

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Specifically in very high switching frequency applications, for example in excess of 1 MHz, and where the low-

side minimum pulse widths are very small, the diode peak forward current could be very high and peak reverse

current could also be very high, specifically if high bootstrap capacitor value has been chosen. In such

applications it might be advisable to use Schottkey diode as bootstrap diode. MURS210 diode will work with the

application example described here.

8.2.2.3 Estimate Driver Power Losses

The total power loss in gate driver device such as the UCC27289 is the summation of the power loss in different

functional blocks of the gate driver device. These power loss components are explained in this section.

1. Equation 4 describes how quiescent currents (I_DDand I_HB) affect the static power losses, P_QC

: ; : ;

= V_DD× I_DD+ V_DDF V_DH× I_HB

P_QC

= 10 V × 0.4 mA + 9 V × 0.4 mA = 7.6 mW

(4)

it is not shown here, but for more conservative approximation, add no load operating current, I_DDOand I_HBOin

above equation.

2. Equation 5 shows how high-side to low-side leakage current (I_HBS) affects level-shifter losses (P_IHBS).

IHBS

= V_HB× I_HBS× D = 85 V × 50 µA × 0.5 = 2.12 mW

(5)

where

•

D is the high-side MOSFET duty cycle

V_HBis the sum of input voltage and voltage across bootstrap capacitor.

3. Equation 6 shows how MOSFETs gate charge (Q_G) affects the dynamic losses, P_QG

R_{GD_R}

P_QG= 2 × V_DD× Q_G× f_SW

R_{GD _R}+ R_GATE+ R_{GFET int}

;

= 2 × 10 V × 52 nC × 300 kHz × 0.74 = 0.23 W

(6)

where

•

Q_Gis the total MOSFET gate charge

f_SWis the switching frequency

R_{GD_R}is the average value of pullup and pulldown resistor

R_GATEis the external gate drive resistor

R_GFET(int)is the power MOSFETs internal gate resistor

Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull

down resistance of the driver output section is approximately 4 Ω. Substitute the application values to

calculate the dynamic loss due to gate charge, which is 230 mW here.

4. Equation 7 shows how parasitic level-shifter charge (Q_P) on each switching cycle affects dynamic losses,

(P_LS) during high-side switching.

P = V_HB× Q_P× f_SW

(7)

For this example and simplicity, it is assumed that value of parasitic charge Q_Pis 1 nC. Substituting values

results in 25.5 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.

The sum of all the losses is 265.22 mW as a total gate driver loss. As shown in this example, in most

applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate

drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward

conduction loss is computed as product of average forward voltage drop and average forward current.

Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.

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kT F T_Ao

R_EJA

(8)

where

•

P_MAXis the maximum allowed power dissipation in the gate driver device

T_Jis the recommended maximum operating junction temperature

T_Ais hte ambient temperature of the gate driver device

R_θJAis the junction-to-ambient thermal resistance

To better estimate the junction temperature of the gate driver device in the application, it is recommended to first

accurately measure the case temperature and then determine the power dissipation in a given application. Then

use ψ _JTto calculate junction temperature. After estimating junction temperature and measuring ambient

temperature in the application, calculate θ_{JA(effective)}. Then, if design parameters (such as the value of an external

gate resistor or power MOSFET) change during the development of the project, use θ_{JA(effective)}to estimate how

these changes affect junction temperature of the gate driver device.

The Thermal Information table summarizes the thermal metrics for the driver package. For detailed information

regarding the thermal information table, please refer to the Semiconductor and Device Package Thermal Metrics

application report.

8.2.2.4 Selecting External Gate Resistor

In high-frequency switching power supply applications where high-current gate drivers such as the UCC27289

are used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing on

the gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some

applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak

output current capability. In such applications external gate resistors can limit the peak output current of the gate

driver. it is recommended that there should be provision of external gate resistor whenever the layout or

application permits.

Use Equation 9 to calculate the driver high-side pull-up current.

V_DDF V_DH

R_HOH+ R_GATE+ R_{GFET int}

I_OHH

;

(9)

where

•

I_OHHis the high-side, peak pull-up current

V_DHis the bootstrap diode forward voltage drop

R_HOHis the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be

calculated from test conditions (R_HOH= V_HOH/I_HO

)

•

R_GATEis the external gate resistance connected between driver output and power MOSFET gate

R_GFET(int)is the MOSFET internal gate resistance provided by MOSFET datasheet

Use Equation 10 to calculate the driver high-side sink current.

V_DDF V_DH

R_HOL+ R_GATE+ R_{GFET int}

I_OLH

;

(10)

where

R_HOLis the gate driver internal high-side pull-down resistance

•

Use Equation 11 to calculate the driver low-side source current.

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V_DD

I_OHL

R_LOH+ R_GATE+ R_{GFET int}

;

(11)

where

R_LOHis the gate driver internal low-side pull-up resistance

•

Use Equation 12 to calculate the driver low-side sink current.

V_DD

I_OLL

R_LOL+ R_GATE+ R_{GFET int}

;

(12)

where

R_LOLis the gate driver internal low-side pull-down resistance

•

Typical peak pull up and pull down current of the device is 2.5 A and 3.5 A respectively. These equations help

reduce the peak current if needed. To establish different rise time value compared to fall time value, external

gate resistor can be anti-paralleled with diode-resistor combination as shown in Figure 8-1. Generally selecting

an optimal value or configuration of external gate resistor is an iterative process. For additional information on

selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers

8.2.2.5 Delays and Pulse Width

The total delay encountered in the PWM, driver and power stage need to be considered for a number of

reasons, primarily delay in current limit response. Also to be considered are differences in delays between the

drivers which can lead to various concerns depending on the topology. The synchronous buck topology

switching requires careful selection of dead-time between the high-side and low-side switches to avoid cross

conduction as well as excessive body diode conduction.

Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the

high-side and low-side pulse widths in any operating condition. The UCC27289 device has maximum

propagation delay, across process, and temperature variation, of 30 ns and delay matching of 7 ns, which is one

of the best in the industry.

Narrow input pulse width performance is an important consideration in gate driver devices, because output may

not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively

wide steady state PWM output signals from controller, very narrow pulses may be encountered under following

operating conditions.

•

soft-start period

large load transients

short circuit conditions

These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to

respond properly to these narrow signals.

Figure 8-2 shows that the UCC27289 device produces reliable output pulse even when the input pulses are very

narrow. The propagation delay and delay matching do not get affected when the input pulse width is very narrow.

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HI (2V/div)

BW=1GHz

LI (2V/div)

BW=1GHz

LO (5V/div)

BW=1GHz

HO (5V/div)

BW=1GHz

Figure 8-2. Input and Output Pulse Width

8.2.2.6 VDD and Input Filter

Some switching power supply applications are extremely noisy. Noise may come from ground bouncing and

ringing at the inputs, (which are the HI and LI pins of the gate driver device). To mitigate such situations, the

UCC27289 offers both negative input voltage handling capability and wide input threshold hysteresis. If these

features are not enough, then the application might need an input filter. Small filter such as 10-Ω resistor and 47-

pF capacitor might be sufficient to filter noise at the inputs of the gate driver device. This RC filter would

introduce delay and therefore need to be considered carefully. High frequency noise on bias supply can cause

problems in performance of the gate driver device. To filter this noise it is recommended to use 1-Ω resistor in

series with VDD pin as shown in Figure 8-1. This resistor also acts as a current limiting element. In the event of

short circuit on the bias rail, this resistor opens up and prevents further damage. This resistor can also be helpful

in debugging the design during development phase.

8.2.2.7 Transient Protection

As mentioned in previous sections, high power high switching frequency power supplies are inherently noisy.

High dV/dt and dI/dt in the circuit can cause negative voltage on different pins such as HO, LO, and HS. The

device tolerates negative voltage on all of these pins as mentioned in specification tables. If parasitic elements of

the circuit cause very large negative swings, circuit might require additional protection. In such cases fast acting

and low leakage type Schottky diode should be used. This diode must be placed as close to the gate driver

device pin as possible for it to be effective in clamping excessive negative voltage on the gate driver device pin.

To avoid the possibility of driver device damage due to over-voltage on its output pins or supply pins, low

leakage Zener diode can be used. A 15-V Zener diode is often sufficient to clamp the voltage below the

maximum recommended value of 16 V.

8.2.3 Application Curves

To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be as

fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the UCC27289

is designed with high drive current capability and low resistance of the output stages. One of the common way to

test the drive capability of the gate driver device , is to test it under heavy load. Rise time and fall time of the

outputs would provide idea of drive capability of the gate driver device. There should not be any resistance in

series with the load capacitor if large capacitor is used to measure the drive strength. Peak current capability can

be estimated using the fastest dV/dt along the rise and fall curve of the plot. This method is also useful in

comparing performance of two or more gate driver devices.

UCC27289 was tested in application like environment. Synchrounous buck converter at no load was used to

gnerate following waveforms. Switching frequency was set to 100kHz and input voltage was set to 100V.

UCC27289 was driving BSC16DN250NS3 with 2 Ohm external resistor. All the waveforms were taken using

single ended probes. Figure 8-3 and Figure 8-4 shows rise time and fall time of HO respectively. Figure 8-5 and

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Figure 8-6 shows rise time and fall time of LO respectively. Internal bootstrap diode and external bootstrap

capacitor generated the high-side bias.

As explained in Section 8.2.2.5, propagation delay plays an important role in reliable operation of many

applications. Figure 8-7 and Figure 8-8 shows LO rise and fall propagation delay of UCC27289. Similar

propagation delay was observed for HO output as well.

HO (20V/div)

HI (10V/div)

V_DD==12 V, HS=100V

V_DD=12 V, HS=100V

Figure 8-4. HO Fall Time

Figure 8-3. HO Rise Time

LO (10V/div)

HO (20V/div)

LI (10V/div)

HI (10V/div)

V_DD=12V, HS=100V

Figure 8-5. LO Rise Time

Figure 8-6. LO Fall Time

LO (10V/div)

LI (10V/div)

V_DD=12 V

Figure 8-7. Turn-on Propagation Delay

Figure 8-8. Turn-off Propagation Delay

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V_DD=10V, V_in=100V

C_L=1nF

Ch1=HI Ch2=LI Ch3=HO Ch4=LO

Figure 8-9. Input Negative Voltage

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9 Power Supply Recommendations

The recommended bias supply voltage range for UCC27289 is from 8 V to 16 V. The lower end of this range is

governed by the internal under voltage-lockout (UVLO) protection feature, 7.0 V typical, of the V_DDsupply circuit

block. The upper end of this range is driven by the 16-V recomended maximum voltage rating of the V_VDD. It is

recommended that voltage on VDD pin should be lower than maximum recommended voltage.

The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in

normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage

drop do not exceeds the hysteresis specification, V _DDHYS. If the voltage drop is more than hysteresis

specification, the device shuts down. Therefore, while operating at or near the 8-V range, the voltage ripple on

the auxiliary power supply output should be smaller than the hysteresis specification of UCC27289 to avoid

triggering device shutdown.

UCC27289 has enable/disable functionality through EN pin. Therefore, signal at the EN pin should be as clean

as possible. If EN pin is not used, then it is recommended to connect the pin to VDD pin. If EN pin is pulled up

through a resistor, then the pull-up resistor needs to be strong. In noise prone applications, it is recommended to

filter the EN pin with small capacitor, such as X7R 0402 1nF.

A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as

close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is

recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor

for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surface-

mount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin

are sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value

small size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO

pulses.

In applications where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is

recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the

design. In such applications. it is also recommended to have a place holder for power MOSFET external gate

resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which

impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is

recommended to use a resistor in series with the diode, which provides further control of fall time.

In power supply applications such as motor drives, there exist lot of transients through-out the system. This

sometime causes over voltage and under voltage spikes on almost all pins of the gate driver device. To increase

the robustness of the design, it is recommended that the clamp diode should be used on HO and LO pins. If user

does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which

needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these

diodes across the temperature needs to be minimal.

In power supply applications where it is almost certain that there is excessive negative HS voltage, it is

recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit

current into the driver device up to some extent. This resistor will impact the high side drive capability and

therefore needs to be considered carefully.

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UCC27289

SLUSDU4 – DECEMBER 2020

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10 Layout

10.1 Layout Guidelines

To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed

wiring board (PWB) layout guidelines.

•

Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between

HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the

external MOSFETs.

•

To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a

good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).

In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the

source of the high-side MOSFET and the source of the low-side MOSFET (synchronous rectifier) must be

minimized.

•

Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling

of switching noise into the ground plane is minimized.

Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the

device. Generally it is connected to the ground plane which is the same as VSS of the device. It is

recommended to connect this pad to the VSS pin only.

•

Grounding considerations:

– The first priority in designing grounding connections is to confine the high peak currents that charge and

discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance

and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the

MOSFETs as possible.

– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap

diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The

bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground

referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak

current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.

10.2 Layout Example

HB Bypass

Capacitor (Top)

Gate Driver

(Top)

External Gate

Resistor (Top)

Input Filters

(Top)

Boot Diode

(Bottom)

VDD Bypass

Capacitors (Top)

External Gate

Resistor (Bottom)

Figure 10-1. Layout Example

Submit Document Feedback

UCC27289

SLUSDU4 – DECEMBER 2020

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

11-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC27289D

UCC27289DR

UCC27289DRCR

ACTIVE

SOIC

VSON

1500 RoHS & Green

2500 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Call TI

-40 to 125

U289

NIPDAU

Call TI

PREVIEW

DRC

3000 RoHS (In work)

& Non-Green

UCC27289DRCT

PREVIEW

VSON

DRC

250

RoHS (In work)

& Non-Green

Call TI

-40 to 125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC27289DRCR [TI]

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UCC27289DRCT

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UCC27321DGNG4

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