UCC27423PE4 [TI]
Dual 4-A High Speed Low-Side MOSFET Drivers With Enable; 双4 -A高速低侧MOSFET驱动器与启用
| 型号： | UCC27423PE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 4-A High Speed Low-Side MOSFET Drivers With Enable |
| 文件： | 总30页 (文件大小：1460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC27423, UCC27424, UCC27425
www.ti.com
SLUS545D –NOVEMBER 2002–REVISED MAY 2013
Dual 4-A High Speed Low-Side MOSFET Drivers With Enable
Check for Samples: UCC27423, UCC27424, UCC27425
1
FEATURES
DESCRIPTION
The UCC27423/4/5 family of high-speed dual
2
•
•
•
•
Industry-Standard Pin-Out
MOSFET drivers can deliver large peak currents into
capacitive loads. Three standard logic options are
offered – dual-inverting, dual-noninverting and one-
inverting and one-noninverting driver. The thermally
enhanced 8-pin PowerPAD™ MSOP package (DGN)
drastically lowers the thermal resistance to improve
long-term reliability. It is also offered in the standard
SOIC-8 (D) or PDIP-8 (P) packages.
Enable Functions for Each Driver
High Current Drive Capability of ±4A
Unique BiPolar and CMOS True Drive Output
Stage Provides High Current at MOSFET Miller
Thresholds
•
•
•
TTL/CMOS Compatible Inputs Independent of
Supply Voltage
Using a design that inherently minimizes shoot-
through current, these drivers deliver 4A of current
where it is needed most at the Miller plateau region
during the MOSFET switching transition. A unique
BiPolar and MOSFET hybrid output stage in parallel
also allows efficient current sourcing and sinking at
low supply voltages.
20ns Typical Rise and 15ns Typical Fall Times
with 1.8nF Load
Typical Propagation Delay Times of 25ns with
Input Falling and 35ns with Input Rising
•
•
4V to 15V Supply Voltage
Dual Outputs Can Be Paralleled for Higher
Drive Current
The UCC27423/4/5 provides enable (ENBL) functions
to have better control of the operation of the driver
applications. ENBA and ENBB are implemented on
pins 1 and 8 which were previously left unused in the
industry standard pin-out. They are internally pulled
up to Vdd for active high logic and can be left open
for standard operation.
•
•
Available in Thermally Enhanced MSOP
PowerPAD™ Package with 4.7°C/W θJC
Rated From –40°C to 125°C
APPLICATIONS
•
•
•
•
•
Switch Mode Power Supplies
DC/DC Converters
BLOCK DIAGRAM
Motor Controllers
8
ENBB
Line Drivers
ENBA
1
INVERTING
Class D Switching Amplifiers
7
6
OUTA
VDD
VDD
INA
2
3
NON-INVERTING
INVERTING
GND
5
OUTB
INB
4
NON-INVERTING
UDG-01063
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
UCC27423, UCC27424, UCC27425
SLUS545D –NOVEMBER 2002–REVISED MAY 2013
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ORDERING INFORMATION
PACKAGED DEVICES
OUTPUT
CONFIGURATION
TEMPERATURE RANGE
TA = TJ
SOIC-8
(D)(1)
MSOP-8 PowerPAD
(DGN)(2)
PDIP-8
(P)
Dual inverting
–40°C to 125°C
–40°C to 125°C
UCC27423D
UCC27424D
UCC27423DGN
UCC27424DGN
UCC27423P
UCC27424P
Dual nonInverting
One inverting, one
noninverting
–40°C to 125°C
UCC27425D
UCC27425DGN
UCC27425P
(1) D (SOIC-8) and DGN (PowerPAD-MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR,
UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.
(2) The PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
D, DGN, OR P PACKAGE
(TOP VIEW)
D, DGN, OR P PACKAGE
(TOP VIEW)
D, DGN, OR P PACKAGE
(TOP VIEW)
UCC27425
UCC27424
UCC27423
ENBA
1
8
7
6
5
ENBB
OUTA
VDD
ENBA
1
8
7
6
5
ENBB
OUTA
VDD
ENBA
1
8
7
6
5
ENBB
OUTA
VDD
INA 2
GND 3
INB 4
INA 2
GND 3
INB 4
INA 2
GND 3
INB 4
OUTB
OUTB
OUTB
(DUAL INVERTING)
(DUAL NON-INVERTING)
(ONE INVERTING AND
ONE NON-INVERTING)
POWER DISSIPATION RATING TABLE
DERATING FACTOR
POWER RATING (mW)
TA = 70°C(1)
PACKAGE
SUFFIX
θJC (°C/W)
θJA (°C/W)
ABOVE
70°C (mW/°C)(1)
SOIC-8
PDIP-8
D
P
42
49
84 - 160‡
110
344–655(2)
500
6.25–11.9(2)
9
MSOP PowerPAD-8(3)
DGN
4.7
50 - 59‡
1370
17.1
(1) 125°C operating junction temperature is used for power rating calculations
(2) The range of values indicates the effect of pc-board. These values are intended to give the system designer an indication of the best
and worst case conditions. In general, the system designer should attempt to use larger traces on the pc-board where possible in order
to spread the heat away form the device more effectively. For information on the PowerPAD™ package, refer to Technical Brief,
PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002) and Application Brief, PowerPad Made Easy, Texas
Instruments (SLMA004).
(3) The PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
Table 1. Input/Output Table
INPUTS (VIN_L, VIN_H)
UCC27423
UCC27424
UCC27425
ENBA
ENBB
INA
L
INB
L
OUTA OUTB OUTA OUTB OUTA OUTB
H
H
H
H
L
H
H
H
H
L
H
H
L
H
L
L
L
L
H
L
H
H
L
L
H
L
L
H
H
L
H
L
H
H
L
H
H
L
H
L
L
H
L
X
X
L
L
L
2
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SLUS545D –NOVEMBER 2002–REVISED MAY 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
VDD
Supply voltage
-0.3 to 16
V
A
A
V
IOUT_DC
IOUT_PULSED
VIN
Output current (OUTA, OUTB) DC
Pulsed, (0.5μs)
0.2
4.5
Input voltage (INA, INB)
Enable voltage (ENBA, ENBB)
-5 to 6 or VDD+0.3 (whichever is larger)
–0.3 V to 6 V or VDD+0.3 (whichever is larger)
DGN package
D package
3
650
W
Power dissipation at TA = 25°C
mW
P package
350
TJ
Junction operating temperature
Storage temperature
–55 to 150
–65 to 150
300
Tstg
°C
Lead temperature (soldering, 10 sec)
(1) When VDD ≤ 6 V, EN rating max value is 6 V; when VDD > 6 V, EN rating max value is VDD + 0.3 V.
ELECTRICAL CHARACTERISTICS
VDD = 4.5V to 15V, TA = –40°C to 125°C ,TA = TJ, (unless otherwise noted)
PARAMETER
INPUT (INA, INB)
VIN_H Logic 1 input threshold
TEST CONDITION
MIN
2
TYP
MAX
UNIT
V
VIN_L
Logic 0 input threshold
Input current
1
0 V ≤ VIN ≤ VDD
–10
0
10
μA
OUTPUT (OUTA, OUTB)
(1)
Output current
VDD = 14 V
4
330
22
A
VOH
VOL
High-level output voltage
VOH = VDD – VOUT, IOUT = –10 mA
450
45
mV
Low-level output level
IOUT = 10 mA
TA = 25°C, IOUT = –10 mA, VDD = 14 V(2)
TA = full range, IOUT = –10 mA, VDD = 14 V(2)
TA = 25°C, IOUT = 10 mA, VDD = 14 V(2)
TA = full range IOUT = 10 mA, VDD = 14 V(2)
25
18
30
35
Output resistance high
45
Ω
1.9
1.2
500
2.2
2.5
4.0
Output resistance low
Latch-up protection
mA
SWITCHING TIME
tr
Rise time (OUTA, OUTB)
CLOAD = 1.8 nF
CLOAD = 1.8 nF
CLOAD = 1.8 nF
CLOAD = 1.8 nF
20
15
25
35
40
40
40
50
tf
Fall time (OUTA, OUTB)
Delay, IN rising (IN to OUT)
Delay, IN falling (IN to OUT)
ns
td1
td2
(1) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
(2) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
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ELECTRICAL CHARACTERISTICS (Continued)
VDD = 4.5V to 15 V, TA = –40°C to 125°C,TA = TJ (unless otherwise noted)
(1) (2)
PARAMETER
ENABLE (ENBA, ENBB)
VIN_H High-level input voltage
TEST CONDITION
MIN
TYP
MAX UNITS
LO to HI transition
1.7
1.1
2.4
1.8
2.9
VIN_L
Low-level input voltage
Hysteresis
HI to LO transition
2.2
0.90
140
60
V
0.15
75
0.55
100
30
RENBL Enable impedance
tD3 Propagation delay time (see Figure 2)
tD4 Propagation delay time (see Figure 2)
OVERALL
VDD = 14 V, ENBL = GND
CLOAD = 1.8 nF
kΩ
ns
CLOAD = 1.8 nF
100
150
INA = 0 V, INB = 0 V
900
750
750
600
300
750
750
1200
600
1050
450
900
300
450
450
600
1350
1100
1100
900
INA = 0 V, INB = HIGH
INA = HIGH, INB = 0 V
INA = HIGH, INB = HIGH
INA = 0 V, INB = 0 V
UCC27423
UCC27424
UCC27425
All
μA
μA
μA
μA
450
Static operating current,
VDD = 15 V,
ENBA = ENBB = 15 V
INA = 0 V, INB = HIGH
INA = HIGH, INB = 0 V
INA = HIGH, INB = HIGH
INA = 0 V, INB = 0 V
1100
1100
1800
900
IDD
INA = 0 V, INB = HIGH
INA = HIGH, INB = 0 V
INA = HIGH, INB = HIGH
INA = 0 V, INB = 0 V
1600
700
1350
450
INA = 0 V, INB = HIGH
INA = HIGH, INB = 0 V
INA = HIGH, INB = HIGH
700
Disabled, VDD = 15 V,
ENBA = ENBB = 0 V
IDD
700
900
(1) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors.
(2) The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
(a)
(b)
+5V
90%
90%
INPUT
INPUT
10%
10%
0V
t
t
t
t
f
t
F
D1
D2
F
t
F
16V
90%
90%
90%
t
D1
t
OUTPUT
OUTPUT
D2
10%
10%
0V
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
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5V
ENBx
0V
V
V
IN_L
IN_H
t
t
D3
D4
V
DD
90%
90%
t
F
t
R
OUTx
10%
0V
NOTE: The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 2. Switching Waveform for Enable to Output
Terminal Functions
TERMINAL
I/O
FUNCTION
NO.
NAME
1
ENBA
I
Enable input for the driver A with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with
this pin. It is internally pulled up to VDD with 100kΩ resistor for active high operation. The output state when the device is
disabled will be low regardless of the input state.
2
INA
I
I
Input A. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to
either VDD or GND. It should not be left floating.(1)
3
4
GND
INB
Common ground. This ground should be connected very closely to the source of the power MOSFET which the driver is driving.
Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to
either VDD or GND. It should not be left floating.
5
6
7
8
OUTB
VDD
O
I
Driver output B. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
Supply. Supply voltage and the power input connection for this device.
OUTA
ENBB
O
I
Driver output A. The output stage is capable of providing 4A drive current to the gate of a power MOSFET.
Enable input for the driver B with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with
this pin. It is internally pulled up to VDD with 100kΩ resistor for active high operation. The output state when the device is
disabled will be low regardless of the input state.(1)
(1) Refer to APPLICATION INFORMATION Section for more details.
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APPLICATION INFORMATION
General Information
High frequency power supplies often require high-speed, high-current drivers such as the UCC27423/4/5 family.
A leading application is the need to provide a high power buffer stage between the PWM output of the control IC
and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is utilized
to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the
need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry.
Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching
devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended
switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to
minimize the effect of high frequency switching noise by placing the high current driver physically close to the
load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at
all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the
UCC27423/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external
driver can help by moving the heat from the controller to an external package.
Input Stage
The input thresholds have a 3.3V logic sensitivity over the full range of VDD voltages; yet it is equally compatible
with 0 to VDD signals. The inputs of UCC27423/4/5 family of drivers are designed to withstand 500-mA reverse
current without either damage to the IC for logic upset. The input stage of each driver should be driven by a
signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input
signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to
the drivers function as a digital gate, and they are not intended for applications where a slow changing input
voltage is used to generate a switching output when the logic threshold of the input section is reached. While this
may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.
Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal
at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power
device, then an external resistance can be added between the output of the driver and the load device, which is
generally a power MOSFET gate. The external resistor may also help remove power dissipation from the devoce
package, as discussed in the section on Thermal Considerations.
Output Stage
Inverting outputs of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channel
MOSFETs. Noninverting outputs of the UCC27424 and OUTB of the UCC27425 are intended to drive external N-
channel MOSFETs.
Each output stage is capable of supplying ±4A peak current pulses and swings to both VDD and GND. The
pullup/pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is
the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of
the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to
the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not
required.
The UCC27423 family delivers 4A of gate drive where it is most needed during the MOSFET switching
transition – at the Miller plateau region – providing improved efficiency gains. A unique BiPolar and MOSFET
hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCC27423/4/5 drivers have been optimized to provide maximum drive to a power MOSFET
during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging
between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver device. [1]
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Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry is
added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is
applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient
period where the current peaked up and then settled down to a steady-state value. The noted current
measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient.
The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped
around 5V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found to
sink 4.5A at VDD = 15V and 4.28A at VDD = 12V.
The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V
with a string of Zener diodes. The UCC27423 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V.
VDD
UCC27423
ENBA
1
2
3
4
ENBB
8
7
6
5
INPUT
D
SCHOTTKY
Ω
10
INA
OUTA
V
SUPPLY
5.5 V
C2
+
µ
1
F
F
GND
INB
VDD
OUTB
V
SNS
µ
100
F
R
0.1
µ
CER
SNS
1
F
AL EL
Ω
UDG-01065
Figure 3.
It should be noted that the current sink capability is slightly stronger than the current source capability at lower
VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the
current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.
In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the
turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients
which may turn the device back ON.
Parallel Outputs
The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the
OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 4.
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VDD
UCC27423
ENBA
1
2
3
4
ENBB
OUTA
8
7
INPUT
D
SCHOTTKY
10Ω
INA
D
ADJ
5.5 V
C2
µ
C3
100 F
µ
+
1 F
GND
INB
VDD 6
OUTB
5
V
SNS
100 F
AL EL
µ
R
SNS
1 µF
CER
0.1
Ω
UDG-01066
Figure 4.
Operational Waveforms and Circuit Layout
Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load.
The input pulsewidth (not shown) is set to 300ns to show both transitions in the output waveform. Note the linear
rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the
driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.
VDD
UCC27423
ENBA
1
2
3
4
ENBB
8
7
6
5
INPUT
INA
OUTA
GND
INB
VDD
OUTB
C
LOAD
2.2µF
1
F
µ
CER
UDG-01067
Figure 5.
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Figure 6.
In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much
overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high
di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is
advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the
opposite side of the output, so the ground should be connected to the bypass capacitors and the load with
copper trace as wide as possible. These connections should also be made with a small enclosed loop area to
minimize the inductance.
VDD
Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB
current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the
average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from:
IOUT = Qg × f, where f is frequency
For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise
problems. The use of surface mount components is highly recommended. A 0.1μF ceramic capacitor should be
located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1μF) with relatively low
ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination
of capacitors should present a low impedance characteristic for the expected current levels in the driver
application.
Drive Current and Power Requirements
The UCC27423/4/5 family of drivers are capable of delivering 4A of current to a MOSFET gate for a period of
several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the
device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating
frequency of the power device. A MOSFET is used in this discussion because it is the most common type of
switching device used in high frequency power conversion equipment.
References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching
devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.
When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is
required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor
is given by:
1
2
2
E + CV
, where C is the load capacitor and V is the bias voltage feeding the driver.
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There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by the following:
1
2
2
P + 2 CV f
, where f is the switching frequency.
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD = 12V, CLOAD = 10nF, and f = 300kHz, the power loss can be calculated as:
P = 10nF × (12)2 × (300kHz) = 0.432W
With a 12V supply, this would equate to a current of:
0.432 W
12 V
P
V
I +
+
+ 0.036 A
(1)
The actual current measured from the supply was 0.037A, and is very close to the predicted value. But, the IDD
current that is due to the IC internal consumption should be considered. With no load the IC current draw is
0.0027A. Under this condition the output rise and fall times are faster than with a load. This could lead to an
almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,
these small current differences are buried in the high frequency switching spikes, and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10nF load is reasonably close to that
expected.
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for
power:
2
P + C V f + Q f
g
(2)
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage.
ENABLE
UCC27423/4/5 provides dual Enable inputs for improved control of each driver channel operation. The inputs
incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100kΩ resistor
for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when ENBA and
ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver and therefore
can be left open for standard operation. However, if the enable pin is left open, it is recommended to terminate
any PCB traces to be as short as possible to limit noise. If large noise is present due to non-optimal PCB layout,
it is recommended to tie the Enable pin to Vcc or to add a filter capacitor (0.1 µF) to the Enable pin. The output
states when the drivers are disabled is low regardless of the input state. See the truth table of Table 1 for the
operation using enable logic.
Enable input are compatible with both logic signals and slow changing analog signals. They can be directly
driven or a power-up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and
ENBB control input A and input B respectively.
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Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the IC package. In order for a power driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The UCC27423/4/5 family of drivers is available in three different packages to cover a range of
application requirements.
As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power
rating of around 0.5W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also
given in the table. Note that the power dissipation in our earlier example is 0.432W with a 10nF load, 12VDD,
switched at 300kHz. Thus, only one load of this size could be driven using the D or P package, even if the two
onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.
The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of
removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer
a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC
board directly underneath the IC package, reducing the θjc down to 4.7°C/W. Data is presented in Reference 3
to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the
standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking over
that available in the D or P packages, and is shown to more than double the power capability of the D and P
packages. Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is
electrically and thermally connected to the substrate which is the ground of the device.
References
1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments (SLUP133).
2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive
Circuits, by Bill Andreycak, Texas Instruments ( SLUA105)
3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments (SLMA002)
4. Application Brief, PowerPAD Made Easy, Texas Instruments (SLMA004)
Related Products
PRODUCT
UCC37323/4/5
UCC37321/2
DESCRIPTION
Dual 4-A Low-Side Drivers
PACKAGES
MSOP-8 PowerPAD, SOIC-8, PDIP-8
MSOP-8 PowerPAD, SOIC-8, PDIP-8
TSSOP-8, SOIC-8, PDIP-8
TSSOP-8, SOIC-8, PDIP-8
5-Pin SOT-23
Single 9-A Low-Side Driver with Enable
TPS2811/12/13
TPS2814/15
Dual 2-A Low-Side Drivers with Internal Regulator
Dual 2-A Low-Side Drivers with Two Inputs per Channel
Single 2-A Low-Side Driver with Internal Regulator
Single 2-A Low-Side Driver
TPS2816/17/18/19
TPS2828/29
5-Pin SOT-23
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY (VDD = 4.5V)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 8.0V)
100
80
100
80
10 nF
10 nF
4.7 nF
60
60
40
40
20
0
4.7 nF
2.2 nF
2.2 nF
1 nF
20
0
1 nF
470 pF
1.5 M
470 pF
0
500 K
1 M
1.5 M
2 M
0
500 K
1 M
2 M
f - Frequency - Hz
Figure 7.
f - Frequency - Hz
Figure 8.
SUPPLY CURRENT
vs
FREQUENCY (VDD = 12V)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 15V)
200
150
100
50
10 nF
4.7 nF
2.2 nF
1 nF
470 pF
1.5 M
0
0
500 K
1 M
2 M
f - Frequency - Hz
Figure 9.
Figure 10.
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SLUS545D –NOVEMBER 2002–REVISED MAY 2013
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (CLOAD = 2.2nF)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (CLOAD = 4.7nF)
160
140
120
100
80
90
80
70
2 MHz
2 MHz
60
50
40
30
20
10
1 MHz
1 MHz
60
500 kHz
500 kHz
200 kHz
40
200 kHz
20
100 kHz
50/20 kHz
100/50 kHz
14 16
0
0
4
4
9
14
19
6
8
10
12
V
DD
- Supply Voltage - V
V
DD
- Supply Voltage - V
Figure 11.
Figure 12.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (UCC27423)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (UCC27424)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE (UCC27425)
RISE TIME/FALL TIME
vs
TEMPERATURE (UCC27423)
0.75
0.70
0.65
25
20
tr
Input = V
DD
0.60
0.55
0.50
15
tf
10
5
Input = 0 V
0.45
0.40
0.35
0
0.30
-50
0
50
100
150
6
8
10
14
16
4
12
T
J
- Temperature - °C
V
DD
- Supply Voltage - V
Figure 15.
Figure 16.
RISE TIME
vs
SUPPLY VOLTAGE
FALL TIME
vs
SUPPLY VOLTAGE
Figure 17.
Figure 18.
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SLUS545D –NOVEMBER 2002–REVISED MAY 2013
TYPICAL CHARACTERISTICS (continued)
DELAY TIME (fD1)
vs
SUPPLY VOLTAGE (UCC27423)
DELAY TIME (fD2)
vs
SUPPLY VOLTAGE (UCC27423)
38
30
36
34
28
26
10 nF
10 nF
32
24
22
20
4.7 nF
30
28
4.7 nF
2.2 nF
18
16
14
26
2.2 nF
470 pF
1 nF
24
22
20
470 pF
1 nF
12
4
6
8
10
12
14
16
4
6
8
10 12
- Supply Voltage - V
14
16
V
DD
V
DD
- Supply Voltage - V
Figure 19.
Figure 20.
ENABLE THRESHOLD AND HYSTERESIS
ENABLE RESISTANCE
vs
vs
TEMPERATURE
TEMPERATURE
3.0
2.5
ENBL - ON
2.0
1.5
1.0
ENBL - OFF
0.5
ENBL - HYSTERESIS
0
-50
-25
0
25
50
75
100
125
T
J
- Temperature - °C
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT BEHAVIOR
vs
SUPPLY VOLTAGE (INVERTING)
OUTPUT BEHAVIOR
vs
SUPPLY VOLTAGE (INVERTING)
50 ms/div
50 ms/div
Figure 23.
Figure 24.
OUTPUT BEHAVIOR
vs
VDD (INVERTING)
OUTPUT BEHAVIOR
vs
VDD (INVERTING)
IN = V
DD
ENBL = V
DD
V
DD
OUT
0 V
10 nF Between Output and GND
50 ms/div
50 ms/div
Figure 25.
Figure 26.
16
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SLUS545D –NOVEMBER 2002–REVISED MAY 2013
TYPICAL CHARACTERISTICS (continued)
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
50 ms/div
50 ms/div
Figure 27.
Figure 28.
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
OUTPUT BEHAVIOR
vs
VDD (NON-INVERTING)
IN = GND
ENBL = VDD
VDD
OUT
0 V
10 nF Between Output and GND
50 ms/div
50 ms/div
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
INPUT THRESHOLD
vs
TEMPERATURE
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
V
= 15 V
DD
V
DD
= 10 V
V
DD
= 4.5 V
-50
-25
0
25
50
75
100
125
T
J
- Temperature - °C
Figure 31.
REVISION HISTORY
Changes from Revision B (November 2004) to Revision C
Page
•
•
•
•
•
Changed temperature rating. ................................................................................................................................................ 1
Changed ORDERING INFORMATION temperature range, three instances. ...................................................................... 2
Changed Output current (OUTA, OUTB) DC from 0.3 A to 0.2 A. ....................................................................................... 3
Changed ELECTRICAL CHARACTERISTICS temperature rating. ...................................................................................... 3
Changed Low-level output level from 40 mV max to 45 mV max. ....................................................................................... 3
Changes from Revision C (July, 2011) to Revision D
Page
•
•
•
Added ABSOLUTE MAXIMUM RATINGS note. ................................................................................................................... 3
Added Terminal Functions note. ........................................................................................................................................... 5
Added additional ENABLE pin description. ......................................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2013
PACKAGING INFORMATION
Orderable Device
UCC27423D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
27423
UCC27423DG4
UCC27423DGN
UCC27423DGNG4
UCC27423DGNR
UCC27423DGNRG4
UCC27423DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
DGN
DGN
DGN
DGN
D
75
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
27423
27423
27423
27423
27423
27423
27423
27423
27423
27424
27424
27424
27424
27424
27424
27424
MSOP-
PowerPAD
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
2500
2500
2500
2500
50
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
UCC27423DRG4
UCC27423P
D
Green (RoHS
& no Sb/Br)
P
Pb-Free
(RoHS)
UCC27423PE4
UCC27424D
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
UCC27424DG4
UCC27424DGN
UCC27424DGNG4
UCC27424DGNR
UCC27424DGNRG4
UCC27424DR
D
75
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
D
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
2500
2500
2500
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
UCC27424DRG4
UCC27424P
ACTIVE
SOIC
PDIP
PDIP
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
27424
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
P
P
50
50
Pb-Free
(RoHS)
27424
27424
27425
27425
27425
27425
27425
27425
27425
27425
27425
27425
UCC27424PE4
UCC27425D
Pb-Free
(RoHS)
D
75
Green (RoHS
& no Sb/Br)
UCC27425DG4
UCC27425DGN
UCC27425DGNG4
UCC27425DGNR
UCC27425DGNRG4
UCC27425DR
D
75
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
D
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
2500
2500
2500
2500
50
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
SOIC
SOIC
PDIP
PDIP
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
UCC27425DRG4
UCC27425P
D
Green (RoHS
& no Sb/Br)
P
Pb-Free
(RoHS)
UCC27425PE4
P
50
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27423, UCC27424, UCC27425 :
Automotive: UCC27423-Q1, UCC27424-Q1, UCC27425-Q1
•
Enhanced Product: UCC27423-EP, UCC27424-EP
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27423DGNR
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
UCC27423DR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
UCC27424DGNR
MSOP-
Power
PAD
DGN
UCC27424DR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
UCC27425DGNR
MSOP-
Power
PAD
DGN
UCC27425DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC27423DGNR
UCC27423DR
MSOP-PowerPAD
SOIC
DGN
D
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
364.0
340.5
364.0
340.5
364.0
340.5
364.0
338.1
364.0
338.1
364.0
338.1
27.0
20.6
27.0
20.6
27.0
20.6
UCC27424DGNR
UCC27424DR
MSOP-PowerPAD
SOIC
DGN
D
UCC27425DGNR
UCC27425DR
MSOP-PowerPAD
SOIC
DGN
D
Pack Materials-Page 2
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